common: Combine writes to SIM_CLKDIV1 in clock::configure_clkdiv().

By setting both CLKDIV1 and CLKDIV4 at the same time we avoid
running the flash at twice the intended clock rate for a couple
of cycles which has been observed to make it read bad data.

diff --git a/src/common/clock.rs b/src/common/clock.rs
index 86aa3efb884175e399aa4fe9e9269237f6f3c341..3d46016cb0558c86c45dc8483da96eb8ac932f17 100644 (file)
--- a/src/common/clock.rs
+++ b/src/common/clock.rs
@@ -78,8 +78,8 @@ const MCG_S_LOCK0: u8 = 1 << 6;
 fn configure_clkdiv() {
     let mut clkdiv1 = Reg32::new(SIM_CLKDIV1);
 
-    clkdiv1.write(1 << SIM_CLKDIV1_OUTDIV4_SHIFT);
-    clkdiv1.modify(|v| v | (1 << SIM_CLKDIV1_OUTDIV1_SHIFT));
+    clkdiv1.write((1 << SIM_CLKDIV1_OUTDIV4_SHIFT)
+                | (1 << SIM_CLKDIV1_OUTDIV1_SHIFT));
 }
 
 fn switch_to_fbe() {