From d6f292a7c11479db134403df91fb152f0ffd1b9b Mon Sep 17 00:00:00 2001 From: Tilman Sauerbeck Date: Sat, 16 Nov 2019 21:54:50 +0100 Subject: [PATCH] common: Combine writes to SIM_CLKDIV1 in clock::configure_clkdiv(). By setting both CLKDIV1 and CLKDIV4 at the same time we avoid running the flash at twice the intended clock rate for a couple of cycles which has been observed to make it read bad data. --- src/common/clock.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/common/clock.rs b/src/common/clock.rs index 86aa3ef..3d46016 100644 --- a/src/common/clock.rs +++ b/src/common/clock.rs @@ -78,8 +78,8 @@ const MCG_S_LOCK0: u8 = 1 << 6; fn configure_clkdiv() { let mut clkdiv1 = Reg32::new(SIM_CLKDIV1); - clkdiv1.write(1 << SIM_CLKDIV1_OUTDIV4_SHIFT); - clkdiv1.modify(|v| v | (1 << SIM_CLKDIV1_OUTDIV1_SHIFT)); + clkdiv1.write((1 << SIM_CLKDIV1_OUTDIV4_SHIFT) + | (1 << SIM_CLKDIV1_OUTDIV1_SHIFT)); } fn switch_to_fbe() { -- 2.30.2