common: Implement port::init().

This function powers up ports A, B, C, D and E.

diff --git a/src/common/port.rs b/src/common/port.rs
index 0dc95a818c6a70329c4ef639586703d57336ce37..32f8c26709279e63c9f6037d9d2b56b274f69a11 100644 (file)
--- a/src/common/port.rs
+++ b/src/common/port.rs
@@ -33,12 +33,20 @@ pub const PORTC: u32 = PORT_BASE + 0x2000;
 pub const PORTD: u32 = PORT_BASE + 0x3000;
 pub const PORTE: u32 = PORT_BASE + 0x4000;
 
+const SIM_SCGC5: u32 = 0x40048038;
+
 const PORT_PCR_MUX_SHIFT: u32 = 8;
 const PORT_PCR_MUX_MASK: u32 = 3 << PORT_PCR_MUX_SHIFT;
 
 const PORT_PCR_PE: u32 = 1 << 1;
 const PORT_PCR_PS: u32 = 1 << 0;
 
+const SIM_SCGC5_PORTA: u32 = 1 << 9;
+const SIM_SCGC5_PORTB: u32 = 1 << 10;
+const SIM_SCGC5_PORTC: u32 = 1 << 11;
+const SIM_SCGC5_PORTD: u32 = 1 << 12;
+const SIM_SCGC5_PORTE: u32 = 1 << 13;
+
 pub enum Pull {
     None,
     Up,
@@ -49,6 +57,19 @@ fn pcr_offset(pin: u32) -> u32 {
     pin * 4
 }
 
+pub fn init() {
+    let mut scgc5 = Reg32::new(SIM_SCGC5);
+
+    scgc5.modify(|v| {
+          v
+        | SIM_SCGC5_PORTA
+        | SIM_SCGC5_PORTB
+        | SIM_SCGC5_PORTC
+        | SIM_SCGC5_PORTD
+        | SIM_SCGC5_PORTE
+    });
+}
+
 pub fn set_af(port: u32, pin: u32, af: u32) {
     let mut pcr = Reg32::new(port + pcr_offset(pin));