Add an extra sample to the logic edges so that the end sample is visible

[pulseview.git] / pv / data / logicsnapshot.cpp

diff --git a/pv/data/logicsnapshot.cpp b/pv/data/logicsnapshot.cpp
index f2fa81bcdde675fa9811977a32261be129687b75..f203e8b674fb57fb37c556edc593c5e1798873a8 100644 (file)
--- a/pv/data/logicsnapshot.cpp
+++ b/pv/data/logicsnapshot.cpp
@@ -78,9 +78,9 @@ void LogicSnapshot::get_samples(uint8_t *const data,
 {
        assert(data);
        assert(start_sample >= 0);
-       assert(start_sample < (int64_t)_sample_count);
+       assert(start_sample <= (int64_t)_sample_count);
        assert(end_sample >= 0);
-       assert(end_sample < (int64_t)_sample_count);
+       assert(end_sample <= (int64_t)_sample_count);
        assert(start_sample <= end_sample);
 
        lock_guard<recursive_mutex> lock(_mutex);
@@ -366,8 +366,10 @@ void LogicSnapshot::get_subsampled_edges(
        }
 
        // Add the final state
-       edges.push_back(pair<int64_t, bool>(end,
-               get_sample(end) & sig_mask));
+       const bool end_sample = get_sample(end) & sig_mask;
+       if (last_sample != end_sample)
+               edges.push_back(pair<int64_t, bool>(end, end_sample));
+       edges.push_back(pair<int64_t, bool>(end + 1, end_sample));
 }
 
 uint64_t LogicSnapshot::get_subsample(int level, uint64_t offset) const