--- /dev/null
+/*
+ * Copyright (c) 2019 Tilman Sauerbeck (tilman at code-monkey de)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+use register;
+
+type Reg8 = register::Register<u8>;
+type Reg32 = register::Register<u32>;
+
+const I2C_BASE: u32 = 0x40066000;
+
+pub const I2C0: u32 = I2C_BASE + 0x0000;
+pub const I2C1: u32 = I2C_BASE + 0x1000;
+
+const SIM_SCGC4: u32 = 0x40048034;
+
+const SIM_SCGC4_I2C0: u32 = 1 << 6;
+const SIM_SCGC4_I2C1: u32 = 1 << 7;
+
+const I2C_F : u32 = 0x01;
+const I2C_C1 : u32 = 0x02;
+const I2C_S1 : u32 = 0x03;
+const I2C_D : u32 = 0x04;
+
+const I2C_C1_TX : u8 = 1 << 4;
+const I2C_C1_MST : u8 = 1 << 5;
+const I2C_C1_IICEN: u8 = 1 << 7;
+
+const I2C_S1_IICIF: u8 = 1 << 1;
+
+const I2C_F_ICR_SHIFT: u8 = 0;
+
+pub fn configure(i2c: u32) {
+ {
+ let mut scgc4 = Reg32::new(SIM_SCGC4);
+
+ if i2c == I2C0 {
+ scgc4.modify(|v| v | SIM_SCGC4_I2C0);
+ } else {
+ scgc4.modify(|v| v | SIM_SCGC4_I2C1);
+ }
+ }
+
+ let mut f = Reg8::new(i2c + I2C_F);
+ f.write(0x12 << I2C_F_ICR_SHIFT);
+
+ let mut c1 = Reg8::new(i2c + I2C_C1);
+ c1.write(I2C_C1_IICEN);
+}
+
+fn prepare_tx(i2c: u32, slave_address: u8) {
+ let mut c1 = Reg8::new(i2c + I2C_C1);
+
+ c1.modify(|v| v | I2C_C1_TX);
+ c1.modify(|v| v | I2C_C1_MST);
+
+ let mut d = Reg8::new(i2c + I2C_D);
+ d.write((slave_address << 1) | 0);
+}
+
+fn finish_tx(i2c: u32) {
+ let mut c1 = Reg8::new(i2c + I2C_C1);
+
+ c1.modify(|v| v & !I2C_C1_MST);
+ c1.modify(|v| v & !I2C_C1_TX);
+}
+
+fn wait_for_and_ack_interrupt(i2c: u32) {
+ let mut s1 = Reg8::new(i2c + I2C_S1);
+
+ // Wait for interrupt to occur.
+ while (s1.read() & I2C_S1_IICIF) == 0 {
+ }
+
+ // Acknowledge interrupt.
+ s1.modify(|v| v | I2C_S1_IICIF);
+}
+
+fn tx(i2c: u32, data: u8) {
+ wait_for_and_ack_interrupt(i2c);
+
+ let mut d = Reg8::new(i2c + I2C_D);
+ d.write(data);
+}
+
+pub fn tx16(i2c: u32, slave_address: u8, data: u16) {
+ prepare_tx(i2c, slave_address);
+
+ tx(i2c, (data >> 0) as u8);
+ tx(i2c, (data >> 8) as u8);
+
+ wait_for_and_ack_interrupt(i2c);
+
+ finish_tx(i2c);
+}