This does not yet build.
source_files_c = [
'src/common/startup.c',
+ 'src/common/usb_device_ch9.c',
+ 'src/common/usb_device_dci.c',
+ 'src/common/usb_device_descriptor.c',
+ 'src/common/usb_device_khci.c',
+ 'src/common/usb_osa_bm.c',
+ 'src/common/virtual_com.c',
]
libcommon_rlib = env.Rustc('libcommon.rlib', source_files_rs[0])
--- /dev/null
+/*
+** ###################################################################
+** Processors: MKL26Z128CAL4
+** MKL26Z128VFM4
+** MKL26Z128VFT4
+** MKL26Z128VLH4
+** MKL26Z128VLL4
+** MKL26Z128VMC4
+** MKL26Z256VLH4
+** MKL26Z256VLL4
+** MKL26Z256VMC4
+** MKL26Z256VMP4
+** MKL26Z32VFM4
+** MKL26Z32VFT4
+** MKL26Z32VLH4
+** MKL26Z64VFM4
+** MKL26Z64VFT4
+** MKL26Z64VLH4
+**
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** MCUXpresso Compiler
+**
+** Reference manuals: KL26P121M48SF4RM Rev. 3.2, October 2013
+** KL26P121M48SF4RM, Rev.2, Dec 2012
+**
+** Version: rev. 1.8, 2015-07-29
+** Build: b171205
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MKL26Z4
+**
+** The Clear BSD License
+** Copyright 1997-2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2017 NXP
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without
+** modification, are permitted (subject to the limitations in the
+** disclaimer below) provided that the following conditions are met:
+**
+** * Redistributions of source code must retain the above copyright
+** notice, this list of conditions and the following disclaimer.
+**
+** * Redistributions in binary form must reproduce the above copyright
+** notice, this list of conditions and the following disclaimer in the
+** documentation and/or other materials provided with the distribution.
+**
+** * Neither the name of the copyright holder nor the names of its
+** contributors may be used to endorse or promote products derived from
+** this software without specific prior written permission.
+**
+** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2012-12-12)
+** Initial version.
+** - rev. 1.1 (2013-04-05)
+** Changed start of doxygen comment.
+** - rev. 1.2 (2013-04-12)
+** SystemInit function fixed for clock configuration 1.
+** Name of the interrupt num. 31 updated to reflect proper function.
+** - rev. 1.3 (2014-05-27)
+** Updated to Kinetis SDK support standard.
+** MCG OSC clock select supported (MCG_C7[OSCSEL]).
+** - rev. 1.4 (2014-07-25)
+** System initialization updated:
+** - Prefix added to the system initialization parameterization constants to avoid name conflicts..
+** - VLLSx wake-up recovery added.
+** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes.
+** - rev. 1.5 (2014-08-28)
+** Update of system files - default clock configuration changed, fix of OSC initialization.
+** Update of startup files - possibility to override DefaultISR added.
+** - rev. 1.6 (2014-10-14)
+** Renamed interrupt vector LPTimer to LPTMR0
+** - rev. 1.7 (2015-02-18)
+** Renamed interrupt vector LLW to LLWU
+** - rev. 1.8 (2015-07-29)
+** Correction of backward compatibility.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL26Z4.h
+ * @version 1.8
+ * @date 2015-07-29
+ * @brief CMSIS Peripheral Access Layer for MKL26Z4
+ *
+ * CMSIS Peripheral Access Layer for MKL26Z4
+ */
+
+#ifndef _MKL26Z4_H_
+#define _MKL26Z4_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0008U
+
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+ /* Auxiliary constants */
+ NotAvail_IRQn = -128, /**< Not available device specific interrupt */
+
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA channel 0 transfer complete and error interrupt */
+ DMA1_IRQn = 1, /**< DMA channel 1 transfer complete and error interrupt */
+ DMA2_IRQn = 2, /**< DMA channel 2 transfer complete and error interrupt */
+ DMA3_IRQn = 3, /**< DMA channel 3 transfer complete and error interrupt */
+ Reserved20_IRQn = 4, /**< Reserved interrupt */
+ FTFA_IRQn = 5, /**< FTFA command complete and read collision */
+ LVD_LVW_IRQn = 6, /**< Low-voltage detect, low-voltage warning */
+ LLWU_IRQn = 7, /**< Low Leakage Wakeup */
+ I2C0_IRQn = 8, /**< I2C0 interrupt */
+ I2C1_IRQn = 9, /**< I2C1 interrupt */
+ SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
+ SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */
+ UART0_IRQn = 12, /**< UART0 status and error */
+ UART1_IRQn = 13, /**< UART1 status and error */
+ UART2_IRQn = 14, /**< UART2 status and error */
+ ADC0_IRQn = 15, /**< ADC0 interrupt */
+ CMP0_IRQn = 16, /**< CMP0 interrupt */
+ TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
+ TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
+ TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
+ RTC_IRQn = 20, /**< RTC alarm interrupt */
+ RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
+ PIT_IRQn = 22, /**< PIT single interrupt vector for all channels */
+ I2S0_IRQn = 23, /**< I2S0 Single interrupt vector for all sources */
+ USB0_IRQn = 24, /**< USB0 OTG */
+ DAC0_IRQn = 25, /**< DAC0 interrupt */
+ TSI0_IRQn = 26, /**< TSI0 interrupt */
+ MCG_IRQn = 27, /**< MCG interrupt */
+ LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */
+ Reserved45_IRQn = 29, /**< Reserved interrupt */
+ PORTA_IRQn = 30, /**< PORTA pin detect */
+ PORTC_PORTD_IRQn = 31 /**< Single interrupt vector for PORTC and PORTD pin detect */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M0 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */
+#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm0plus.h" /* Core Peripheral Access Layer */
+#include "system_MKL26Z4.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Mapping Information
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+ kDmaRequestMux0Disable = 0|0x100U, /**< Disable */
+ kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
+ kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 receive complete */
+ kDmaRequestMux0LPSCI0Rx = 2|0x100U, /**< UART0 receive complete */
+ kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 transmit complete */
+ kDmaRequestMux0LPSCI0Tx = 3|0x100U, /**< UART0 transmit complete */
+ kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 receive complete */
+ kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 transmit complete */
+ kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 receive complete */
+ kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 transmit complete */
+ kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */
+ kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */
+ kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */
+ kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */
+ kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */
+ kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */
+ kDmaRequestMux0I2S0Rx = 14|0x100U, /**< I2S0 receive complete */
+ kDmaRequestMux0I2S0Tx = 15|0x100U, /**< I2S0 transmit complete */
+ kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 receive complete */
+ kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 transmit complete */
+ kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 receive complete */
+ kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 transmit complete */
+ kDmaRequestMux0Reserved20 = 20|0x100U, /**< Reserved20 */
+ kDmaRequestMux0Reserved21 = 21|0x100U, /**< Reserved21 */
+ kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0 transmission complete */
+ kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1 transmission complete */
+ kDmaRequestMux0TPM0Channel0 = 24|0x100U, /**< TPM0 channel 0 event (CMP or CAP) */
+ kDmaRequestMux0TPM0Channel1 = 25|0x100U, /**< TPM0 channel 1 event (CMP or CAP) */
+ kDmaRequestMux0TPM0Channel2 = 26|0x100U, /**< TPM0 channel 2 event (CMP or CAP) */
+ kDmaRequestMux0TPM0Channel3 = 27|0x100U, /**< TPM0 channel 3 event (CMP or CAP) */
+ kDmaRequestMux0TPM0Channel4 = 28|0x100U, /**< TPM0 channel 4 event (CMP or CAP) */
+ kDmaRequestMux0TPM0Channel5 = 29|0x100U, /**< TPM0 channel 5 event (CMP or CAP) */
+ kDmaRequestMux0Reserved30 = 30|0x100U, /**< Reserved30 */
+ kDmaRequestMux0Reserved31 = 31|0x100U, /**< Reserved31 */
+ kDmaRequestMux0TPM1Channel0 = 32|0x100U, /**< TPM1 channel 0 event (CMP or CAP) */
+ kDmaRequestMux0TPM1Channel1 = 33|0x100U, /**< TPM1 channel 1 event (CMP or CAP) */
+ kDmaRequestMux0TPM2Channel0 = 34|0x100U, /**< TPM2 channel 0 event (CMP or CAP) */
+ kDmaRequestMux0TPM2Channel1 = 35|0x100U, /**< TPM2 channel 1 event (CMP or CAP) */
+ kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */
+ kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */
+ kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */
+ kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */
+ kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0 conversion complete */
+ kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */
+ kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0 Output */
+ kDmaRequestMux0Reserved43 = 43|0x100U, /**< Reserved43 */
+ kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */
+ kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0 buffer pointer reaches upper or lower limit */
+ kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */
+ kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */
+ kDmaRequestMux0Reserved48 = 48|0x100U, /**< Reserved48 */
+ kDmaRequestMux0PortA = 49|0x100U, /**< PORTA rising, falling or both edges */
+ kDmaRequestMux0Reserved50 = 50|0x100U, /**< Reserved50 */
+ kDmaRequestMux0PortC = 51|0x100U, /**< PORTC rising, falling or both edges */
+ kDmaRequestMux0PortD = 52|0x100U, /**< PORTD rising, falling or both edges */
+ kDmaRequestMux0Reserved53 = 53|0x100U, /**< Reserved53 */
+ kDmaRequestMux0TPM0Overflow = 54|0x100U, /**< TPM0 overflow */
+ kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< TPM1 overflow */
+ kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< TPM2 overflow */
+ kDmaRequestMux0TSI = 57|0x100U, /**< TSI0 event */
+ kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */
+ kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */
+ kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< Always enabled 60 */
+ kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< Always enabled 61 */
+ kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< Always enabled 62 */
+ kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< Always enabled 63 */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #else
+ #pragma push
+ #pragma anon_unions
+ #endif
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name SC1 - ADC Status and Control Registers 1 */
+#define ADC_SC1_ADCH_MASK (0x1FU)
+#define ADC_SC1_ADCH_SHIFT (0U)
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK (0x20U)
+#define ADC_SC1_DIFF_SHIFT (5U)
+#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
+#define ADC_SC1_AIEN_MASK (0x40U)
+#define ADC_SC1_AIEN_SHIFT (6U)
+#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK (0x80U)
+#define ADC_SC1_COCO_SHIFT (7U)
+#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
+
+/* The count of ADC_SC1 */
+#define ADC_SC1_COUNT (2U)
+
+/*! @name CFG1 - ADC Configuration Register 1 */
+#define ADC_CFG1_ADICLK_MASK (0x3U)
+#define ADC_CFG1_ADICLK_SHIFT (0U)
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK (0xCU)
+#define ADC_CFG1_MODE_SHIFT (2U)
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK (0x10U)
+#define ADC_CFG1_ADLSMP_SHIFT (4U)
+#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
+#define ADC_CFG1_ADIV_MASK (0x60U)
+#define ADC_CFG1_ADIV_SHIFT (5U)
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK (0x80U)
+#define ADC_CFG1_ADLPC_SHIFT (7U)
+#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
+
+/*! @name CFG2 - ADC Configuration Register 2 */
+#define ADC_CFG2_ADLSTS_MASK (0x3U)
+#define ADC_CFG2_ADLSTS_SHIFT (0U)
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK (0x4U)
+#define ADC_CFG2_ADHSC_SHIFT (2U)
+#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
+#define ADC_CFG2_ADACKEN_MASK (0x8U)
+#define ADC_CFG2_ADACKEN_SHIFT (3U)
+#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
+#define ADC_CFG2_MUXSEL_MASK (0x10U)
+#define ADC_CFG2_MUXSEL_SHIFT (4U)
+#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
+
+/*! @name R - ADC Data Result Register */
+#define ADC_R_D_MASK (0xFFFFU)
+#define ADC_R_D_SHIFT (0U)
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
+
+/* The count of ADC_R */
+#define ADC_R_COUNT (2U)
+
+/*! @name CV1 - Compare Value Registers */
+#define ADC_CV1_CV_MASK (0xFFFFU)
+#define ADC_CV1_CV_SHIFT (0U)
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
+
+/*! @name CV2 - Compare Value Registers */
+#define ADC_CV2_CV_MASK (0xFFFFU)
+#define ADC_CV2_CV_SHIFT (0U)
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
+
+/*! @name SC2 - Status and Control Register 2 */
+#define ADC_SC2_REFSEL_MASK (0x3U)
+#define ADC_SC2_REFSEL_SHIFT (0U)
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK (0x4U)
+#define ADC_SC2_DMAEN_SHIFT (2U)
+#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK (0x8U)
+#define ADC_SC2_ACREN_SHIFT (3U)
+#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK (0x10U)
+#define ADC_SC2_ACFGT_SHIFT (4U)
+#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK (0x20U)
+#define ADC_SC2_ACFE_SHIFT (5U)
+#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK (0x40U)
+#define ADC_SC2_ADTRG_SHIFT (6U)
+#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK (0x80U)
+#define ADC_SC2_ADACT_SHIFT (7U)
+#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
+
+/*! @name SC3 - Status and Control Register 3 */
+#define ADC_SC3_AVGS_MASK (0x3U)
+#define ADC_SC3_AVGS_SHIFT (0U)
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK (0x4U)
+#define ADC_SC3_AVGE_SHIFT (2U)
+#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK (0x8U)
+#define ADC_SC3_ADCO_SHIFT (3U)
+#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CALF_MASK (0x40U)
+#define ADC_SC3_CALF_SHIFT (6U)
+#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
+#define ADC_SC3_CAL_MASK (0x80U)
+#define ADC_SC3_CAL_SHIFT (7U)
+#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
+
+/*! @name OFS - ADC Offset Correction Register */
+#define ADC_OFS_OFS_MASK (0xFFFFU)
+#define ADC_OFS_OFS_SHIFT (0U)
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
+
+/*! @name PG - ADC Plus-Side Gain Register */
+#define ADC_PG_PG_MASK (0xFFFFU)
+#define ADC_PG_PG_SHIFT (0U)
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
+
+/*! @name MG - ADC Minus-Side Gain Register */
+#define ADC_MG_MG_MASK (0xFFFFU)
+#define ADC_MG_MG_SHIFT (0U)
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
+
+/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLPD_CLPD_MASK (0x3FU)
+#define ADC_CLPD_CLPD_SHIFT (0U)
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
+
+/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLPS_CLPS_MASK (0x3FU)
+#define ADC_CLPS_CLPS_SHIFT (0U)
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
+
+/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP4_CLP4_MASK (0x3FFU)
+#define ADC_CLP4_CLP4_SHIFT (0U)
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
+
+/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP3_CLP3_MASK (0x1FFU)
+#define ADC_CLP3_CLP3_SHIFT (0U)
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
+
+/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP2_CLP2_MASK (0xFFU)
+#define ADC_CLP2_CLP2_SHIFT (0U)
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
+
+/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP1_CLP1_MASK (0x7FU)
+#define ADC_CLP1_CLP1_SHIFT (0U)
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
+
+/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP0_CLP0_MASK (0x3FU)
+#define ADC_CLP0_CLP0_SHIFT (0U)
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
+
+/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLMD_CLMD_MASK (0x3FU)
+#define ADC_CLMD_CLMD_SHIFT (0U)
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
+
+/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLMS_CLMS_MASK (0x3FU)
+#define ADC_CLMS_CLMS_SHIFT (0U)
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
+
+/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM4_CLM4_MASK (0x3FFU)
+#define ADC_CLM4_CLM4_SHIFT (0U)
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
+
+/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM3_CLM3_MASK (0x1FFU)
+#define ADC_CLM3_CLM3_SHIFT (0U)
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
+
+/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM2_CLM2_MASK (0xFFU)
+#define ADC_CLM2_CLM2_SHIFT (0U)
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
+
+/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM1_CLM1_MASK (0x7FU)
+#define ADC_CLM1_CLM1_SHIFT (0U)
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
+
+/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM0_CLM0_MASK (0x3FU)
+#define ADC_CLM0_CLM0_SHIFT (0U)
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS { ADC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/*! @name CR0 - CMP Control Register 0 */
+#define CMP_CR0_HYSTCTR_MASK (0x3U)
+#define CMP_CR0_HYSTCTR_SHIFT (0U)
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK (0x70U)
+#define CMP_CR0_FILTER_CNT_SHIFT (4U)
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
+
+/*! @name CR1 - CMP Control Register 1 */
+#define CMP_CR1_EN_MASK (0x1U)
+#define CMP_CR1_EN_SHIFT (0U)
+#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK (0x2U)
+#define CMP_CR1_OPE_SHIFT (1U)
+#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK (0x4U)
+#define CMP_CR1_COS_SHIFT (2U)
+#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK (0x8U)
+#define CMP_CR1_INV_SHIFT (3U)
+#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK (0x10U)
+#define CMP_CR1_PMODE_SHIFT (4U)
+#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
+#define CMP_CR1_TRIGM_MASK (0x20U)
+#define CMP_CR1_TRIGM_SHIFT (5U)
+#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
+#define CMP_CR1_WE_MASK (0x40U)
+#define CMP_CR1_WE_SHIFT (6U)
+#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK (0x80U)
+#define CMP_CR1_SE_SHIFT (7U)
+#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
+
+/*! @name FPR - CMP Filter Period Register */
+#define CMP_FPR_FILT_PER_MASK (0xFFU)
+#define CMP_FPR_FILT_PER_SHIFT (0U)
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
+
+/*! @name SCR - CMP Status and Control Register */
+#define CMP_SCR_COUT_MASK (0x1U)
+#define CMP_SCR_COUT_SHIFT (0U)
+#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK (0x2U)
+#define CMP_SCR_CFF_SHIFT (1U)
+#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK (0x4U)
+#define CMP_SCR_CFR_SHIFT (2U)
+#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK (0x8U)
+#define CMP_SCR_IEF_SHIFT (3U)
+#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK (0x10U)
+#define CMP_SCR_IER_SHIFT (4U)
+#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK (0x40U)
+#define CMP_SCR_DMAEN_SHIFT (6U)
+#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
+
+/*! @name DACCR - DAC Control Register */
+#define CMP_DACCR_VOSEL_MASK (0x3FU)
+#define CMP_DACCR_VOSEL_SHIFT (0U)
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK (0x40U)
+#define CMP_DACCR_VRSEL_SHIFT (6U)
+#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK (0x80U)
+#define CMP_DACCR_DACEN_SHIFT (7U)
+#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
+
+/*! @name MUXCR - MUX Control Register */
+#define CMP_MUXCR_MSEL_MASK (0x7U)
+#define CMP_MUXCR_MSEL_SHIFT (0U)
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK (0x38U)
+#define CMP_MUXCR_PSEL_SHIFT (3U)
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK (0x80U)
+#define CMP_MUXCR_PSTM_SHIFT (7U)
+#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS { CMP0_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS { CMP0 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS { CMP0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[2];
+ uint8_t RESERVED_0[28];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/*! @name DATL - DAC Data Low Register */
+#define DAC_DATL_DATA0_MASK (0xFFU)
+#define DAC_DATL_DATA0_SHIFT (0U)
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
+
+/* The count of DAC_DATL */
+#define DAC_DATL_COUNT (2U)
+
+/*! @name DATH - DAC Data High Register */
+#define DAC_DATH_DATA1_MASK (0xFU)
+#define DAC_DATH_DATA1_SHIFT (0U)
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
+
+/* The count of DAC_DATH */
+#define DAC_DATH_COUNT (2U)
+
+/*! @name SR - DAC Status Register */
+#define DAC_SR_DACBFRPBF_MASK (0x1U)
+#define DAC_SR_DACBFRPBF_SHIFT (0U)
+#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPTF_MASK (0x2U)
+#define DAC_SR_DACBFRPTF_SHIFT (1U)
+#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
+
+/*! @name C0 - DAC Control Register */
+#define DAC_C0_DACBBIEN_MASK (0x1U)
+#define DAC_C0_DACBBIEN_SHIFT (0U)
+#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBTIEN_MASK (0x2U)
+#define DAC_C0_DACBTIEN_SHIFT (1U)
+#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_LPEN_MASK (0x8U)
+#define DAC_C0_LPEN_SHIFT (3U)
+#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
+#define DAC_C0_DACSWTRG_MASK (0x10U)
+#define DAC_C0_DACSWTRG_SHIFT (4U)
+#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACTRGSEL_MASK (0x20U)
+#define DAC_C0_DACTRGSEL_SHIFT (5U)
+#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACRFS_MASK (0x40U)
+#define DAC_C0_DACRFS_SHIFT (6U)
+#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACEN_MASK (0x80U)
+#define DAC_C0_DACEN_SHIFT (7U)
+#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
+
+/*! @name C1 - DAC Control Register 1 */
+#define DAC_C1_DACBFEN_MASK (0x1U)
+#define DAC_C1_DACBFEN_SHIFT (0U)
+#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFMD_MASK (0x4U)
+#define DAC_C1_DACBFMD_SHIFT (2U)
+#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DMAEN_MASK (0x80U)
+#define DAC_C1_DMAEN_SHIFT (7U)
+#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
+
+/*! @name C2 - DAC Control Register 2 */
+#define DAC_C2_DACBFUP_MASK (0x1U)
+#define DAC_C2_DACBFUP_SHIFT (0U)
+#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK (0x10U)
+#define DAC_C2_DACBFRP_SHIFT (4U)
+#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x4003F000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS { DAC0_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS { DAC0 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS { DAC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[256];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
+ __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
+ union { /* offset: 0x108, array step: 0x10 */
+ __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
+ struct { /* offset: 0x108, array step: 0x10 */
+ uint8_t RESERVED_0[3];
+ uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
+ } DMA_DSR_ACCESS8BIT;
+ };
+ __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
+ } DMA[4];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name SAR - Source Address Register */
+#define DMA_SAR_SAR_MASK (0xFFFFFFFFU)
+#define DMA_SAR_SAR_SHIFT (0U)
+#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SAR_SAR_SHIFT)) & DMA_SAR_SAR_MASK)
+
+/* The count of DMA_SAR */
+#define DMA_SAR_COUNT (4U)
+
+/*! @name DAR - Destination Address Register */
+#define DMA_DAR_DAR_MASK (0xFFFFFFFFU)
+#define DMA_DAR_DAR_SHIFT (0U)
+#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DAR_DAR_SHIFT)) & DMA_DAR_DAR_MASK)
+
+/* The count of DMA_DAR */
+#define DMA_DAR_COUNT (4U)
+
+/*! @name DSR_BCR - DMA Status Register / Byte Count Register */
+#define DMA_DSR_BCR_BCR_MASK (0xFFFFFFU)
+#define DMA_DSR_BCR_BCR_SHIFT (0U)
+#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BCR_SHIFT)) & DMA_DSR_BCR_BCR_MASK)
+#define DMA_DSR_BCR_DONE_MASK (0x1000000U)
+#define DMA_DSR_BCR_DONE_SHIFT (24U)
+#define DMA_DSR_BCR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_DONE_SHIFT)) & DMA_DSR_BCR_DONE_MASK)
+#define DMA_DSR_BCR_BSY_MASK (0x2000000U)
+#define DMA_DSR_BCR_BSY_SHIFT (25U)
+#define DMA_DSR_BCR_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BSY_SHIFT)) & DMA_DSR_BCR_BSY_MASK)
+#define DMA_DSR_BCR_REQ_MASK (0x4000000U)
+#define DMA_DSR_BCR_REQ_SHIFT (26U)
+#define DMA_DSR_BCR_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_REQ_SHIFT)) & DMA_DSR_BCR_REQ_MASK)
+#define DMA_DSR_BCR_BED_MASK (0x10000000U)
+#define DMA_DSR_BCR_BED_SHIFT (28U)
+#define DMA_DSR_BCR_BED(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BED_SHIFT)) & DMA_DSR_BCR_BED_MASK)
+#define DMA_DSR_BCR_BES_MASK (0x20000000U)
+#define DMA_DSR_BCR_BES_SHIFT (29U)
+#define DMA_DSR_BCR_BES(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BES_SHIFT)) & DMA_DSR_BCR_BES_MASK)
+#define DMA_DSR_BCR_CE_MASK (0x40000000U)
+#define DMA_DSR_BCR_CE_SHIFT (30U)
+#define DMA_DSR_BCR_CE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_CE_SHIFT)) & DMA_DSR_BCR_CE_MASK)
+
+/* The count of DMA_DSR_BCR */
+#define DMA_DSR_BCR_COUNT (4U)
+
+/* The count of DMA_DSR */
+#define DMA_DSR_COUNT (4U)
+
+/*! @name DCR - DMA Control Register */
+#define DMA_DCR_LCH2_MASK (0x3U)
+#define DMA_DCR_LCH2_SHIFT (0U)
+#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH2_SHIFT)) & DMA_DCR_LCH2_MASK)
+#define DMA_DCR_LCH1_MASK (0xCU)
+#define DMA_DCR_LCH1_SHIFT (2U)
+#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH1_SHIFT)) & DMA_DCR_LCH1_MASK)
+#define DMA_DCR_LINKCC_MASK (0x30U)
+#define DMA_DCR_LINKCC_SHIFT (4U)
+#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LINKCC_SHIFT)) & DMA_DCR_LINKCC_MASK)
+#define DMA_DCR_D_REQ_MASK (0x80U)
+#define DMA_DCR_D_REQ_SHIFT (7U)
+#define DMA_DCR_D_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_D_REQ_SHIFT)) & DMA_DCR_D_REQ_MASK)
+#define DMA_DCR_DMOD_MASK (0xF00U)
+#define DMA_DCR_DMOD_SHIFT (8U)
+#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DMOD_SHIFT)) & DMA_DCR_DMOD_MASK)
+#define DMA_DCR_SMOD_MASK (0xF000U)
+#define DMA_DCR_SMOD_SHIFT (12U)
+#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SMOD_SHIFT)) & DMA_DCR_SMOD_MASK)
+#define DMA_DCR_START_MASK (0x10000U)
+#define DMA_DCR_START_SHIFT (16U)
+#define DMA_DCR_START(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_START_SHIFT)) & DMA_DCR_START_MASK)
+#define DMA_DCR_DSIZE_MASK (0x60000U)
+#define DMA_DCR_DSIZE_SHIFT (17U)
+#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DSIZE_SHIFT)) & DMA_DCR_DSIZE_MASK)
+#define DMA_DCR_DINC_MASK (0x80000U)
+#define DMA_DCR_DINC_SHIFT (19U)
+#define DMA_DCR_DINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DINC_SHIFT)) & DMA_DCR_DINC_MASK)
+#define DMA_DCR_SSIZE_MASK (0x300000U)
+#define DMA_DCR_SSIZE_SHIFT (20U)
+#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SSIZE_SHIFT)) & DMA_DCR_SSIZE_MASK)
+#define DMA_DCR_SINC_MASK (0x400000U)
+#define DMA_DCR_SINC_SHIFT (22U)
+#define DMA_DCR_SINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SINC_SHIFT)) & DMA_DCR_SINC_MASK)
+#define DMA_DCR_EADREQ_MASK (0x800000U)
+#define DMA_DCR_EADREQ_SHIFT (23U)
+#define DMA_DCR_EADREQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EADREQ_SHIFT)) & DMA_DCR_EADREQ_MASK)
+#define DMA_DCR_AA_MASK (0x10000000U)
+#define DMA_DCR_AA_SHIFT (28U)
+#define DMA_DCR_AA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_AA_SHIFT)) & DMA_DCR_AA_MASK)
+#define DMA_DCR_CS_MASK (0x20000000U)
+#define DMA_DCR_CS_SHIFT (29U)
+#define DMA_DCR_CS(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_CS_SHIFT)) & DMA_DCR_CS_MASK)
+#define DMA_DCR_ERQ_MASK (0x40000000U)
+#define DMA_DCR_ERQ_SHIFT (30U)
+#define DMA_DCR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_ERQ_SHIFT)) & DMA_DCR_ERQ_MASK)
+#define DMA_DCR_EINT_MASK (0x80000000U)
+#define DMA_DCR_EINT_SHIFT (31U)
+#define DMA_DCR_EINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EINT_SHIFT)) & DMA_DCR_EINT_MASK)
+
+/* The count of DMA_DCR */
+#define DMA_DCR_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/*! @name CHCFG - Channel Configuration register */
+#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
+#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
+#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
+#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
+#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
+#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
+
+/* The count of DMAMUX_CHCFG */
+#define DMAMUX_CHCFG_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX0 base address */
+#define DMAMUX0_BASE (0x40021000u)
+/** Peripheral DMAMUX0 base pointer */
+#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS { DMAMUX0 }
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
+ * @{
+ */
+
+/** FGPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} FGPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
+ * @{
+ */
+
+/*! @name PDOR - Port Data Output Register */
+#define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
+#define FGPIO_PDOR_PDO_SHIFT (0U)
+#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK)
+
+/*! @name PSOR - Port Set Output Register */
+#define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
+#define FGPIO_PSOR_PTSO_SHIFT (0U)
+#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK)
+
+/*! @name PCOR - Port Clear Output Register */
+#define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
+#define FGPIO_PCOR_PTCO_SHIFT (0U)
+#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK)
+
+/*! @name PTOR - Port Toggle Output Register */
+#define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
+#define FGPIO_PTOR_PTTO_SHIFT (0U)
+#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK)
+
+/*! @name PDIR - Port Data Input Register */
+#define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
+#define FGPIO_PDIR_PDI_SHIFT (0U)
+#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK)
+
+/*! @name PDDR - Port Data Direction Register */
+#define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
+#define FGPIO_PDDR_PDD_SHIFT (0U)
+#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Register_Masks */
+
+
+/* FGPIO - Peripheral instance base addresses */
+/** Peripheral FGPIOA base address */
+#define FGPIOA_BASE (0xF8000000u)
+/** Peripheral FGPIOA base pointer */
+#define FGPIOA ((FGPIO_Type *)FGPIOA_BASE)
+/** Peripheral FGPIOB base address */
+#define FGPIOB_BASE (0xF8000040u)
+/** Peripheral FGPIOB base pointer */
+#define FGPIOB ((FGPIO_Type *)FGPIOB_BASE)
+/** Peripheral FGPIOC base address */
+#define FGPIOC_BASE (0xF8000080u)
+/** Peripheral FGPIOC base pointer */
+#define FGPIOC ((FGPIO_Type *)FGPIOC_BASE)
+/** Peripheral FGPIOD base address */
+#define FGPIOD_BASE (0xF80000C0u)
+/** Peripheral FGPIOD base pointer */
+#define FGPIOD ((FGPIO_Type *)FGPIOD_BASE)
+/** Peripheral FGPIOE base address */
+#define FGPIOE_BASE (0xF8000100u)
+/** Peripheral FGPIOE base pointer */
+#define FGPIOE ((FGPIO_Type *)FGPIOE_BASE)
+/** Array initializer of FGPIO peripheral base addresses */
+#define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE, FGPIOD_BASE, FGPIOE_BASE }
+/** Array initializer of FGPIO peripheral base pointers */
+#define FGPIO_BASE_PTRS { FGPIOA, FGPIOB, FGPIOC, FGPIOD, FGPIOE }
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
+ * @{
+ */
+
+/** FTFA - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+} FTFA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Masks FTFA Register Masks
+ * @{
+ */
+
+/*! @name FSTAT - Flash Status Register */
+#define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
+#define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
+#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
+#define FTFA_FSTAT_FPVIOL_MASK (0x10U)
+#define FTFA_FSTAT_FPVIOL_SHIFT (4U)
+#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
+#define FTFA_FSTAT_ACCERR_MASK (0x20U)
+#define FTFA_FSTAT_ACCERR_SHIFT (5U)
+#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
+#define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
+#define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
+#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
+#define FTFA_FSTAT_CCIF_MASK (0x80U)
+#define FTFA_FSTAT_CCIF_SHIFT (7U)
+#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
+
+/*! @name FCNFG - Flash Configuration Register */
+#define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
+#define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
+#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
+#define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
+#define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
+#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
+#define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
+#define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
+#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
+#define FTFA_FCNFG_CCIE_MASK (0x80U)
+#define FTFA_FCNFG_CCIE_SHIFT (7U)
+#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
+
+/*! @name FSEC - Flash Security Register */
+#define FTFA_FSEC_SEC_MASK (0x3U)
+#define FTFA_FSEC_SEC_SHIFT (0U)
+#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK (0xCU)
+#define FTFA_FSEC_FSLACC_SHIFT (2U)
+#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK (0x30U)
+#define FTFA_FSEC_MEEN_SHIFT (4U)
+#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK (0xC0U)
+#define FTFA_FSEC_KEYEN_SHIFT (6U)
+#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Flash Option Register */
+#define FTFA_FOPT_OPT_MASK (0xFFU)
+#define FTFA_FOPT_OPT_SHIFT (0U)
+#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
+
+/*! @name FCCOB3 - Flash Common Command Object Registers */
+#define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB3_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
+
+/*! @name FCCOB2 - Flash Common Command Object Registers */
+#define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB2_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
+
+/*! @name FCCOB1 - Flash Common Command Object Registers */
+#define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB1_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
+
+/*! @name FCCOB0 - Flash Common Command Object Registers */
+#define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB0_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
+
+/*! @name FCCOB7 - Flash Common Command Object Registers */
+#define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB7_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
+
+/*! @name FCCOB6 - Flash Common Command Object Registers */
+#define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB6_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
+
+/*! @name FCCOB5 - Flash Common Command Object Registers */
+#define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB5_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
+
+/*! @name FCCOB4 - Flash Common Command Object Registers */
+#define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB4_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
+
+/*! @name FCCOBB - Flash Common Command Object Registers */
+#define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOBB_CCOBn_SHIFT (0U)
+#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
+
+/*! @name FCCOBA - Flash Common Command Object Registers */
+#define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOBA_CCOBn_SHIFT (0U)
+#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
+
+/*! @name FCCOB9 - Flash Common Command Object Registers */
+#define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB9_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
+
+/*! @name FCCOB8 - Flash Common Command Object Registers */
+#define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB8_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
+
+/*! @name FPROT3 - Program Flash Protection Registers */
+#define FTFA_FPROT3_PROT_MASK (0xFFU)
+#define FTFA_FPROT3_PROT_SHIFT (0U)
+#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Program Flash Protection Registers */
+#define FTFA_FPROT2_PROT_MASK (0xFFU)
+#define FTFA_FPROT2_PROT_SHIFT (0U)
+#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Program Flash Protection Registers */
+#define FTFA_FPROT1_PROT_MASK (0xFFU)
+#define FTFA_FPROT1_PROT_SHIFT (0U)
+#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Program Flash Protection Registers */
+#define FTFA_FPROT0_PROT_MASK (0xFFU)
+#define FTFA_FPROT0_PROT_SHIFT (0U)
+#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Masks */
+
+
+/* FTFA - Peripheral instance base addresses */
+/** Peripheral FTFA base address */
+#define FTFA_BASE (0x40020000u)
+/** Peripheral FTFA base pointer */
+#define FTFA ((FTFA_Type *)FTFA_BASE)
+/** Array initializer of FTFA peripheral base addresses */
+#define FTFA_BASE_ADDRS { FTFA_BASE }
+/** Array initializer of FTFA peripheral base pointers */
+#define FTFA_BASE_PTRS { FTFA }
+/** Interrupt vectors for the FTFA peripheral type */
+#define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FTFA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name PDOR - Port Data Output Register */
+#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
+#define GPIO_PDOR_PDO_SHIFT (0U)
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
+
+/*! @name PSOR - Port Set Output Register */
+#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
+#define GPIO_PSOR_PTSO_SHIFT (0U)
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
+
+/*! @name PCOR - Port Clear Output Register */
+#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
+#define GPIO_PCOR_PTCO_SHIFT (0U)
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
+
+/*! @name PTOR - Port Toggle Output Register */
+#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
+#define GPIO_PTOR_PTTO_SHIFT (0U)
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
+
+/*! @name PDIR - Port Data Input Register */
+#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
+#define GPIO_PDIR_PDI_SHIFT (0U)
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
+
+/*! @name PDDR - Port Data Direction Register */
+#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
+#define GPIO_PDDR_PDD_SHIFT (0U)
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE (0x400FF000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA ((GPIO_Type *)GPIOA_BASE)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE (0x400FF040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB ((GPIO_Type *)GPIOB_BASE)
+/** Peripheral GPIOC base address */
+#define GPIOC_BASE (0x400FF080u)
+/** Peripheral GPIOC base pointer */
+#define GPIOC ((GPIO_Type *)GPIOC_BASE)
+/** Peripheral GPIOD base address */
+#define GPIOD_BASE (0x400FF0C0u)
+/** Peripheral GPIOD base pointer */
+#define GPIOD ((GPIO_Type *)GPIOD_BASE)
+/** Peripheral GPIOE base address */
+#define GPIOE_BASE (0x400FF100u)
+/** Peripheral GPIOE base pointer */
+#define GPIOE ((GPIO_Type *)GPIOE_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name A1 - I2C Address Register 1 */
+#define I2C_A1_AD_MASK (0xFEU)
+#define I2C_A1_AD_SHIFT (1U)
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
+
+/*! @name F - I2C Frequency Divider register */
+#define I2C_F_ICR_MASK (0x3FU)
+#define I2C_F_ICR_SHIFT (0U)
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK (0xC0U)
+#define I2C_F_MULT_SHIFT (6U)
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
+
+/*! @name C1 - I2C Control Register 1 */
+#define I2C_C1_DMAEN_MASK (0x1U)
+#define I2C_C1_DMAEN_SHIFT (0U)
+#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
+#define I2C_C1_WUEN_MASK (0x2U)
+#define I2C_C1_WUEN_SHIFT (1U)
+#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
+#define I2C_C1_RSTA_MASK (0x4U)
+#define I2C_C1_RSTA_SHIFT (2U)
+#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
+#define I2C_C1_TXAK_MASK (0x8U)
+#define I2C_C1_TXAK_SHIFT (3U)
+#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
+#define I2C_C1_TX_MASK (0x10U)
+#define I2C_C1_TX_SHIFT (4U)
+#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
+#define I2C_C1_MST_MASK (0x20U)
+#define I2C_C1_MST_SHIFT (5U)
+#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
+#define I2C_C1_IICIE_MASK (0x40U)
+#define I2C_C1_IICIE_SHIFT (6U)
+#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
+#define I2C_C1_IICEN_MASK (0x80U)
+#define I2C_C1_IICEN_SHIFT (7U)
+#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
+
+/*! @name S - I2C Status register */
+#define I2C_S_RXAK_MASK (0x1U)
+#define I2C_S_RXAK_SHIFT (0U)
+#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
+#define I2C_S_IICIF_MASK (0x2U)
+#define I2C_S_IICIF_SHIFT (1U)
+#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
+#define I2C_S_SRW_MASK (0x4U)
+#define I2C_S_SRW_SHIFT (2U)
+#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
+#define I2C_S_RAM_MASK (0x8U)
+#define I2C_S_RAM_SHIFT (3U)
+#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
+#define I2C_S_ARBL_MASK (0x10U)
+#define I2C_S_ARBL_SHIFT (4U)
+#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
+#define I2C_S_BUSY_MASK (0x20U)
+#define I2C_S_BUSY_SHIFT (5U)
+#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
+#define I2C_S_IAAS_MASK (0x40U)
+#define I2C_S_IAAS_SHIFT (6U)
+#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
+#define I2C_S_TCF_MASK (0x80U)
+#define I2C_S_TCF_SHIFT (7U)
+#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
+
+/*! @name D - I2C Data I/O register */
+#define I2C_D_DATA_MASK (0xFFU)
+#define I2C_D_DATA_SHIFT (0U)
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
+
+/*! @name C2 - I2C Control Register 2 */
+#define I2C_C2_AD_MASK (0x7U)
+#define I2C_C2_AD_SHIFT (0U)
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK (0x8U)
+#define I2C_C2_RMEN_SHIFT (3U)
+#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
+#define I2C_C2_SBRC_MASK (0x10U)
+#define I2C_C2_SBRC_SHIFT (4U)
+#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
+#define I2C_C2_HDRS_MASK (0x20U)
+#define I2C_C2_HDRS_SHIFT (5U)
+#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
+#define I2C_C2_ADEXT_MASK (0x40U)
+#define I2C_C2_ADEXT_SHIFT (6U)
+#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
+#define I2C_C2_GCAEN_MASK (0x80U)
+#define I2C_C2_GCAEN_SHIFT (7U)
+#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
+
+/*! @name FLT - I2C Programmable Input Glitch Filter register */
+#define I2C_FLT_FLT_MASK (0xFU)
+#define I2C_FLT_FLT_SHIFT (0U)
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK (0x10U)
+#define I2C_FLT_STARTF_SHIFT (4U)
+#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
+#define I2C_FLT_SSIE_MASK (0x20U)
+#define I2C_FLT_SSIE_SHIFT (5U)
+#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
+#define I2C_FLT_STOPF_MASK (0x40U)
+#define I2C_FLT_STOPF_SHIFT (6U)
+#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
+#define I2C_FLT_SHEN_MASK (0x80U)
+#define I2C_FLT_SHEN_SHIFT (7U)
+#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
+
+/*! @name RA - I2C Range Address register */
+#define I2C_RA_RAD_MASK (0xFEU)
+#define I2C_RA_RAD_SHIFT (1U)
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
+
+/*! @name SMB - I2C SMBus Control and Status register */
+#define I2C_SMB_SHTF2IE_MASK (0x1U)
+#define I2C_SMB_SHTF2IE_SHIFT (0U)
+#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
+#define I2C_SMB_SHTF2_MASK (0x2U)
+#define I2C_SMB_SHTF2_SHIFT (1U)
+#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
+#define I2C_SMB_SHTF1_MASK (0x4U)
+#define I2C_SMB_SHTF1_SHIFT (2U)
+#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
+#define I2C_SMB_SLTF_MASK (0x8U)
+#define I2C_SMB_SLTF_SHIFT (3U)
+#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
+#define I2C_SMB_TCKSEL_MASK (0x10U)
+#define I2C_SMB_TCKSEL_SHIFT (4U)
+#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
+#define I2C_SMB_SIICAEN_MASK (0x20U)
+#define I2C_SMB_SIICAEN_SHIFT (5U)
+#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
+#define I2C_SMB_ALERTEN_MASK (0x40U)
+#define I2C_SMB_ALERTEN_SHIFT (6U)
+#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
+#define I2C_SMB_FACK_MASK (0x80U)
+#define I2C_SMB_FACK_SHIFT (7U)
+#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
+
+/*! @name A2 - I2C Address Register 2 */
+#define I2C_A2_SAD_MASK (0xFEU)
+#define I2C_A2_SAD_SHIFT (1U)
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
+
+/*! @name SLTH - I2C SCL Low Timeout Register High */
+#define I2C_SLTH_SSLT_MASK (0xFFU)
+#define I2C_SLTH_SSLT_SHIFT (0U)
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
+
+/*! @name SLTL - I2C SCL Low Timeout Register Low */
+#define I2C_SLTL_SSLT_MASK (0xFFU)
+#define I2C_SLTL_SSLT_SHIFT (0U)
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS { I2C0, I2C1 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+ uint8_t RESERVED_1[8];
+ __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_2[60];
+ __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
+ uint8_t RESERVED_3[28];
+ __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+ uint8_t RESERVED_5[8];
+ __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_6[60];
+ __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
+ __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/*! @name TCSR - SAI Transmit Control Register */
+#define I2S_TCSR_FWDE_MASK (0x2U)
+#define I2S_TCSR_FWDE_SHIFT (1U)
+#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FWIE_MASK (0x200U)
+#define I2S_TCSR_FWIE_SHIFT (9U)
+#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK (0x400U)
+#define I2S_TCSR_FEIE_SHIFT (10U)
+#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK (0x800U)
+#define I2S_TCSR_SEIE_SHIFT (11U)
+#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK (0x1000U)
+#define I2S_TCSR_WSIE_SHIFT (12U)
+#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FWF_MASK (0x20000U)
+#define I2S_TCSR_FWF_SHIFT (17U)
+#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK (0x40000U)
+#define I2S_TCSR_FEF_SHIFT (18U)
+#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK (0x80000U)
+#define I2S_TCSR_SEF_SHIFT (19U)
+#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK (0x100000U)
+#define I2S_TCSR_WSF_SHIFT (20U)
+#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK (0x1000000U)
+#define I2S_TCSR_SR_SHIFT (24U)
+#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK (0x2000000U)
+#define I2S_TCSR_FR_SHIFT (25U)
+#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK (0x10000000U)
+#define I2S_TCSR_BCE_SHIFT (28U)
+#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK (0x20000000U)
+#define I2S_TCSR_DBGE_SHIFT (29U)
+#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK (0x40000000U)
+#define I2S_TCSR_STOPE_SHIFT (30U)
+#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK (0x80000000U)
+#define I2S_TCSR_TE_SHIFT (31U)
+#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
+
+/*! @name TCR2 - SAI Transmit Configuration 2 Register */
+#define I2S_TCR2_DIV_MASK (0xFFU)
+#define I2S_TCR2_DIV_SHIFT (0U)
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK (0x1000000U)
+#define I2S_TCR2_BCD_SHIFT (24U)
+#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK (0x2000000U)
+#define I2S_TCR2_BCP_SHIFT (25U)
+#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK (0xC000000U)
+#define I2S_TCR2_MSEL_SHIFT (26U)
+#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK (0x10000000U)
+#define I2S_TCR2_BCI_SHIFT (28U)
+#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK (0x20000000U)
+#define I2S_TCR2_BCS_SHIFT (29U)
+#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK (0xC0000000U)
+#define I2S_TCR2_SYNC_SHIFT (30U)
+#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
+
+/*! @name TCR3 - SAI Transmit Configuration 3 Register */
+#define I2S_TCR3_WDFL_MASK (0x1U)
+#define I2S_TCR3_WDFL_SHIFT (0U)
+#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK (0x10000U)
+#define I2S_TCR3_TCE_SHIFT (16U)
+#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
+
+/*! @name TCR4 - SAI Transmit Configuration 4 Register */
+#define I2S_TCR4_FSD_MASK (0x1U)
+#define I2S_TCR4_FSD_SHIFT (0U)
+#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK (0x2U)
+#define I2S_TCR4_FSP_SHIFT (1U)
+#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_FSE_MASK (0x8U)
+#define I2S_TCR4_FSE_SHIFT (3U)
+#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK (0x10U)
+#define I2S_TCR4_MF_SHIFT (4U)
+#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
+#define I2S_TCR4_SYWD_MASK (0x1F00U)
+#define I2S_TCR4_SYWD_SHIFT (8U)
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK (0x10000U)
+#define I2S_TCR4_FRSZ_SHIFT (16U)
+#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
+
+/*! @name TCR5 - SAI Transmit Configuration 5 Register */
+#define I2S_TCR5_FBT_MASK (0x1F00U)
+#define I2S_TCR5_FBT_SHIFT (8U)
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK (0x1F0000U)
+#define I2S_TCR5_W0W_SHIFT (16U)
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK (0x1F000000U)
+#define I2S_TCR5_WNW_SHIFT (24U)
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
+
+/*! @name TDR - SAI Transmit Data Register */
+#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
+#define I2S_TDR_TDR_SHIFT (0U)
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
+
+/* The count of I2S_TDR */
+#define I2S_TDR_COUNT (1U)
+
+/*! @name TMR - SAI Transmit Mask Register */
+#define I2S_TMR_TWM_MASK (0x3U)
+#define I2S_TMR_TWM_SHIFT (0U)
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
+
+/*! @name RCSR - SAI Receive Control Register */
+#define I2S_RCSR_FWDE_MASK (0x2U)
+#define I2S_RCSR_FWDE_SHIFT (1U)
+#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FWIE_MASK (0x200U)
+#define I2S_RCSR_FWIE_SHIFT (9U)
+#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK (0x400U)
+#define I2S_RCSR_FEIE_SHIFT (10U)
+#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK (0x800U)
+#define I2S_RCSR_SEIE_SHIFT (11U)
+#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK (0x1000U)
+#define I2S_RCSR_WSIE_SHIFT (12U)
+#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FWF_MASK (0x20000U)
+#define I2S_RCSR_FWF_SHIFT (17U)
+#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK (0x40000U)
+#define I2S_RCSR_FEF_SHIFT (18U)
+#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK (0x80000U)
+#define I2S_RCSR_SEF_SHIFT (19U)
+#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK (0x100000U)
+#define I2S_RCSR_WSF_SHIFT (20U)
+#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK (0x1000000U)
+#define I2S_RCSR_SR_SHIFT (24U)
+#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK (0x2000000U)
+#define I2S_RCSR_FR_SHIFT (25U)
+#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK (0x10000000U)
+#define I2S_RCSR_BCE_SHIFT (28U)
+#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK (0x20000000U)
+#define I2S_RCSR_DBGE_SHIFT (29U)
+#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK (0x40000000U)
+#define I2S_RCSR_STOPE_SHIFT (30U)
+#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK (0x80000000U)
+#define I2S_RCSR_RE_SHIFT (31U)
+#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
+
+/*! @name RCR2 - SAI Receive Configuration 2 Register */
+#define I2S_RCR2_DIV_MASK (0xFFU)
+#define I2S_RCR2_DIV_SHIFT (0U)
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK (0x1000000U)
+#define I2S_RCR2_BCD_SHIFT (24U)
+#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK (0x2000000U)
+#define I2S_RCR2_BCP_SHIFT (25U)
+#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK (0xC000000U)
+#define I2S_RCR2_MSEL_SHIFT (26U)
+#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK (0x10000000U)
+#define I2S_RCR2_BCI_SHIFT (28U)
+#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK (0x20000000U)
+#define I2S_RCR2_BCS_SHIFT (29U)
+#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK (0xC0000000U)
+#define I2S_RCR2_SYNC_SHIFT (30U)
+#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
+
+/*! @name RCR3 - SAI Receive Configuration 3 Register */
+#define I2S_RCR3_WDFL_MASK (0x1U)
+#define I2S_RCR3_WDFL_SHIFT (0U)
+#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK (0x10000U)
+#define I2S_RCR3_RCE_SHIFT (16U)
+#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
+
+/*! @name RCR4 - SAI Receive Configuration 4 Register */
+#define I2S_RCR4_FSD_MASK (0x1U)
+#define I2S_RCR4_FSD_SHIFT (0U)
+#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK (0x2U)
+#define I2S_RCR4_FSP_SHIFT (1U)
+#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_FSE_MASK (0x8U)
+#define I2S_RCR4_FSE_SHIFT (3U)
+#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK (0x10U)
+#define I2S_RCR4_MF_SHIFT (4U)
+#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK (0x1F00U)
+#define I2S_RCR4_SYWD_SHIFT (8U)
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK (0x10000U)
+#define I2S_RCR4_FRSZ_SHIFT (16U)
+#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
+
+/*! @name RCR5 - SAI Receive Configuration 5 Register */
+#define I2S_RCR5_FBT_MASK (0x1F00U)
+#define I2S_RCR5_FBT_SHIFT (8U)
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK (0x1F0000U)
+#define I2S_RCR5_W0W_SHIFT (16U)
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK (0x1F000000U)
+#define I2S_RCR5_WNW_SHIFT (24U)
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
+
+/*! @name RDR - SAI Receive Data Register */
+#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
+#define I2S_RDR_RDR_SHIFT (0U)
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
+
+/* The count of I2S_RDR */
+#define I2S_RDR_COUNT (1U)
+
+/*! @name RMR - SAI Receive Mask Register */
+#define I2S_RMR_RWM_MASK (0x3U)
+#define I2S_RMR_RWM_SHIFT (0U)
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
+
+/*! @name MCR - SAI MCLK Control Register */
+#define I2S_MCR_MICS_MASK (0x3000000U)
+#define I2S_MCR_MICS_SHIFT (24U)
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK (0x40000000U)
+#define I2S_MCR_MOE_SHIFT (30U)
+#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
+#define I2S_MCR_DUF_MASK (0x80000000U)
+#define I2S_MCR_DUF_SHIFT (31U)
+#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
+
+/*! @name MDR - SAI MCLK Divide Register */
+#define I2S_MDR_DIVIDE_MASK (0xFFFU)
+#define I2S_MDR_DIVIDE_SHIFT (0U)
+#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK (0xFF000U)
+#define I2S_MDR_FRACT_SHIFT (12U)
+#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS { I2S0_IRQn }
+#define I2S_TX_IRQS { I2S0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/*! @name PE1 - LLWU Pin Enable 1 register */
+#define LLWU_PE1_WUPE0_MASK (0x3U)
+#define LLWU_PE1_WUPE0_SHIFT (0U)
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK (0xCU)
+#define LLWU_PE1_WUPE1_SHIFT (2U)
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK (0x30U)
+#define LLWU_PE1_WUPE2_SHIFT (4U)
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK (0xC0U)
+#define LLWU_PE1_WUPE3_SHIFT (6U)
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
+
+/*! @name PE2 - LLWU Pin Enable 2 register */
+#define LLWU_PE2_WUPE4_MASK (0x3U)
+#define LLWU_PE2_WUPE4_SHIFT (0U)
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK (0xCU)
+#define LLWU_PE2_WUPE5_SHIFT (2U)
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK (0x30U)
+#define LLWU_PE2_WUPE6_SHIFT (4U)
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK (0xC0U)
+#define LLWU_PE2_WUPE7_SHIFT (6U)
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
+
+/*! @name PE3 - LLWU Pin Enable 3 register */
+#define LLWU_PE3_WUPE8_MASK (0x3U)
+#define LLWU_PE3_WUPE8_SHIFT (0U)
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK (0xCU)
+#define LLWU_PE3_WUPE9_SHIFT (2U)
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK (0x30U)
+#define LLWU_PE3_WUPE10_SHIFT (4U)
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK (0xC0U)
+#define LLWU_PE3_WUPE11_SHIFT (6U)
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
+
+/*! @name PE4 - LLWU Pin Enable 4 register */
+#define LLWU_PE4_WUPE12_MASK (0x3U)
+#define LLWU_PE4_WUPE12_SHIFT (0U)
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK (0xCU)
+#define LLWU_PE4_WUPE13_SHIFT (2U)
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK (0x30U)
+#define LLWU_PE4_WUPE14_SHIFT (4U)
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK (0xC0U)
+#define LLWU_PE4_WUPE15_SHIFT (6U)
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
+
+/*! @name ME - LLWU Module Enable register */
+#define LLWU_ME_WUME0_MASK (0x1U)
+#define LLWU_ME_WUME0_SHIFT (0U)
+#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK (0x2U)
+#define LLWU_ME_WUME1_SHIFT (1U)
+#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK (0x4U)
+#define LLWU_ME_WUME2_SHIFT (2U)
+#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME3_MASK (0x8U)
+#define LLWU_ME_WUME3_SHIFT (3U)
+#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME4_MASK (0x10U)
+#define LLWU_ME_WUME4_SHIFT (4U)
+#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME5_MASK (0x20U)
+#define LLWU_ME_WUME5_SHIFT (5U)
+#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK (0x40U)
+#define LLWU_ME_WUME6_SHIFT (6U)
+#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK (0x80U)
+#define LLWU_ME_WUME7_SHIFT (7U)
+#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
+
+/*! @name F1 - LLWU Flag 1 register */
+#define LLWU_F1_WUF0_MASK (0x1U)
+#define LLWU_F1_WUF0_SHIFT (0U)
+#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
+#define LLWU_F1_WUF1_MASK (0x2U)
+#define LLWU_F1_WUF1_SHIFT (1U)
+#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
+#define LLWU_F1_WUF2_MASK (0x4U)
+#define LLWU_F1_WUF2_SHIFT (2U)
+#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
+#define LLWU_F1_WUF3_MASK (0x8U)
+#define LLWU_F1_WUF3_SHIFT (3U)
+#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
+#define LLWU_F1_WUF4_MASK (0x10U)
+#define LLWU_F1_WUF4_SHIFT (4U)
+#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
+#define LLWU_F1_WUF5_MASK (0x20U)
+#define LLWU_F1_WUF5_SHIFT (5U)
+#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
+#define LLWU_F1_WUF6_MASK (0x40U)
+#define LLWU_F1_WUF6_SHIFT (6U)
+#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
+#define LLWU_F1_WUF7_MASK (0x80U)
+#define LLWU_F1_WUF7_SHIFT (7U)
+#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
+
+/*! @name F2 - LLWU Flag 2 register */
+#define LLWU_F2_WUF8_MASK (0x1U)
+#define LLWU_F2_WUF8_SHIFT (0U)
+#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
+#define LLWU_F2_WUF9_MASK (0x2U)
+#define LLWU_F2_WUF9_SHIFT (1U)
+#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
+#define LLWU_F2_WUF10_MASK (0x4U)
+#define LLWU_F2_WUF10_SHIFT (2U)
+#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
+#define LLWU_F2_WUF11_MASK (0x8U)
+#define LLWU_F2_WUF11_SHIFT (3U)
+#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
+#define LLWU_F2_WUF12_MASK (0x10U)
+#define LLWU_F2_WUF12_SHIFT (4U)
+#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
+#define LLWU_F2_WUF13_MASK (0x20U)
+#define LLWU_F2_WUF13_SHIFT (5U)
+#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
+#define LLWU_F2_WUF14_MASK (0x40U)
+#define LLWU_F2_WUF14_SHIFT (6U)
+#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
+#define LLWU_F2_WUF15_MASK (0x80U)
+#define LLWU_F2_WUF15_SHIFT (7U)
+#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
+
+/*! @name F3 - LLWU Flag 3 register */
+#define LLWU_F3_MWUF0_MASK (0x1U)
+#define LLWU_F3_MWUF0_SHIFT (0U)
+#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
+#define LLWU_F3_MWUF1_MASK (0x2U)
+#define LLWU_F3_MWUF1_SHIFT (1U)
+#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
+#define LLWU_F3_MWUF2_MASK (0x4U)
+#define LLWU_F3_MWUF2_SHIFT (2U)
+#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
+#define LLWU_F3_MWUF3_MASK (0x8U)
+#define LLWU_F3_MWUF3_SHIFT (3U)
+#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
+#define LLWU_F3_MWUF4_MASK (0x10U)
+#define LLWU_F3_MWUF4_SHIFT (4U)
+#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
+#define LLWU_F3_MWUF5_MASK (0x20U)
+#define LLWU_F3_MWUF5_SHIFT (5U)
+#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
+#define LLWU_F3_MWUF6_MASK (0x40U)
+#define LLWU_F3_MWUF6_SHIFT (6U)
+#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
+#define LLWU_F3_MWUF7_MASK (0x80U)
+#define LLWU_F3_MWUF7_SHIFT (7U)
+#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
+
+/*! @name FILT1 - LLWU Pin Filter 1 register */
+#define LLWU_FILT1_FILTSEL_MASK (0xFU)
+#define LLWU_FILT1_FILTSEL_SHIFT (0U)
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK (0x60U)
+#define LLWU_FILT1_FILTE_SHIFT (5U)
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK (0x80U)
+#define LLWU_FILT1_FILTF_SHIFT (7U)
+#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
+
+/*! @name FILT2 - LLWU Pin Filter 2 register */
+#define LLWU_FILT2_FILTSEL_MASK (0xFU)
+#define LLWU_FILT2_FILTSEL_SHIFT (0U)
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK (0x60U)
+#define LLWU_FILT2_FILTE_SHIFT (5U)
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK (0x80U)
+#define LLWU_FILT2_FILTF_SHIFT (7U)
+#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS { LLWU_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/*! @name CSR - Low Power Timer Control Status Register */
+#define LPTMR_CSR_TEN_MASK (0x1U)
+#define LPTMR_CSR_TEN_SHIFT (0U)
+#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK (0x2U)
+#define LPTMR_CSR_TMS_SHIFT (1U)
+#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK (0x4U)
+#define LPTMR_CSR_TFC_SHIFT (2U)
+#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK (0x8U)
+#define LPTMR_CSR_TPP_SHIFT (3U)
+#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK (0x30U)
+#define LPTMR_CSR_TPS_SHIFT (4U)
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK (0x40U)
+#define LPTMR_CSR_TIE_SHIFT (6U)
+#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK (0x80U)
+#define LPTMR_CSR_TCF_SHIFT (7U)
+#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
+
+/*! @name PSR - Low Power Timer Prescale Register */
+#define LPTMR_PSR_PCS_MASK (0x3U)
+#define LPTMR_PSR_PCS_SHIFT (0U)
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK (0x4U)
+#define LPTMR_PSR_PBYP_SHIFT (2U)
+#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK (0x78U)
+#define LPTMR_PSR_PRESCALE_SHIFT (3U)
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
+
+/*! @name CMR - Low Power Timer Compare Register */
+#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
+#define LPTMR_CMR_COMPARE_SHIFT (0U)
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+
+/*! @name CNR - Low Power Timer Counter Register */
+#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
+#define LPTMR_CNR_COUNTER_SHIFT (0U)
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS { LPTMR0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+ __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
+ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
+ uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
+ uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/*! @name C1 - MCG Control 1 Register */
+#define MCG_C1_IREFSTEN_MASK (0x1U)
+#define MCG_C1_IREFSTEN_SHIFT (0U)
+#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IRCLKEN_MASK (0x2U)
+#define MCG_C1_IRCLKEN_SHIFT (1U)
+#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IREFS_MASK (0x4U)
+#define MCG_C1_IREFS_SHIFT (2U)
+#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
+#define MCG_C1_FRDIV_MASK (0x38U)
+#define MCG_C1_FRDIV_SHIFT (3U)
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK (0xC0U)
+#define MCG_C1_CLKS_SHIFT (6U)
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
+
+/*! @name C2 - MCG Control 2 Register */
+#define MCG_C2_IRCS_MASK (0x1U)
+#define MCG_C2_IRCS_SHIFT (0U)
+#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
+#define MCG_C2_LP_MASK (0x2U)
+#define MCG_C2_LP_SHIFT (1U)
+#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
+#define MCG_C2_EREFS0_MASK (0x4U)
+#define MCG_C2_EREFS0_SHIFT (2U)
+#define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK)
+#define MCG_C2_HGO0_MASK (0x8U)
+#define MCG_C2_HGO0_SHIFT (3U)
+#define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK)
+#define MCG_C2_RANGE0_MASK (0x30U)
+#define MCG_C2_RANGE0_SHIFT (4U)
+#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK)
+#define MCG_C2_FCFTRIM_MASK (0x40U)
+#define MCG_C2_FCFTRIM_SHIFT (6U)
+#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
+#define MCG_C2_LOCRE0_MASK (0x80U)
+#define MCG_C2_LOCRE0_SHIFT (7U)
+#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
+
+/*! @name C3 - MCG Control 3 Register */
+#define MCG_C3_SCTRIM_MASK (0xFFU)
+#define MCG_C3_SCTRIM_SHIFT (0U)
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
+
+/*! @name C4 - MCG Control 4 Register */
+#define MCG_C4_SCFTRIM_MASK (0x1U)
+#define MCG_C4_SCFTRIM_SHIFT (0U)
+#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_FCTRIM_MASK (0x1EU)
+#define MCG_C4_FCTRIM_SHIFT (1U)
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK (0x60U)
+#define MCG_C4_DRST_DRS_SHIFT (5U)
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK (0x80U)
+#define MCG_C4_DMX32_SHIFT (7U)
+#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
+
+/*! @name C5 - MCG Control 5 Register */
+#define MCG_C5_PRDIV0_MASK (0x1FU)
+#define MCG_C5_PRDIV0_SHIFT (0U)
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK (0x20U)
+#define MCG_C5_PLLSTEN0_SHIFT (5U)
+#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
+#define MCG_C5_PLLCLKEN0_MASK (0x40U)
+#define MCG_C5_PLLCLKEN0_SHIFT (6U)
+#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
+
+/*! @name C6 - MCG Control 6 Register */
+#define MCG_C6_VDIV0_MASK (0x1FU)
+#define MCG_C6_VDIV0_SHIFT (0U)
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK (0x20U)
+#define MCG_C6_CME0_SHIFT (5U)
+#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
+#define MCG_C6_PLLS_MASK (0x40U)
+#define MCG_C6_PLLS_SHIFT (6U)
+#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
+#define MCG_C6_LOLIE0_MASK (0x80U)
+#define MCG_C6_LOLIE0_SHIFT (7U)
+#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
+
+/*! @name S - MCG Status Register */
+#define MCG_S_IRCST_MASK (0x1U)
+#define MCG_S_IRCST_SHIFT (0U)
+#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
+#define MCG_S_OSCINIT0_MASK (0x2U)
+#define MCG_S_OSCINIT0_SHIFT (1U)
+#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
+#define MCG_S_CLKST_MASK (0xCU)
+#define MCG_S_CLKST_SHIFT (2U)
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK (0x10U)
+#define MCG_S_IREFST_SHIFT (4U)
+#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
+#define MCG_S_PLLST_MASK (0x20U)
+#define MCG_S_PLLST_SHIFT (5U)
+#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
+#define MCG_S_LOCK0_MASK (0x40U)
+#define MCG_S_LOCK0_SHIFT (6U)
+#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
+#define MCG_S_LOLS0_MASK (0x80U)
+#define MCG_S_LOLS0_SHIFT (7U)
+#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
+
+/*! @name SC - MCG Status and Control Register */
+#define MCG_SC_LOCS0_MASK (0x1U)
+#define MCG_SC_LOCS0_SHIFT (0U)
+#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
+#define MCG_SC_FCRDIV_MASK (0xEU)
+#define MCG_SC_FCRDIV_SHIFT (1U)
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK (0x10U)
+#define MCG_SC_FLTPRSRV_SHIFT (4U)
+#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_ATMF_MASK (0x20U)
+#define MCG_SC_ATMF_SHIFT (5U)
+#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMS_MASK (0x40U)
+#define MCG_SC_ATMS_SHIFT (6U)
+#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
+#define MCG_SC_ATME_MASK (0x80U)
+#define MCG_SC_ATME_SHIFT (7U)
+#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
+
+/*! @name ATCVH - MCG Auto Trim Compare Value High Register */
+#define MCG_ATCVH_ATCVH_MASK (0xFFU)
+#define MCG_ATCVH_ATCVH_SHIFT (0U)
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
+
+/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
+#define MCG_ATCVL_ATCVL_MASK (0xFFU)
+#define MCG_ATCVL_ATCVL_SHIFT (0U)
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
+
+/*! @name C7 - MCG Control 7 Register */
+#define MCG_C7_OSCSEL_MASK (0x1U)
+#define MCG_C7_OSCSEL_SHIFT (0U)
+#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
+
+/*! @name C8 - MCG Control 8 Register */
+#define MCG_C8_LOLRE_MASK (0x40U)
+#define MCG_C8_LOLRE_SHIFT (6U)
+#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS { MCG }
+/** Interrupt vectors for the MCG peripheral type */
+#define MCG_IRQS { MCG_IRQn }
+/* MCG C2[EREFS] backward compatibility */
+#define MCG_C2_EREFS_MASK (MCG_C2_EREFS0_MASK)
+#define MCG_C2_EREFS_SHIFT (MCG_C2_EREFS0_SHIFT)
+#define MCG_C2_EREFS_WIDTH (MCG_C2_EREFS0_WIDTH)
+#define MCG_C2_EREFS(x) (MCG_C2_EREFS0(x))
+
+/* MCG C2[HGO] backward compatibility */
+#define MCG_C2_HGO_MASK (MCG_C2_HGO0_MASK)
+#define MCG_C2_HGO_SHIFT (MCG_C2_HGO0_SHIFT)
+#define MCG_C2_HGO_WIDTH (MCG_C2_HGO0_WIDTH)
+#define MCG_C2_HGO(x) (MCG_C2_HGO0(x))
+
+/* MCG C2[RANGE] backward compatibility */
+#define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK)
+#define MCG_C2_RANGE_SHIFT (MCG_C2_RANGE0_SHIFT)
+#define MCG_C2_RANGE_WIDTH (MCG_C2_RANGE0_WIDTH)
+#define MCG_C2_RANGE(x) (MCG_C2_RANGE0(x))
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+ __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
+#define MCM_PLASC_ASC_MASK (0xFFU)
+#define MCM_PLASC_ASC_SHIFT (0U)
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
+
+/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
+#define MCM_PLAMC_AMC_MASK (0xFFU)
+#define MCM_PLAMC_AMC_SHIFT (0U)
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
+
+/*! @name PLACR - Platform Control Register */
+#define MCM_PLACR_ARB_MASK (0x200U)
+#define MCM_PLACR_ARB_SHIFT (9U)
+#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
+#define MCM_PLACR_CFCC_MASK (0x400U)
+#define MCM_PLACR_CFCC_SHIFT (10U)
+#define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK)
+#define MCM_PLACR_DFCDA_MASK (0x800U)
+#define MCM_PLACR_DFCDA_SHIFT (11U)
+#define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK)
+#define MCM_PLACR_DFCIC_MASK (0x1000U)
+#define MCM_PLACR_DFCIC_SHIFT (12U)
+#define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK)
+#define MCM_PLACR_DFCC_MASK (0x2000U)
+#define MCM_PLACR_DFCC_SHIFT (13U)
+#define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK)
+#define MCM_PLACR_EFDS_MASK (0x4000U)
+#define MCM_PLACR_EFDS_SHIFT (14U)
+#define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
+#define MCM_PLACR_DFCS_MASK (0x8000U)
+#define MCM_PLACR_DFCS_SHIFT (15U)
+#define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK)
+#define MCM_PLACR_ESFC_MASK (0x10000U)
+#define MCM_PLACR_ESFC_SHIFT (16U)
+#define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK)
+
+/*! @name CPO - Compute Operation Control Register */
+#define MCM_CPO_CPOREQ_MASK (0x1U)
+#define MCM_CPO_CPOREQ_SHIFT (0U)
+#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
+#define MCM_CPO_CPOACK_MASK (0x2U)
+#define MCM_CPO_CPOACK_SHIFT (1U)
+#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
+#define MCM_CPO_CPOWOI_MASK (0x4U)
+#define MCM_CPO_CPOWOI_SHIFT (2U)
+#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE (0xF0003000u)
+/** Peripheral MCM base pointer */
+#define MCM ((MCM_Type *)MCM_BASE)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS { MCM }
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
+ * @{
+ */
+
+/** MTB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
+ __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
+ __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
+ __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
+ uint8_t RESERVED_0[3824];
+ __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
+ uint8_t RESERVED_1[156];
+ __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
+ __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
+ uint8_t RESERVED_2[8];
+ __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
+ __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
+ __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
+ __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
+ uint8_t RESERVED_3[8];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
+ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
+ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
+ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
+ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
+ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
+ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
+ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Register_Masks MTB Register Masks
+ * @{
+ */
+
+/*! @name POSITION - MTB Position Register */
+#define MTB_POSITION_WRAP_MASK (0x4U)
+#define MTB_POSITION_WRAP_SHIFT (2U)
+#define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
+#define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U)
+#define MTB_POSITION_POINTER_SHIFT (3U)
+#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
+
+/*! @name MASTER - MTB Master Register */
+#define MTB_MASTER_MASK_MASK (0x1FU)
+#define MTB_MASTER_MASK_SHIFT (0U)
+#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
+#define MTB_MASTER_TSTARTEN_MASK (0x20U)
+#define MTB_MASTER_TSTARTEN_SHIFT (5U)
+#define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
+#define MTB_MASTER_TSTOPEN_MASK (0x40U)
+#define MTB_MASTER_TSTOPEN_SHIFT (6U)
+#define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
+#define MTB_MASTER_SFRWPRIV_MASK (0x80U)
+#define MTB_MASTER_SFRWPRIV_SHIFT (7U)
+#define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
+#define MTB_MASTER_RAMPRIV_MASK (0x100U)
+#define MTB_MASTER_RAMPRIV_SHIFT (8U)
+#define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
+#define MTB_MASTER_HALTREQ_MASK (0x200U)
+#define MTB_MASTER_HALTREQ_SHIFT (9U)
+#define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
+#define MTB_MASTER_EN_MASK (0x80000000U)
+#define MTB_MASTER_EN_SHIFT (31U)
+#define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
+
+/*! @name FLOW - MTB Flow Register */
+#define MTB_FLOW_AUTOSTOP_MASK (0x1U)
+#define MTB_FLOW_AUTOSTOP_SHIFT (0U)
+#define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
+#define MTB_FLOW_AUTOHALT_MASK (0x2U)
+#define MTB_FLOW_AUTOHALT_SHIFT (1U)
+#define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
+#define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U)
+#define MTB_FLOW_WATERMARK_SHIFT (3U)
+#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
+
+/*! @name BASE - MTB Base Register */
+#define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU)
+#define MTB_BASE_BASEADDR_SHIFT (0U)
+#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK)
+
+/*! @name MODECTRL - Integration Mode Control Register */
+#define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU)
+#define MTB_MODECTRL_MODECTRL_SHIFT (0U)
+#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK)
+
+/*! @name TAGSET - Claim TAG Set Register */
+#define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU)
+#define MTB_TAGSET_TAGSET_SHIFT (0U)
+#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK)
+
+/*! @name TAGCLEAR - Claim TAG Clear Register */
+#define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU)
+#define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U)
+#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK)
+
+/*! @name LOCKACCESS - Lock Access Register */
+#define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU)
+#define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U)
+#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK)
+
+/*! @name LOCKSTAT - Lock Status Register */
+#define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU)
+#define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U)
+#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK)
+
+/*! @name AUTHSTAT - Authentication Status Register */
+#define MTB_AUTHSTAT_BIT0_MASK (0x1U)
+#define MTB_AUTHSTAT_BIT0_SHIFT (0U)
+#define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK)
+#define MTB_AUTHSTAT_BIT1_MASK (0x2U)
+#define MTB_AUTHSTAT_BIT1_SHIFT (1U)
+#define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK)
+#define MTB_AUTHSTAT_BIT2_MASK (0x4U)
+#define MTB_AUTHSTAT_BIT2_SHIFT (2U)
+#define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK)
+#define MTB_AUTHSTAT_BIT3_MASK (0x8U)
+#define MTB_AUTHSTAT_BIT3_SHIFT (3U)
+#define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK)
+
+/*! @name DEVICEARCH - Device Architecture Register */
+#define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU)
+#define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U)
+#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK)
+
+/*! @name DEVICECFG - Device Configuration Register */
+#define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
+#define MTB_DEVICECFG_DEVICECFG_SHIFT (0U)
+#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK)
+
+/*! @name DEVICETYPID - Device Type Identifier Register */
+#define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
+#define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U)
+#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK)
+
+/*! @name PERIPHID4 - Peripheral ID Register */
+#define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTB_PERIPHID4_PERIPHID_SHIFT (0U)
+#define MTB_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK)
+
+/*! @name PERIPHID5 - Peripheral ID Register */
+#define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTB_PERIPHID5_PERIPHID_SHIFT (0U)
+#define MTB_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK)
+
+/*! @name PERIPHID6 - Peripheral ID Register */
+#define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTB_PERIPHID6_PERIPHID_SHIFT (0U)
+#define MTB_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK)
+
+/*! @name PERIPHID7 - Peripheral ID Register */
+#define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTB_PERIPHID7_PERIPHID_SHIFT (0U)
+#define MTB_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK)
+
+/*! @name PERIPHID0 - Peripheral ID Register */
+#define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTB_PERIPHID0_PERIPHID_SHIFT (0U)
+#define MTB_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK)
+
+/*! @name PERIPHID1 - Peripheral ID Register */
+#define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTB_PERIPHID1_PERIPHID_SHIFT (0U)
+#define MTB_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK)
+
+/*! @name PERIPHID2 - Peripheral ID Register */
+#define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTB_PERIPHID2_PERIPHID_SHIFT (0U)
+#define MTB_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK)
+
+/*! @name PERIPHID3 - Peripheral ID Register */
+#define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTB_PERIPHID3_PERIPHID_SHIFT (0U)
+#define MTB_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK)
+
+/*! @name COMPID - Component ID Register */
+#define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU)
+#define MTB_COMPID_COMPID_SHIFT (0U)
+#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK)
+
+/* The count of MTB_COMPID */
+#define MTB_COMPID_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group MTB_Register_Masks */
+
+
+/* MTB - Peripheral instance base addresses */
+/** Peripheral MTB base address */
+#define MTB_BASE (0xF0000000u)
+/** Peripheral MTB base pointer */
+#define MTB ((MTB_Type *)MTB_BASE)
+/** Array initializer of MTB peripheral base addresses */
+#define MTB_BASE_ADDRS { MTB_BASE }
+/** Array initializer of MTB peripheral base pointers */
+#define MTB_BASE_PTRS { MTB }
+
+/*!
+ * @}
+ */ /* end of group MTB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
+ * @{
+ */
+
+/** MTBDWT - Register Layout Typedef */
+typedef struct {
+ __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ struct { /* offset: 0x20, array step: 0x10 */
+ __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
+ __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
+ __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
+ uint8_t RESERVED_0[4];
+ } COMPARATOR[2];
+ uint8_t RESERVED_1[448];
+ __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
+ uint8_t RESERVED_2[3524];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
+ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
+ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
+ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
+ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
+ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
+ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
+ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTBDWT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
+ * @{
+ */
+
+/*! @name CTRL - MTB DWT Control Register */
+#define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU)
+#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U)
+#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK)
+#define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U)
+#define MTBDWT_CTRL_NUMCMP_SHIFT (28U)
+#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK)
+
+/*! @name COMP - MTB_DWT Comparator Register */
+#define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU)
+#define MTBDWT_COMP_COMP_SHIFT (0U)
+#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK)
+
+/* The count of MTBDWT_COMP */
+#define MTBDWT_COMP_COUNT (2U)
+
+/*! @name MASK - MTB_DWT Comparator Mask Register */
+#define MTBDWT_MASK_MASK_MASK (0x1FU)
+#define MTBDWT_MASK_MASK_SHIFT (0U)
+#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK)
+
+/* The count of MTBDWT_MASK */
+#define MTBDWT_MASK_COUNT (2U)
+
+/*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */
+#define MTBDWT_FCT_FUNCTION_MASK (0xFU)
+#define MTBDWT_FCT_FUNCTION_SHIFT (0U)
+#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK)
+#define MTBDWT_FCT_DATAVMATCH_MASK (0x100U)
+#define MTBDWT_FCT_DATAVMATCH_SHIFT (8U)
+#define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK)
+#define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U)
+#define MTBDWT_FCT_DATAVSIZE_SHIFT (10U)
+#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK)
+#define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U)
+#define MTBDWT_FCT_DATAVADDR0_SHIFT (12U)
+#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK)
+#define MTBDWT_FCT_MATCHED_MASK (0x1000000U)
+#define MTBDWT_FCT_MATCHED_SHIFT (24U)
+#define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK)
+
+/* The count of MTBDWT_FCT */
+#define MTBDWT_FCT_COUNT (2U)
+
+/*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */
+#define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U)
+#define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U)
+#define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK)
+#define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U)
+#define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U)
+#define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK)
+#define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U)
+#define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U)
+#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK)
+
+/*! @name DEVICECFG - Device Configuration Register */
+#define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
+#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U)
+#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK)
+
+/*! @name DEVICETYPID - Device Type Identifier Register */
+#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
+#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U)
+#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
+
+/*! @name PERIPHID4 - Peripheral ID Register */
+#define MTBDWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID4_PERIPHID_SHIFT (0U)
+#define MTBDWT_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK)
+
+/*! @name PERIPHID5 - Peripheral ID Register */
+#define MTBDWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID5_PERIPHID_SHIFT (0U)
+#define MTBDWT_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK)
+
+/*! @name PERIPHID6 - Peripheral ID Register */
+#define MTBDWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID6_PERIPHID_SHIFT (0U)
+#define MTBDWT_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK)
+
+/*! @name PERIPHID7 - Peripheral ID Register */
+#define MTBDWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID7_PERIPHID_SHIFT (0U)
+#define MTBDWT_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK)
+
+/*! @name PERIPHID0 - Peripheral ID Register */
+#define MTBDWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID0_PERIPHID_SHIFT (0U)
+#define MTBDWT_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK)
+
+/*! @name PERIPHID1 - Peripheral ID Register */
+#define MTBDWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID1_PERIPHID_SHIFT (0U)
+#define MTBDWT_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK)
+
+/*! @name PERIPHID2 - Peripheral ID Register */
+#define MTBDWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID2_PERIPHID_SHIFT (0U)
+#define MTBDWT_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK)
+
+/*! @name PERIPHID3 - Peripheral ID Register */
+#define MTBDWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID3_PERIPHID_SHIFT (0U)
+#define MTBDWT_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK)
+
+/*! @name COMPID - Component ID Register */
+#define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU)
+#define MTBDWT_COMPID_COMPID_SHIFT (0U)
+#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK)
+
+/* The count of MTBDWT_COMPID */
+#define MTBDWT_COMPID_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Register_Masks */
+
+
+/* MTBDWT - Peripheral instance base addresses */
+/** Peripheral MTBDWT base address */
+#define MTBDWT_BASE (0xF0001000u)
+/** Peripheral MTBDWT base pointer */
+#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
+/** Array initializer of MTBDWT peripheral base addresses */
+#define MTBDWT_BASE_ADDRS { MTBDWT_BASE }
+/** Array initializer of MTBDWT peripheral base pointers */
+#define MTBDWT_BASE_PTRS { MTBDWT }
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
+#define NV_BACKKEY3_KEY_MASK (0xFFU)
+#define NV_BACKKEY3_KEY_SHIFT (0U)
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
+
+/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
+#define NV_BACKKEY2_KEY_MASK (0xFFU)
+#define NV_BACKKEY2_KEY_SHIFT (0U)
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
+
+/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
+#define NV_BACKKEY1_KEY_MASK (0xFFU)
+#define NV_BACKKEY1_KEY_SHIFT (0U)
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
+
+/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
+#define NV_BACKKEY0_KEY_MASK (0xFFU)
+#define NV_BACKKEY0_KEY_SHIFT (0U)
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
+
+/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
+#define NV_BACKKEY7_KEY_MASK (0xFFU)
+#define NV_BACKKEY7_KEY_SHIFT (0U)
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
+
+/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
+#define NV_BACKKEY6_KEY_MASK (0xFFU)
+#define NV_BACKKEY6_KEY_SHIFT (0U)
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
+
+/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
+#define NV_BACKKEY5_KEY_MASK (0xFFU)
+#define NV_BACKKEY5_KEY_SHIFT (0U)
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
+
+/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
+#define NV_BACKKEY4_KEY_MASK (0xFFU)
+#define NV_BACKKEY4_KEY_SHIFT (0U)
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
+
+/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
+#define NV_FPROT3_PROT_MASK (0xFFU)
+#define NV_FPROT3_PROT_SHIFT (0U)
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
+#define NV_FPROT2_PROT_MASK (0xFFU)
+#define NV_FPROT2_PROT_SHIFT (0U)
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
+#define NV_FPROT1_PROT_MASK (0xFFU)
+#define NV_FPROT1_PROT_SHIFT (0U)
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
+#define NV_FPROT0_PROT_MASK (0xFFU)
+#define NV_FPROT0_PROT_SHIFT (0U)
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
+
+/*! @name FSEC - Non-volatile Flash Security Register */
+#define NV_FSEC_SEC_MASK (0x3U)
+#define NV_FSEC_SEC_SHIFT (0U)
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK (0xCU)
+#define NV_FSEC_FSLACC_SHIFT (2U)
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK (0x30U)
+#define NV_FSEC_MEEN_SHIFT (4U)
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK (0xC0U)
+#define NV_FSEC_KEYEN_SHIFT (6U)
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Non-volatile Flash Option Register */
+#define NV_FOPT_LPBOOT0_MASK (0x1U)
+#define NV_FOPT_LPBOOT0_SHIFT (0U)
+#define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK)
+#define NV_FOPT_NMI_DIS_MASK (0x4U)
+#define NV_FOPT_NMI_DIS_SHIFT (2U)
+#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
+#define NV_FOPT_RESET_PIN_CFG_MASK (0x8U)
+#define NV_FOPT_RESET_PIN_CFG_SHIFT (3U)
+#define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK)
+#define NV_FOPT_LPBOOT1_MASK (0x10U)
+#define NV_FOPT_LPBOOT1_SHIFT (4U)
+#define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK)
+#define NV_FOPT_FAST_INIT_MASK (0x20U)
+#define NV_FOPT_FAST_INIT_SHIFT (5U)
+#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFA_FlashConfig base address */
+#define FTFA_FlashConfig_BASE (0x400u)
+/** Peripheral FTFA_FlashConfig base pointer */
+#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS { FTFA_FlashConfig }
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/*! @name CR - OSC Control Register */
+#define OSC_CR_SC16P_MASK (0x1U)
+#define OSC_CR_SC16P_SHIFT (0U)
+#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
+#define OSC_CR_SC8P_MASK (0x2U)
+#define OSC_CR_SC8P_SHIFT (1U)
+#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
+#define OSC_CR_SC4P_MASK (0x4U)
+#define OSC_CR_SC4P_SHIFT (2U)
+#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
+#define OSC_CR_SC2P_MASK (0x8U)
+#define OSC_CR_SC2P_SHIFT (3U)
+#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
+#define OSC_CR_EREFSTEN_MASK (0x20U)
+#define OSC_CR_EREFSTEN_SHIFT (5U)
+#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
+#define OSC_CR_ERCLKEN_MASK (0x80U)
+#define OSC_CR_ERCLKEN_SHIFT (7U)
+#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0 ((OSC_Type *)OSC0_BASE)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS { OSC0_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS { OSC0 }
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[220];
+ __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
+ __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
+ uint8_t RESERVED_1[24];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[2];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/*! @name MCR - PIT Module Control Register */
+#define PIT_MCR_FRZ_MASK (0x1U)
+#define PIT_MCR_FRZ_SHIFT (0U)
+#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
+#define PIT_MCR_MDIS_MASK (0x2U)
+#define PIT_MCR_MDIS_SHIFT (1U)
+#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
+
+/*! @name LTMR64H - PIT Upper Lifetime Timer Register */
+#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
+#define PIT_LTMR64H_LTH_SHIFT (0U)
+#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
+
+/*! @name LTMR64L - PIT Lower Lifetime Timer Register */
+#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
+#define PIT_LTMR64L_LTL_SHIFT (0U)
+#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
+
+/*! @name LDVAL - Timer Load Value Register */
+#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
+#define PIT_LDVAL_TSV_SHIFT (0U)
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
+
+/* The count of PIT_LDVAL */
+#define PIT_LDVAL_COUNT (2U)
+
+/*! @name CVAL - Current Timer Value Register */
+#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
+#define PIT_CVAL_TVL_SHIFT (0U)
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
+
+/* The count of PIT_CVAL */
+#define PIT_CVAL_COUNT (2U)
+
+/*! @name TCTRL - Timer Control Register */
+#define PIT_TCTRL_TEN_MASK (0x1U)
+#define PIT_TCTRL_TEN_SHIFT (0U)
+#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
+#define PIT_TCTRL_TIE_MASK (0x2U)
+#define PIT_TCTRL_TIE_SHIFT (1U)
+#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
+#define PIT_TCTRL_CHN_MASK (0x4U)
+#define PIT_TCTRL_CHN_SHIFT (2U)
+#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
+
+/* The count of PIT_TCTRL */
+#define PIT_TCTRL_COUNT (2U)
+
+/*! @name TFLG - Timer Flag Register */
+#define PIT_TFLG_TIF_MASK (0x1U)
+#define PIT_TFLG_TIF_SHIFT (0U)
+#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
+
+/* The count of PIT_TFLG */
+#define PIT_TFLG_COUNT (2U)
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
+#define PMC_LVDSC1_LVDV_MASK (0x3U)
+#define PMC_LVDSC1_LVDV_SHIFT (0U)
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK (0x10U)
+#define PMC_LVDSC1_LVDRE_SHIFT (4U)
+#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDIE_MASK (0x20U)
+#define PMC_LVDSC1_LVDIE_SHIFT (5U)
+#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDACK_MASK (0x40U)
+#define PMC_LVDSC1_LVDACK_SHIFT (6U)
+#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDF_MASK (0x80U)
+#define PMC_LVDSC1_LVDF_SHIFT (7U)
+#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
+
+/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
+#define PMC_LVDSC2_LVWV_MASK (0x3U)
+#define PMC_LVDSC2_LVWV_SHIFT (0U)
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK (0x20U)
+#define PMC_LVDSC2_LVWIE_SHIFT (5U)
+#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWACK_MASK (0x40U)
+#define PMC_LVDSC2_LVWACK_SHIFT (6U)
+#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWF_MASK (0x80U)
+#define PMC_LVDSC2_LVWF_SHIFT (7U)
+#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
+
+/*! @name REGSC - Regulator Status And Control register */
+#define PMC_REGSC_BGBE_MASK (0x1U)
+#define PMC_REGSC_BGBE_SHIFT (0U)
+#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_REGONS_MASK (0x4U)
+#define PMC_REGSC_REGONS_SHIFT (2U)
+#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_ACKISO_MASK (0x8U)
+#define PMC_REGSC_ACKISO_SHIFT (3U)
+#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_BGEN_MASK (0x10U)
+#define PMC_REGSC_BGEN_SHIFT (4U)
+#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS { LVD_LVW_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/*! @name PCR - Pin Control Register n */
+#define PORT_PCR_PS_MASK (0x1U)
+#define PORT_PCR_PS_SHIFT (0U)
+#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK (0x2U)
+#define PORT_PCR_PE_SHIFT (1U)
+#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK (0x4U)
+#define PORT_PCR_SRE_SHIFT (2U)
+#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK (0x10U)
+#define PORT_PCR_PFE_SHIFT (4U)
+#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
+#define PORT_PCR_DSE_MASK (0x40U)
+#define PORT_PCR_DSE_SHIFT (6U)
+#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
+#define PORT_PCR_MUX_MASK (0x700U)
+#define PORT_PCR_MUX_SHIFT (8U)
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
+#define PORT_PCR_IRQC_MASK (0xF0000U)
+#define PORT_PCR_IRQC_SHIFT (16U)
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK (0x1000000U)
+#define PORT_PCR_ISF_SHIFT (24U)
+#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
+
+/* The count of PORT_PCR */
+#define PORT_PCR_COUNT (32U)
+
+/*! @name GPCLR - Global Pin Control Low Register */
+#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
+#define PORT_GPCLR_GPWD_SHIFT (0U)
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
+#define PORT_GPCLR_GPWE_SHIFT (16U)
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
+
+/*! @name GPCHR - Global Pin Control High Register */
+#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
+#define PORT_GPCHR_GPWD_SHIFT (0U)
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
+#define PORT_GPCHR_GPWE_SHIFT (16U)
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
+
+/*! @name ISFR - Interrupt Status Flag Register */
+#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
+#define PORT_ISFR_ISF_SHIFT (0U)
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS { PORTA_IRQn, NotAvail_IRQn, PORTC_PORTD_IRQn, PORTC_PORTD_IRQn, NotAvail_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/*! @name SRS0 - System Reset Status Register 0 */
+#define RCM_SRS0_WAKEUP_MASK (0x1U)
+#define RCM_SRS0_WAKEUP_SHIFT (0U)
+#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_LVD_MASK (0x2U)
+#define RCM_SRS0_LVD_SHIFT (1U)
+#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LOC_MASK (0x4U)
+#define RCM_SRS0_LOC_SHIFT (2U)
+#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_LOL_MASK (0x8U)
+#define RCM_SRS0_LOL_SHIFT (3U)
+#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
+#define RCM_SRS0_WDOG_MASK (0x20U)
+#define RCM_SRS0_WDOG_SHIFT (5U)
+#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_PIN_MASK (0x40U)
+#define RCM_SRS0_PIN_SHIFT (6U)
+#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_POR_MASK (0x80U)
+#define RCM_SRS0_POR_SHIFT (7U)
+#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
+
+/*! @name SRS1 - System Reset Status Register 1 */
+#define RCM_SRS1_LOCKUP_MASK (0x2U)
+#define RCM_SRS1_LOCKUP_SHIFT (1U)
+#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_SW_MASK (0x4U)
+#define RCM_SRS1_SW_SHIFT (2U)
+#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
+#define RCM_SRS1_MDM_AP_MASK (0x8U)
+#define RCM_SRS1_MDM_AP_SHIFT (3U)
+#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_SACKERR_MASK (0x20U)
+#define RCM_SRS1_SACKERR_SHIFT (5U)
+#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
+
+/*! @name RPFC - Reset Pin Filter Control register */
+#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
+#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
+#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
+#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
+
+/*! @name RPFW - Reset Pin Filter Width register */
+#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
+#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS { RCM }
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ROM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
+ * @{
+ */
+
+/** ROM - Register Layout Typedef */
+typedef struct {
+ __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
+ __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
+ uint8_t RESERVED_0[4028];
+ __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
+ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
+ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
+ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
+ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
+ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
+ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
+ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
+ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} ROM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ROM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Register_Masks ROM Register Masks
+ * @{
+ */
+
+/*! @name ENTRY - Entry */
+#define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU)
+#define ROM_ENTRY_ENTRY_SHIFT (0U)
+#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK)
+
+/* The count of ROM_ENTRY */
+#define ROM_ENTRY_COUNT (3U)
+
+/*! @name TABLEMARK - End of Table Marker Register */
+#define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU)
+#define ROM_TABLEMARK_MARK_SHIFT (0U)
+#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK)
+
+/*! @name SYSACCESS - System Access Register */
+#define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU)
+#define ROM_SYSACCESS_SYSACCESS_SHIFT (0U)
+#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK)
+
+/*! @name PERIPHID4 - Peripheral ID Register */
+#define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
+#define ROM_PERIPHID4_PERIPHID_SHIFT (0U)
+#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK)
+
+/*! @name PERIPHID5 - Peripheral ID Register */
+#define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
+#define ROM_PERIPHID5_PERIPHID_SHIFT (0U)
+#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK)
+
+/*! @name PERIPHID6 - Peripheral ID Register */
+#define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
+#define ROM_PERIPHID6_PERIPHID_SHIFT (0U)
+#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK)
+
+/*! @name PERIPHID7 - Peripheral ID Register */
+#define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
+#define ROM_PERIPHID7_PERIPHID_SHIFT (0U)
+#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK)
+
+/*! @name PERIPHID0 - Peripheral ID Register */
+#define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
+#define ROM_PERIPHID0_PERIPHID_SHIFT (0U)
+#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK)
+
+/*! @name PERIPHID1 - Peripheral ID Register */
+#define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
+#define ROM_PERIPHID1_PERIPHID_SHIFT (0U)
+#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK)
+
+/*! @name PERIPHID2 - Peripheral ID Register */
+#define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
+#define ROM_PERIPHID2_PERIPHID_SHIFT (0U)
+#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK)
+
+/*! @name PERIPHID3 - Peripheral ID Register */
+#define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
+#define ROM_PERIPHID3_PERIPHID_SHIFT (0U)
+#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK)
+
+/*! @name COMPID - Component ID Register */
+#define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU)
+#define ROM_COMPID_COMPID_SHIFT (0U)
+#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK)
+
+/* The count of ROM_COMPID */
+#define ROM_COMPID_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group ROM_Register_Masks */
+
+
+/* ROM - Peripheral instance base addresses */
+/** Peripheral ROM base address */
+#define ROM_BASE (0xF0002000u)
+/** Peripheral ROM base pointer */
+#define ROM ((ROM_Type *)ROM_BASE)
+/** Array initializer of ROM peripheral base addresses */
+#define ROM_BASE_ADDRS { ROM_BASE }
+/** Array initializer of ROM peripheral base pointers */
+#define ROM_BASE_PTRS { ROM }
+
+/*!
+ * @}
+ */ /* end of group ROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name TSR - RTC Time Seconds Register */
+#define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
+#define RTC_TSR_TSR_SHIFT (0U)
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
+
+/*! @name TPR - RTC Time Prescaler Register */
+#define RTC_TPR_TPR_MASK (0xFFFFU)
+#define RTC_TPR_TPR_SHIFT (0U)
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
+
+/*! @name TAR - RTC Time Alarm Register */
+#define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
+#define RTC_TAR_TAR_SHIFT (0U)
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
+
+/*! @name TCR - RTC Time Compensation Register */
+#define RTC_TCR_TCR_MASK (0xFFU)
+#define RTC_TCR_TCR_SHIFT (0U)
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK (0xFF00U)
+#define RTC_TCR_CIR_SHIFT (8U)
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK (0xFF0000U)
+#define RTC_TCR_TCV_SHIFT (16U)
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK (0xFF000000U)
+#define RTC_TCR_CIC_SHIFT (24U)
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
+
+/*! @name CR - RTC Control Register */
+#define RTC_CR_SWR_MASK (0x1U)
+#define RTC_CR_SWR_SHIFT (0U)
+#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK (0x2U)
+#define RTC_CR_WPE_SHIFT (1U)
+#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK (0x4U)
+#define RTC_CR_SUP_SHIFT (2U)
+#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK (0x8U)
+#define RTC_CR_UM_SHIFT (3U)
+#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
+#define RTC_CR_WPS_MASK (0x10U)
+#define RTC_CR_WPS_SHIFT (4U)
+#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
+#define RTC_CR_OSCE_MASK (0x100U)
+#define RTC_CR_OSCE_SHIFT (8U)
+#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK (0x200U)
+#define RTC_CR_CLKO_SHIFT (9U)
+#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK (0x400U)
+#define RTC_CR_SC16P_SHIFT (10U)
+#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK (0x800U)
+#define RTC_CR_SC8P_SHIFT (11U)
+#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK (0x1000U)
+#define RTC_CR_SC4P_SHIFT (12U)
+#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK (0x2000U)
+#define RTC_CR_SC2P_SHIFT (13U)
+#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
+
+/*! @name SR - RTC Status Register */
+#define RTC_SR_TIF_MASK (0x1U)
+#define RTC_SR_TIF_SHIFT (0U)
+#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK (0x2U)
+#define RTC_SR_TOF_SHIFT (1U)
+#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK (0x4U)
+#define RTC_SR_TAF_SHIFT (2U)
+#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
+#define RTC_SR_TCE_MASK (0x10U)
+#define RTC_SR_TCE_SHIFT (4U)
+#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
+
+/*! @name LR - RTC Lock Register */
+#define RTC_LR_TCL_MASK (0x8U)
+#define RTC_LR_TCL_SHIFT (3U)
+#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK (0x10U)
+#define RTC_LR_CRL_SHIFT (4U)
+#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK (0x20U)
+#define RTC_LR_SRL_SHIFT (5U)
+#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK (0x40U)
+#define RTC_LR_LRL_SHIFT (6U)
+#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
+
+/*! @name IER - RTC Interrupt Enable Register */
+#define RTC_IER_TIIE_MASK (0x1U)
+#define RTC_IER_TIIE_SHIFT (0U)
+#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK (0x2U)
+#define RTC_IER_TOIE_SHIFT (1U)
+#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK (0x4U)
+#define RTC_IER_TAIE_SHIFT (2U)
+#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
+#define RTC_IER_TSIE_MASK (0x10U)
+#define RTC_IER_TSIE_SHIFT (4U)
+#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK (0x80U)
+#define RTC_IER_WPON_SHIFT (7U)
+#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS { RTC_IRQn }
+#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ uint8_t RESERVED_5[4];
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ uint8_t RESERVED_6[4];
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+ uint8_t RESERVED_7[156];
+ __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
+ __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/*! @name SOPT1 - System Options Register 1 */
+#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
+#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
+#define SIM_SOPT1_USBVSTBY_SHIFT (29U)
+#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
+#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
+#define SIM_SOPT1_USBSSTBY_SHIFT (30U)
+#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
+#define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
+#define SIM_SOPT1_USBREGEN_SHIFT (31U)
+#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
+
+/*! @name SOPT1CFG - SOPT1 Configuration Register */
+#define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
+#define SIM_SOPT1CFG_URWE_SHIFT (24U)
+#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
+#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
+#define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
+#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
+#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
+#define SIM_SOPT1CFG_USSWE_SHIFT (26U)
+#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
+
+/*! @name SOPT2 - System Options Register 2 */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
+#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
+#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK (0x10000U)
+#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
+#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK (0x40000U)
+#define SIM_SOPT2_USBSRC_SHIFT (18U)
+#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
+#define SIM_SOPT2_TPMSRC_MASK (0x3000000U)
+#define SIM_SOPT2_TPMSRC_SHIFT (24U)
+#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_UART0SRC_MASK (0xC000000U)
+#define SIM_SOPT2_UART0SRC_SHIFT (26U)
+#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_UART0SRC_SHIFT)) & SIM_SOPT2_UART0SRC_MASK)
+
+/*! @name SOPT4 - System Options Register 4 */
+#define SIM_SOPT4_TPM1CH0SRC_MASK (0xC0000U)
+#define SIM_SOPT4_TPM1CH0SRC_SHIFT (18U)
+#define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CH0SRC_SHIFT)) & SIM_SOPT4_TPM1CH0SRC_MASK)
+#define SIM_SOPT4_TPM2CH0SRC_MASK (0x100000U)
+#define SIM_SOPT4_TPM2CH0SRC_SHIFT (20U)
+#define SIM_SOPT4_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CH0SRC_SHIFT)) & SIM_SOPT4_TPM2CH0SRC_MASK)
+#define SIM_SOPT4_TPM0CLKSEL_MASK (0x1000000U)
+#define SIM_SOPT4_TPM0CLKSEL_SHIFT (24U)
+#define SIM_SOPT4_TPM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM0CLKSEL_SHIFT)) & SIM_SOPT4_TPM0CLKSEL_MASK)
+#define SIM_SOPT4_TPM1CLKSEL_MASK (0x2000000U)
+#define SIM_SOPT4_TPM1CLKSEL_SHIFT (25U)
+#define SIM_SOPT4_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CLKSEL_SHIFT)) & SIM_SOPT4_TPM1CLKSEL_MASK)
+#define SIM_SOPT4_TPM2CLKSEL_MASK (0x4000000U)
+#define SIM_SOPT4_TPM2CLKSEL_SHIFT (26U)
+#define SIM_SOPT4_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CLKSEL_SHIFT)) & SIM_SOPT4_TPM2CLKSEL_MASK)
+
+/*! @name SOPT5 - System Options Register 5 */
+#define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
+#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
+#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK (0x4U)
+#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
+#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
+#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
+#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK (0x40U)
+#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
+#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
+#define SIM_SOPT5_UART0ODE_MASK (0x10000U)
+#define SIM_SOPT5_UART0ODE_SHIFT (16U)
+#define SIM_SOPT5_UART0ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0ODE_SHIFT)) & SIM_SOPT5_UART0ODE_MASK)
+#define SIM_SOPT5_UART1ODE_MASK (0x20000U)
+#define SIM_SOPT5_UART1ODE_SHIFT (17U)
+#define SIM_SOPT5_UART1ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1ODE_SHIFT)) & SIM_SOPT5_UART1ODE_MASK)
+#define SIM_SOPT5_UART2ODE_MASK (0x40000U)
+#define SIM_SOPT5_UART2ODE_SHIFT (18U)
+#define SIM_SOPT5_UART2ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART2ODE_SHIFT)) & SIM_SOPT5_UART2ODE_MASK)
+
+/*! @name SOPT7 - System Options Register 7 */
+#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
+#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
+#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
+
+/*! @name SDID - System Device Identification Register */
+#define SIM_SDID_PINID_MASK (0xFU)
+#define SIM_SDID_PINID_SHIFT (0U)
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
+#define SIM_SDID_DIEID_MASK (0xF80U)
+#define SIM_SDID_DIEID_SHIFT (7U)
+#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK (0xF000U)
+#define SIM_SDID_REVID_SHIFT (12U)
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
+#define SIM_SDID_SRAMSIZE_MASK (0xF0000U)
+#define SIM_SDID_SRAMSIZE_SHIFT (16U)
+#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK)
+#define SIM_SDID_SERIESID_MASK (0xF00000U)
+#define SIM_SDID_SERIESID_SHIFT (20U)
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK (0xF000000U)
+#define SIM_SDID_SUBFAMID_SHIFT (24U)
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMID_MASK (0xF0000000U)
+#define SIM_SDID_FAMID_SHIFT (28U)
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
+
+/*! @name SCGC4 - System Clock Gating Control Register 4 */
+#define SIM_SCGC4_I2C0_MASK (0x40U)
+#define SIM_SCGC4_I2C0_SHIFT (6U)
+#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C1_MASK (0x80U)
+#define SIM_SCGC4_I2C1_SHIFT (7U)
+#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_UART0_MASK (0x400U)
+#define SIM_SCGC4_UART0_SHIFT (10U)
+#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
+#define SIM_SCGC4_UART1_MASK (0x800U)
+#define SIM_SCGC4_UART1_SHIFT (11U)
+#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
+#define SIM_SCGC4_UART2_MASK (0x1000U)
+#define SIM_SCGC4_UART2_SHIFT (12U)
+#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_USBOTG_MASK (0x40000U)
+#define SIM_SCGC4_USBOTG_SHIFT (18U)
+#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
+#define SIM_SCGC4_CMP_MASK (0x80000U)
+#define SIM_SCGC4_CMP_SHIFT (19U)
+#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_SPI0_MASK (0x400000U)
+#define SIM_SCGC4_SPI0_SHIFT (22U)
+#define SIM_SCGC4_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI0_SHIFT)) & SIM_SCGC4_SPI0_MASK)
+#define SIM_SCGC4_SPI1_MASK (0x800000U)
+#define SIM_SCGC4_SPI1_SHIFT (23U)
+#define SIM_SCGC4_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI1_SHIFT)) & SIM_SCGC4_SPI1_MASK)
+
+/*! @name SCGC5 - System Clock Gating Control Register 5 */
+#define SIM_SCGC5_LPTMR_MASK (0x1U)
+#define SIM_SCGC5_LPTMR_SHIFT (0U)
+#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
+#define SIM_SCGC5_TSI_MASK (0x20U)
+#define SIM_SCGC5_TSI_SHIFT (5U)
+#define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
+#define SIM_SCGC5_PORTA_MASK (0x200U)
+#define SIM_SCGC5_PORTA_SHIFT (9U)
+#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
+#define SIM_SCGC5_PORTB_MASK (0x400U)
+#define SIM_SCGC5_PORTB_SHIFT (10U)
+#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
+#define SIM_SCGC5_PORTC_MASK (0x800U)
+#define SIM_SCGC5_PORTC_SHIFT (11U)
+#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
+#define SIM_SCGC5_PORTD_MASK (0x1000U)
+#define SIM_SCGC5_PORTD_SHIFT (12U)
+#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
+#define SIM_SCGC5_PORTE_MASK (0x2000U)
+#define SIM_SCGC5_PORTE_SHIFT (13U)
+#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
+
+/*! @name SCGC6 - System Clock Gating Control Register 6 */
+#define SIM_SCGC6_FTF_MASK (0x1U)
+#define SIM_SCGC6_FTF_SHIFT (0U)
+#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
+#define SIM_SCGC6_DMAMUX_MASK (0x2U)
+#define SIM_SCGC6_DMAMUX_SHIFT (1U)
+#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_I2S_MASK (0x8000U)
+#define SIM_SCGC6_I2S_SHIFT (15U)
+#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_PIT_MASK (0x800000U)
+#define SIM_SCGC6_PIT_SHIFT (23U)
+#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_TPM0_MASK (0x1000000U)
+#define SIM_SCGC6_TPM0_SHIFT (24U)
+#define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK)
+#define SIM_SCGC6_TPM1_MASK (0x2000000U)
+#define SIM_SCGC6_TPM1_SHIFT (25U)
+#define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK)
+#define SIM_SCGC6_TPM2_MASK (0x4000000U)
+#define SIM_SCGC6_TPM2_SHIFT (26U)
+#define SIM_SCGC6_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK)
+#define SIM_SCGC6_ADC0_MASK (0x8000000U)
+#define SIM_SCGC6_ADC0_SHIFT (27U)
+#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_RTC_MASK (0x20000000U)
+#define SIM_SCGC6_RTC_SHIFT (29U)
+#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
+#define SIM_SCGC6_DAC0_MASK (0x80000000U)
+#define SIM_SCGC6_DAC0_SHIFT (31U)
+#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
+
+/*! @name SCGC7 - System Clock Gating Control Register 7 */
+#define SIM_SCGC7_DMA_MASK (0x100U)
+#define SIM_SCGC7_DMA_SHIFT (8U)
+#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
+
+/*! @name CLKDIV1 - System Clock Divider Register 1 */
+#define SIM_CLKDIV1_OUTDIV4_MASK (0x70000U)
+#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
+#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
+
+/*! @name FCFG1 - Flash Configuration Register 1 */
+#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
+#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
+#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
+#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
+#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
+#define SIM_FCFG1_PFSIZE_SHIFT (24U)
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
+
+/*! @name FCFG2 - Flash Configuration Register 2 */
+#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
+#define SIM_FCFG2_MAXADDR1_SHIFT (16U)
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
+#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
+
+/*! @name UIDMH - Unique Identification Register Mid-High */
+#define SIM_UIDMH_UID_MASK (0xFFFFU)
+#define SIM_UIDMH_UID_SHIFT (0U)
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
+
+/*! @name UIDML - Unique Identification Register Mid Low */
+#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDML_UID_SHIFT (0U)
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
+
+/*! @name UIDL - Unique Identification Register Low */
+#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDL_UID_SHIFT (0U)
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
+
+/*! @name COPC - COP Control Register */
+#define SIM_COPC_COPW_MASK (0x1U)
+#define SIM_COPC_COPW_SHIFT (0U)
+#define SIM_COPC_COPW(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPW_SHIFT)) & SIM_COPC_COPW_MASK)
+#define SIM_COPC_COPCLKS_MASK (0x2U)
+#define SIM_COPC_COPCLKS_SHIFT (1U)
+#define SIM_COPC_COPCLKS(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKS_SHIFT)) & SIM_COPC_COPCLKS_MASK)
+#define SIM_COPC_COPT_MASK (0xCU)
+#define SIM_COPC_COPT_SHIFT (2U)
+#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPT_SHIFT)) & SIM_COPC_COPT_MASK)
+
+/*! @name SRVCOP - Service COP */
+#define SIM_SRVCOP_SRVCOP_MASK (0xFFU)
+#define SIM_SRVCOP_SRVCOP_SHIFT (0U)
+#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRVCOP_SRVCOP_SHIFT)) & SIM_SRVCOP_SRVCOP_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS { SIM }
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
+ __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/*! @name PMPROT - Power Mode Protection register */
+#define SMC_PMPROT_AVLLS_MASK (0x2U)
+#define SMC_PMPROT_AVLLS_SHIFT (1U)
+#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK (0x8U)
+#define SMC_PMPROT_ALLS_SHIFT (3U)
+#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK (0x20U)
+#define SMC_PMPROT_AVLP_SHIFT (5U)
+#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
+
+/*! @name PMCTRL - Power Mode Control register */
+#define SMC_PMCTRL_STOPM_MASK (0x7U)
+#define SMC_PMCTRL_STOPM_SHIFT (0U)
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK (0x8U)
+#define SMC_PMCTRL_STOPA_SHIFT (3U)
+#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_RUNM_MASK (0x60U)
+#define SMC_PMCTRL_RUNM_SHIFT (5U)
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
+
+/*! @name STOPCTRL - Stop Control Register */
+#define SMC_STOPCTRL_VLLSM_MASK (0x7U)
+#define SMC_STOPCTRL_VLLSM_SHIFT (0U)
+#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_VLLSM_SHIFT)) & SMC_STOPCTRL_VLLSM_MASK)
+#define SMC_STOPCTRL_PORPO_MASK (0x20U)
+#define SMC_STOPCTRL_PORPO_SHIFT (5U)
+#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
+#define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
+#define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
+#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
+
+/*! @name PMSTAT - Power Mode Status register */
+#define SMC_PMSTAT_PMSTAT_MASK (0x7FU)
+#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS { SMC }
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t S; /**< SPI Status Register, offset: 0x0 */
+ __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */
+ __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */
+ __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */
+ __IO uint8_t ML; /**< SPI Match Register low, offset: 0x4 */
+ __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
+ __IO uint8_t DL; /**< SPI Data Register low, offset: 0x6 */
+ __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
+ __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/*! @name S - SPI Status Register */
+#define SPI_S_RFIFOEF_MASK (0x1U)
+#define SPI_S_RFIFOEF_SHIFT (0U)
+#define SPI_S_RFIFOEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RFIFOEF_SHIFT)) & SPI_S_RFIFOEF_MASK)
+#define SPI_S_TXFULLF_MASK (0x2U)
+#define SPI_S_TXFULLF_SHIFT (1U)
+#define SPI_S_TXFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TXFULLF_SHIFT)) & SPI_S_TXFULLF_MASK)
+#define SPI_S_TNEAREF_MASK (0x4U)
+#define SPI_S_TNEAREF_SHIFT (2U)
+#define SPI_S_TNEAREF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TNEAREF_SHIFT)) & SPI_S_TNEAREF_MASK)
+#define SPI_S_RNFULLF_MASK (0x8U)
+#define SPI_S_RNFULLF_SHIFT (3U)
+#define SPI_S_RNFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RNFULLF_SHIFT)) & SPI_S_RNFULLF_MASK)
+#define SPI_S_MODF_MASK (0x10U)
+#define SPI_S_MODF_SHIFT (4U)
+#define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK)
+#define SPI_S_SPTEF_MASK (0x20U)
+#define SPI_S_SPTEF_SHIFT (5U)
+#define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK)
+#define SPI_S_SPMF_MASK (0x40U)
+#define SPI_S_SPMF_SHIFT (6U)
+#define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK)
+#define SPI_S_SPRF_MASK (0x80U)
+#define SPI_S_SPRF_SHIFT (7U)
+#define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK)
+
+/*! @name BR - SPI Baud Rate Register */
+#define SPI_BR_SPR_MASK (0xFU)
+#define SPI_BR_SPR_SHIFT (0U)
+#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK)
+#define SPI_BR_SPPR_MASK (0x70U)
+#define SPI_BR_SPPR_SHIFT (4U)
+#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK)
+
+/*! @name C2 - SPI Control Register 2 */
+#define SPI_C2_SPC0_MASK (0x1U)
+#define SPI_C2_SPC0_SHIFT (0U)
+#define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK)
+#define SPI_C2_SPISWAI_MASK (0x2U)
+#define SPI_C2_SPISWAI_SHIFT (1U)
+#define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK)
+#define SPI_C2_RXDMAE_MASK (0x4U)
+#define SPI_C2_RXDMAE_SHIFT (2U)
+#define SPI_C2_RXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_RXDMAE_SHIFT)) & SPI_C2_RXDMAE_MASK)
+#define SPI_C2_BIDIROE_MASK (0x8U)
+#define SPI_C2_BIDIROE_SHIFT (3U)
+#define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK)
+#define SPI_C2_MODFEN_MASK (0x10U)
+#define SPI_C2_MODFEN_SHIFT (4U)
+#define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK)
+#define SPI_C2_TXDMAE_MASK (0x20U)
+#define SPI_C2_TXDMAE_SHIFT (5U)
+#define SPI_C2_TXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_TXDMAE_SHIFT)) & SPI_C2_TXDMAE_MASK)
+#define SPI_C2_SPIMODE_MASK (0x40U)
+#define SPI_C2_SPIMODE_SHIFT (6U)
+#define SPI_C2_SPIMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPIMODE_SHIFT)) & SPI_C2_SPIMODE_MASK)
+#define SPI_C2_SPMIE_MASK (0x80U)
+#define SPI_C2_SPMIE_SHIFT (7U)
+#define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK)
+
+/*! @name C1 - SPI Control Register 1 */
+#define SPI_C1_LSBFE_MASK (0x1U)
+#define SPI_C1_LSBFE_SHIFT (0U)
+#define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK)
+#define SPI_C1_SSOE_MASK (0x2U)
+#define SPI_C1_SSOE_SHIFT (1U)
+#define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK)
+#define SPI_C1_CPHA_MASK (0x4U)
+#define SPI_C1_CPHA_SHIFT (2U)
+#define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK)
+#define SPI_C1_CPOL_MASK (0x8U)
+#define SPI_C1_CPOL_SHIFT (3U)
+#define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK)
+#define SPI_C1_MSTR_MASK (0x10U)
+#define SPI_C1_MSTR_SHIFT (4U)
+#define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK)
+#define SPI_C1_SPTIE_MASK (0x20U)
+#define SPI_C1_SPTIE_SHIFT (5U)
+#define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK)
+#define SPI_C1_SPE_MASK (0x40U)
+#define SPI_C1_SPE_SHIFT (6U)
+#define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK)
+#define SPI_C1_SPIE_MASK (0x80U)
+#define SPI_C1_SPIE_SHIFT (7U)
+#define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK)
+
+/*! @name ML - SPI Match Register low */
+#define SPI_ML_Bits_MASK (0xFFU)
+#define SPI_ML_Bits_SHIFT (0U)
+#define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_ML_Bits_SHIFT)) & SPI_ML_Bits_MASK)
+
+/*! @name MH - SPI match register high */
+#define SPI_MH_Bits_MASK (0xFFU)
+#define SPI_MH_Bits_SHIFT (0U)
+#define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_MH_Bits_SHIFT)) & SPI_MH_Bits_MASK)
+
+/*! @name DL - SPI Data Register low */
+#define SPI_DL_Bits_MASK (0xFFU)
+#define SPI_DL_Bits_SHIFT (0U)
+#define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DL_Bits_SHIFT)) & SPI_DL_Bits_MASK)
+
+/*! @name DH - SPI data register high */
+#define SPI_DH_Bits_MASK (0xFFU)
+#define SPI_DH_Bits_SHIFT (0U)
+#define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DH_Bits_SHIFT)) & SPI_DH_Bits_MASK)
+
+/*! @name CI - SPI clear interrupt register */
+#define SPI_CI_SPRFCI_MASK (0x1U)
+#define SPI_CI_SPRFCI_SHIFT (0U)
+#define SPI_CI_SPRFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPRFCI_SHIFT)) & SPI_CI_SPRFCI_MASK)
+#define SPI_CI_SPTEFCI_MASK (0x2U)
+#define SPI_CI_SPTEFCI_SHIFT (1U)
+#define SPI_CI_SPTEFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPTEFCI_SHIFT)) & SPI_CI_SPTEFCI_MASK)
+#define SPI_CI_RNFULLFCI_MASK (0x4U)
+#define SPI_CI_RNFULLFCI_SHIFT (2U)
+#define SPI_CI_RNFULLFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RNFULLFCI_SHIFT)) & SPI_CI_RNFULLFCI_MASK)
+#define SPI_CI_TNEAREFCI_MASK (0x8U)
+#define SPI_CI_TNEAREFCI_SHIFT (3U)
+#define SPI_CI_TNEAREFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TNEAREFCI_SHIFT)) & SPI_CI_TNEAREFCI_MASK)
+#define SPI_CI_RXFOF_MASK (0x10U)
+#define SPI_CI_RXFOF_SHIFT (4U)
+#define SPI_CI_RXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFOF_SHIFT)) & SPI_CI_RXFOF_MASK)
+#define SPI_CI_TXFOF_MASK (0x20U)
+#define SPI_CI_TXFOF_SHIFT (5U)
+#define SPI_CI_TXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFOF_SHIFT)) & SPI_CI_TXFOF_MASK)
+#define SPI_CI_RXFERR_MASK (0x40U)
+#define SPI_CI_RXFERR_SHIFT (6U)
+#define SPI_CI_RXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFERR_SHIFT)) & SPI_CI_RXFERR_MASK)
+#define SPI_CI_TXFERR_MASK (0x80U)
+#define SPI_CI_TXFERR_SHIFT (7U)
+#define SPI_CI_TXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFERR_SHIFT)) & SPI_CI_TXFERR_MASK)
+
+/*! @name C3 - SPI control register 3 */
+#define SPI_C3_FIFOMODE_MASK (0x1U)
+#define SPI_C3_FIFOMODE_SHIFT (0U)
+#define SPI_C3_FIFOMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_FIFOMODE_SHIFT)) & SPI_C3_FIFOMODE_MASK)
+#define SPI_C3_RNFULLIEN_MASK (0x2U)
+#define SPI_C3_RNFULLIEN_SHIFT (1U)
+#define SPI_C3_RNFULLIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLIEN_SHIFT)) & SPI_C3_RNFULLIEN_MASK)
+#define SPI_C3_TNEARIEN_MASK (0x4U)
+#define SPI_C3_TNEARIEN_SHIFT (2U)
+#define SPI_C3_TNEARIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEARIEN_SHIFT)) & SPI_C3_TNEARIEN_MASK)
+#define SPI_C3_INTCLR_MASK (0x8U)
+#define SPI_C3_INTCLR_SHIFT (3U)
+#define SPI_C3_INTCLR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_INTCLR_SHIFT)) & SPI_C3_INTCLR_MASK)
+#define SPI_C3_RNFULLF_MARK_MASK (0x10U)
+#define SPI_C3_RNFULLF_MARK_SHIFT (4U)
+#define SPI_C3_RNFULLF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLF_MARK_SHIFT)) & SPI_C3_RNFULLF_MARK_MASK)
+#define SPI_C3_TNEAREF_MARK_MASK (0x20U)
+#define SPI_C3_TNEAREF_MARK_SHIFT (5U)
+#define SPI_C3_TNEAREF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEAREF_MARK_SHIFT)) & SPI_C3_TNEAREF_MARK_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x40076000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE (0x40077000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1 ((SPI_Type *)SPI1_BASE)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS { SPI0, SPI1 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TPM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[6];
+ uint8_t RESERVED_0[20];
+ __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+} TPM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TPM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/*! @name SC - Status and Control */
+#define TPM_SC_PS_MASK (0x7U)
+#define TPM_SC_PS_SHIFT (0U)
+#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK (0x18U)
+#define TPM_SC_CMOD_SHIFT (3U)
+#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK (0x20U)
+#define TPM_SC_CPWMS_SHIFT (5U)
+#define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
+#define TPM_SC_TOIE_MASK (0x40U)
+#define TPM_SC_TOIE_SHIFT (6U)
+#define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
+#define TPM_SC_TOF_MASK (0x80U)
+#define TPM_SC_TOF_SHIFT (7U)
+#define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
+#define TPM_SC_DMA_MASK (0x100U)
+#define TPM_SC_DMA_SHIFT (8U)
+#define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
+
+/*! @name CNT - Counter */
+#define TPM_CNT_COUNT_MASK (0xFFFFU)
+#define TPM_CNT_COUNT_SHIFT (0U)
+#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
+
+/*! @name MOD - Modulo */
+#define TPM_MOD_MOD_MASK (0xFFFFU)
+#define TPM_MOD_MOD_SHIFT (0U)
+#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
+
+/*! @name CnSC - Channel (n) Status and Control */
+#define TPM_CnSC_DMA_MASK (0x1U)
+#define TPM_CnSC_DMA_SHIFT (0U)
+#define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
+#define TPM_CnSC_ELSA_MASK (0x4U)
+#define TPM_CnSC_ELSA_SHIFT (2U)
+#define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
+#define TPM_CnSC_ELSB_MASK (0x8U)
+#define TPM_CnSC_ELSB_SHIFT (3U)
+#define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
+#define TPM_CnSC_MSA_MASK (0x10U)
+#define TPM_CnSC_MSA_SHIFT (4U)
+#define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
+#define TPM_CnSC_MSB_MASK (0x20U)
+#define TPM_CnSC_MSB_SHIFT (5U)
+#define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
+#define TPM_CnSC_CHIE_MASK (0x40U)
+#define TPM_CnSC_CHIE_SHIFT (6U)
+#define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
+#define TPM_CnSC_CHF_MASK (0x80U)
+#define TPM_CnSC_CHF_SHIFT (7U)
+#define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
+
+/* The count of TPM_CnSC */
+#define TPM_CnSC_COUNT (6U)
+
+/*! @name CnV - Channel (n) Value */
+#define TPM_CnV_VAL_MASK (0xFFFFU)
+#define TPM_CnV_VAL_SHIFT (0U)
+#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
+
+/* The count of TPM_CnV */
+#define TPM_CnV_COUNT (6U)
+
+/*! @name STATUS - Capture and Compare Status */
+#define TPM_STATUS_CH0F_MASK (0x1U)
+#define TPM_STATUS_CH0F_SHIFT (0U)
+#define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
+#define TPM_STATUS_CH1F_MASK (0x2U)
+#define TPM_STATUS_CH1F_SHIFT (1U)
+#define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
+#define TPM_STATUS_CH2F_MASK (0x4U)
+#define TPM_STATUS_CH2F_SHIFT (2U)
+#define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
+#define TPM_STATUS_CH3F_MASK (0x8U)
+#define TPM_STATUS_CH3F_SHIFT (3U)
+#define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
+#define TPM_STATUS_CH4F_MASK (0x10U)
+#define TPM_STATUS_CH4F_SHIFT (4U)
+#define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK)
+#define TPM_STATUS_CH5F_MASK (0x20U)
+#define TPM_STATUS_CH5F_SHIFT (5U)
+#define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK)
+#define TPM_STATUS_TOF_MASK (0x100U)
+#define TPM_STATUS_TOF_SHIFT (8U)
+#define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
+
+/*! @name CONF - Configuration */
+#define TPM_CONF_DOZEEN_MASK (0x20U)
+#define TPM_CONF_DOZEEN_SHIFT (5U)
+#define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
+#define TPM_CONF_DBGMODE_MASK (0xC0U)
+#define TPM_CONF_DBGMODE_SHIFT (6U)
+#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBEEN_MASK (0x200U)
+#define TPM_CONF_GTBEEN_SHIFT (9U)
+#define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
+#define TPM_CONF_CSOT_MASK (0x10000U)
+#define TPM_CONF_CSOT_SHIFT (16U)
+#define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
+#define TPM_CONF_CSOO_MASK (0x20000U)
+#define TPM_CONF_CSOO_SHIFT (17U)
+#define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
+#define TPM_CONF_CROT_MASK (0x40000U)
+#define TPM_CONF_CROT_SHIFT (18U)
+#define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
+#define TPM_CONF_TRGSEL_MASK (0xF000000U)
+#define TPM_CONF_TRGSEL_SHIFT (24U)
+#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM0 base address */
+#define TPM0_BASE (0x40038000u)
+/** Peripheral TPM0 base pointer */
+#define TPM0 ((TPM_Type *)TPM0_BASE)
+/** Peripheral TPM1 base address */
+#define TPM1_BASE (0x40039000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1 ((TPM_Type *)TPM1_BASE)
+/** Peripheral TPM2 base address */
+#define TPM2_BASE (0x4003A000u)
+/** Peripheral TPM2 base pointer */
+#define TPM2 ((TPM_Type *)TPM2_BASE)
+/** Array initializer of TPM peripheral base addresses */
+#define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE }
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASE_PTRS { TPM0, TPM1, TPM2 }
+/** Interrupt vectors for the TPM peripheral type */
+#define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TSI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
+ __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
+ __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TSI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/*! @name GENCS - TSI General Control and Status Register */
+#define TSI_GENCS_CURSW_MASK (0x2U)
+#define TSI_GENCS_CURSW_SHIFT (1U)
+#define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
+#define TSI_GENCS_EOSF_MASK (0x4U)
+#define TSI_GENCS_EOSF_SHIFT (2U)
+#define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
+#define TSI_GENCS_SCNIP_MASK (0x8U)
+#define TSI_GENCS_SCNIP_SHIFT (3U)
+#define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
+#define TSI_GENCS_STM_MASK (0x10U)
+#define TSI_GENCS_STM_SHIFT (4U)
+#define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
+#define TSI_GENCS_STPE_MASK (0x20U)
+#define TSI_GENCS_STPE_SHIFT (5U)
+#define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
+#define TSI_GENCS_TSIIEN_MASK (0x40U)
+#define TSI_GENCS_TSIIEN_SHIFT (6U)
+#define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
+#define TSI_GENCS_TSIEN_MASK (0x80U)
+#define TSI_GENCS_TSIEN_SHIFT (7U)
+#define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
+#define TSI_GENCS_NSCN_MASK (0x1F00U)
+#define TSI_GENCS_NSCN_SHIFT (8U)
+#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_PS_MASK (0xE000U)
+#define TSI_GENCS_PS_SHIFT (13U)
+#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
+#define TSI_GENCS_EXTCHRG_MASK (0x70000U)
+#define TSI_GENCS_EXTCHRG_SHIFT (16U)
+#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
+#define TSI_GENCS_DVOLT_MASK (0x180000U)
+#define TSI_GENCS_DVOLT_SHIFT (19U)
+#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
+#define TSI_GENCS_REFCHRG_MASK (0xE00000U)
+#define TSI_GENCS_REFCHRG_SHIFT (21U)
+#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
+#define TSI_GENCS_MODE_MASK (0xF000000U)
+#define TSI_GENCS_MODE_SHIFT (24U)
+#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
+#define TSI_GENCS_ESOR_MASK (0x10000000U)
+#define TSI_GENCS_ESOR_SHIFT (28U)
+#define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
+#define TSI_GENCS_OUTRGF_MASK (0x80000000U)
+#define TSI_GENCS_OUTRGF_SHIFT (31U)
+#define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
+
+/*! @name DATA - TSI DATA Register */
+#define TSI_DATA_TSICNT_MASK (0xFFFFU)
+#define TSI_DATA_TSICNT_SHIFT (0U)
+#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
+#define TSI_DATA_SWTS_MASK (0x400000U)
+#define TSI_DATA_SWTS_SHIFT (22U)
+#define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
+#define TSI_DATA_DMAEN_MASK (0x800000U)
+#define TSI_DATA_DMAEN_SHIFT (23U)
+#define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
+#define TSI_DATA_TSICH_MASK (0xF0000000U)
+#define TSI_DATA_TSICH_SHIFT (28U)
+#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
+
+/*! @name TSHD - TSI Threshold Register */
+#define TSI_TSHD_THRESL_MASK (0xFFFFU)
+#define TSI_TSHD_THRESL_SHIFT (0U)
+#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
+#define TSI_TSHD_THRESH_MASK (0xFFFF0000U)
+#define TSI_TSHD_THRESH_SHIFT (16U)
+#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0 ((TSI_Type *)TSI0_BASE)
+/** Array initializer of TSI peripheral base addresses */
+#define TSI_BASE_ADDRS { TSI0_BASE }
+/** Array initializer of TSI peripheral base pointers */
+#define TSI_BASE_PTRS { TSI0 }
+/** Interrupt vectors for the TSI peripheral type */
+#define TSI_IRQS { TSI0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/*! @name BDH - UART Baud Rate Register: High */
+#define UART_BDH_SBR_MASK (0x1FU)
+#define UART_BDH_SBR_SHIFT (0U)
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK (0x20U)
+#define UART_BDH_SBNS_SHIFT (5U)
+#define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK)
+#define UART_BDH_RXEDGIE_MASK (0x40U)
+#define UART_BDH_RXEDGIE_SHIFT (6U)
+#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
+#define UART_BDH_LBKDIE_MASK (0x80U)
+#define UART_BDH_LBKDIE_SHIFT (7U)
+#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
+
+/*! @name BDL - UART Baud Rate Register: Low */
+#define UART_BDL_SBR_MASK (0xFFU)
+#define UART_BDL_SBR_SHIFT (0U)
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
+
+/*! @name C1 - UART Control Register 1 */
+#define UART_C1_PT_MASK (0x1U)
+#define UART_C1_PT_SHIFT (0U)
+#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
+#define UART_C1_PE_MASK (0x2U)
+#define UART_C1_PE_SHIFT (1U)
+#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
+#define UART_C1_ILT_MASK (0x4U)
+#define UART_C1_ILT_SHIFT (2U)
+#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
+#define UART_C1_WAKE_MASK (0x8U)
+#define UART_C1_WAKE_SHIFT (3U)
+#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
+#define UART_C1_M_MASK (0x10U)
+#define UART_C1_M_SHIFT (4U)
+#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
+#define UART_C1_RSRC_MASK (0x20U)
+#define UART_C1_RSRC_SHIFT (5U)
+#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
+#define UART_C1_UARTSWAI_MASK (0x40U)
+#define UART_C1_UARTSWAI_SHIFT (6U)
+#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
+#define UART_C1_LOOPS_MASK (0x80U)
+#define UART_C1_LOOPS_SHIFT (7U)
+#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
+
+/*! @name C2 - UART Control Register 2 */
+#define UART_C2_SBK_MASK (0x1U)
+#define UART_C2_SBK_SHIFT (0U)
+#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
+#define UART_C2_RWU_MASK (0x2U)
+#define UART_C2_RWU_SHIFT (1U)
+#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
+#define UART_C2_RE_MASK (0x4U)
+#define UART_C2_RE_SHIFT (2U)
+#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
+#define UART_C2_TE_MASK (0x8U)
+#define UART_C2_TE_SHIFT (3U)
+#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
+#define UART_C2_ILIE_MASK (0x10U)
+#define UART_C2_ILIE_SHIFT (4U)
+#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
+#define UART_C2_RIE_MASK (0x20U)
+#define UART_C2_RIE_SHIFT (5U)
+#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
+#define UART_C2_TCIE_MASK (0x40U)
+#define UART_C2_TCIE_SHIFT (6U)
+#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
+#define UART_C2_TIE_MASK (0x80U)
+#define UART_C2_TIE_SHIFT (7U)
+#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
+
+/*! @name S1 - UART Status Register 1 */
+#define UART_S1_PF_MASK (0x1U)
+#define UART_S1_PF_SHIFT (0U)
+#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
+#define UART_S1_FE_MASK (0x2U)
+#define UART_S1_FE_SHIFT (1U)
+#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
+#define UART_S1_NF_MASK (0x4U)
+#define UART_S1_NF_SHIFT (2U)
+#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
+#define UART_S1_OR_MASK (0x8U)
+#define UART_S1_OR_SHIFT (3U)
+#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
+#define UART_S1_IDLE_MASK (0x10U)
+#define UART_S1_IDLE_SHIFT (4U)
+#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
+#define UART_S1_RDRF_MASK (0x20U)
+#define UART_S1_RDRF_SHIFT (5U)
+#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
+#define UART_S1_TC_MASK (0x40U)
+#define UART_S1_TC_SHIFT (6U)
+#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
+#define UART_S1_TDRE_MASK (0x80U)
+#define UART_S1_TDRE_SHIFT (7U)
+#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
+
+/*! @name S2 - UART Status Register 2 */
+#define UART_S2_RAF_MASK (0x1U)
+#define UART_S2_RAF_SHIFT (0U)
+#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
+#define UART_S2_LBKDE_MASK (0x2U)
+#define UART_S2_LBKDE_SHIFT (1U)
+#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
+#define UART_S2_BRK13_MASK (0x4U)
+#define UART_S2_BRK13_SHIFT (2U)
+#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
+#define UART_S2_RWUID_MASK (0x8U)
+#define UART_S2_RWUID_SHIFT (3U)
+#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
+#define UART_S2_RXINV_MASK (0x10U)
+#define UART_S2_RXINV_SHIFT (4U)
+#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
+#define UART_S2_RXEDGIF_MASK (0x40U)
+#define UART_S2_RXEDGIF_SHIFT (6U)
+#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
+#define UART_S2_LBKDIF_MASK (0x80U)
+#define UART_S2_LBKDIF_SHIFT (7U)
+#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
+
+/*! @name C3 - UART Control Register 3 */
+#define UART_C3_PEIE_MASK (0x1U)
+#define UART_C3_PEIE_SHIFT (0U)
+#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
+#define UART_C3_FEIE_MASK (0x2U)
+#define UART_C3_FEIE_SHIFT (1U)
+#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
+#define UART_C3_NEIE_MASK (0x4U)
+#define UART_C3_NEIE_SHIFT (2U)
+#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
+#define UART_C3_ORIE_MASK (0x8U)
+#define UART_C3_ORIE_SHIFT (3U)
+#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
+#define UART_C3_TXINV_MASK (0x10U)
+#define UART_C3_TXINV_SHIFT (4U)
+#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
+#define UART_C3_TXDIR_MASK (0x20U)
+#define UART_C3_TXDIR_SHIFT (5U)
+#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
+#define UART_C3_T8_MASK (0x40U)
+#define UART_C3_T8_SHIFT (6U)
+#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
+#define UART_C3_R8_MASK (0x80U)
+#define UART_C3_R8_SHIFT (7U)
+#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
+
+/*! @name D - UART Data Register */
+#define UART_D_R0T0_MASK (0x1U)
+#define UART_D_R0T0_SHIFT (0U)
+#define UART_D_R0T0(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R0T0_SHIFT)) & UART_D_R0T0_MASK)
+#define UART_D_R1T1_MASK (0x2U)
+#define UART_D_R1T1_SHIFT (1U)
+#define UART_D_R1T1(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R1T1_SHIFT)) & UART_D_R1T1_MASK)
+#define UART_D_R2T2_MASK (0x4U)
+#define UART_D_R2T2_SHIFT (2U)
+#define UART_D_R2T2(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R2T2_SHIFT)) & UART_D_R2T2_MASK)
+#define UART_D_R3T3_MASK (0x8U)
+#define UART_D_R3T3_SHIFT (3U)
+#define UART_D_R3T3(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R3T3_SHIFT)) & UART_D_R3T3_MASK)
+#define UART_D_R4T4_MASK (0x10U)
+#define UART_D_R4T4_SHIFT (4U)
+#define UART_D_R4T4(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R4T4_SHIFT)) & UART_D_R4T4_MASK)
+#define UART_D_R5T5_MASK (0x20U)
+#define UART_D_R5T5_SHIFT (5U)
+#define UART_D_R5T5(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R5T5_SHIFT)) & UART_D_R5T5_MASK)
+#define UART_D_R6T6_MASK (0x40U)
+#define UART_D_R6T6_SHIFT (6U)
+#define UART_D_R6T6(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R6T6_SHIFT)) & UART_D_R6T6_MASK)
+#define UART_D_R7T7_MASK (0x80U)
+#define UART_D_R7T7_SHIFT (7U)
+#define UART_D_R7T7(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R7T7_SHIFT)) & UART_D_R7T7_MASK)
+
+/*! @name C4 - UART Control Register 4 */
+#define UART_C4_RDMAS_MASK (0x20U)
+#define UART_C4_RDMAS_SHIFT (5U)
+#define UART_C4_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_RDMAS_SHIFT)) & UART_C4_RDMAS_MASK)
+#define UART_C4_TDMAS_MASK (0x80U)
+#define UART_C4_TDMAS_SHIFT (7U)
+#define UART_C4_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_TDMAS_SHIFT)) & UART_C4_TDMAS_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS { 0u, UART1_BASE, UART2_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS { (UART_Type *)0u, UART1, UART2 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn }
+#define UART_ERR_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART0 Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
+ * @{
+ */
+
+/** UART0 - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+} UART0_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART0 Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART0_Register_Masks UART0 Register Masks
+ * @{
+ */
+
+/*! @name BDH - UART Baud Rate Register High */
+#define UART0_BDH_SBR_MASK (0x1FU)
+#define UART0_BDH_SBR_SHIFT (0U)
+#define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_SBR_SHIFT)) & UART0_BDH_SBR_MASK)
+#define UART0_BDH_SBNS_MASK (0x20U)
+#define UART0_BDH_SBNS_SHIFT (5U)
+#define UART0_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_SBNS_SHIFT)) & UART0_BDH_SBNS_MASK)
+#define UART0_BDH_RXEDGIE_MASK (0x40U)
+#define UART0_BDH_RXEDGIE_SHIFT (6U)
+#define UART0_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_RXEDGIE_SHIFT)) & UART0_BDH_RXEDGIE_MASK)
+#define UART0_BDH_LBKDIE_MASK (0x80U)
+#define UART0_BDH_LBKDIE_SHIFT (7U)
+#define UART0_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_LBKDIE_SHIFT)) & UART0_BDH_LBKDIE_MASK)
+
+/*! @name BDL - UART Baud Rate Register Low */
+#define UART0_BDL_SBR_MASK (0xFFU)
+#define UART0_BDL_SBR_SHIFT (0U)
+#define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDL_SBR_SHIFT)) & UART0_BDL_SBR_MASK)
+
+/*! @name C1 - UART Control Register 1 */
+#define UART0_C1_PT_MASK (0x1U)
+#define UART0_C1_PT_SHIFT (0U)
+#define UART0_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_PT_SHIFT)) & UART0_C1_PT_MASK)
+#define UART0_C1_PE_MASK (0x2U)
+#define UART0_C1_PE_SHIFT (1U)
+#define UART0_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_PE_SHIFT)) & UART0_C1_PE_MASK)
+#define UART0_C1_ILT_MASK (0x4U)
+#define UART0_C1_ILT_SHIFT (2U)
+#define UART0_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_ILT_SHIFT)) & UART0_C1_ILT_MASK)
+#define UART0_C1_WAKE_MASK (0x8U)
+#define UART0_C1_WAKE_SHIFT (3U)
+#define UART0_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_WAKE_SHIFT)) & UART0_C1_WAKE_MASK)
+#define UART0_C1_M_MASK (0x10U)
+#define UART0_C1_M_SHIFT (4U)
+#define UART0_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_M_SHIFT)) & UART0_C1_M_MASK)
+#define UART0_C1_RSRC_MASK (0x20U)
+#define UART0_C1_RSRC_SHIFT (5U)
+#define UART0_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_RSRC_SHIFT)) & UART0_C1_RSRC_MASK)
+#define UART0_C1_DOZEEN_MASK (0x40U)
+#define UART0_C1_DOZEEN_SHIFT (6U)
+#define UART0_C1_DOZEEN(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_DOZEEN_SHIFT)) & UART0_C1_DOZEEN_MASK)
+#define UART0_C1_LOOPS_MASK (0x80U)
+#define UART0_C1_LOOPS_SHIFT (7U)
+#define UART0_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_LOOPS_SHIFT)) & UART0_C1_LOOPS_MASK)
+
+/*! @name C2 - UART Control Register 2 */
+#define UART0_C2_SBK_MASK (0x1U)
+#define UART0_C2_SBK_SHIFT (0U)
+#define UART0_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_SBK_SHIFT)) & UART0_C2_SBK_MASK)
+#define UART0_C2_RWU_MASK (0x2U)
+#define UART0_C2_RWU_SHIFT (1U)
+#define UART0_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RWU_SHIFT)) & UART0_C2_RWU_MASK)
+#define UART0_C2_RE_MASK (0x4U)
+#define UART0_C2_RE_SHIFT (2U)
+#define UART0_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RE_SHIFT)) & UART0_C2_RE_MASK)
+#define UART0_C2_TE_MASK (0x8U)
+#define UART0_C2_TE_SHIFT (3U)
+#define UART0_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TE_SHIFT)) & UART0_C2_TE_MASK)
+#define UART0_C2_ILIE_MASK (0x10U)
+#define UART0_C2_ILIE_SHIFT (4U)
+#define UART0_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_ILIE_SHIFT)) & UART0_C2_ILIE_MASK)
+#define UART0_C2_RIE_MASK (0x20U)
+#define UART0_C2_RIE_SHIFT (5U)
+#define UART0_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RIE_SHIFT)) & UART0_C2_RIE_MASK)
+#define UART0_C2_TCIE_MASK (0x40U)
+#define UART0_C2_TCIE_SHIFT (6U)
+#define UART0_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TCIE_SHIFT)) & UART0_C2_TCIE_MASK)
+#define UART0_C2_TIE_MASK (0x80U)
+#define UART0_C2_TIE_SHIFT (7U)
+#define UART0_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TIE_SHIFT)) & UART0_C2_TIE_MASK)
+
+/*! @name S1 - UART Status Register 1 */
+#define UART0_S1_PF_MASK (0x1U)
+#define UART0_S1_PF_SHIFT (0U)
+#define UART0_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_PF_SHIFT)) & UART0_S1_PF_MASK)
+#define UART0_S1_FE_MASK (0x2U)
+#define UART0_S1_FE_SHIFT (1U)
+#define UART0_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_FE_SHIFT)) & UART0_S1_FE_MASK)
+#define UART0_S1_NF_MASK (0x4U)
+#define UART0_S1_NF_SHIFT (2U)
+#define UART0_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_NF_SHIFT)) & UART0_S1_NF_MASK)
+#define UART0_S1_OR_MASK (0x8U)
+#define UART0_S1_OR_SHIFT (3U)
+#define UART0_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_OR_SHIFT)) & UART0_S1_OR_MASK)
+#define UART0_S1_IDLE_MASK (0x10U)
+#define UART0_S1_IDLE_SHIFT (4U)
+#define UART0_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_IDLE_SHIFT)) & UART0_S1_IDLE_MASK)
+#define UART0_S1_RDRF_MASK (0x20U)
+#define UART0_S1_RDRF_SHIFT (5U)
+#define UART0_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_RDRF_SHIFT)) & UART0_S1_RDRF_MASK)
+#define UART0_S1_TC_MASK (0x40U)
+#define UART0_S1_TC_SHIFT (6U)
+#define UART0_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_TC_SHIFT)) & UART0_S1_TC_MASK)
+#define UART0_S1_TDRE_MASK (0x80U)
+#define UART0_S1_TDRE_SHIFT (7U)
+#define UART0_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_TDRE_SHIFT)) & UART0_S1_TDRE_MASK)
+
+/*! @name S2 - UART Status Register 2 */
+#define UART0_S2_RAF_MASK (0x1U)
+#define UART0_S2_RAF_SHIFT (0U)
+#define UART0_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RAF_SHIFT)) & UART0_S2_RAF_MASK)
+#define UART0_S2_LBKDE_MASK (0x2U)
+#define UART0_S2_LBKDE_SHIFT (1U)
+#define UART0_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_LBKDE_SHIFT)) & UART0_S2_LBKDE_MASK)
+#define UART0_S2_BRK13_MASK (0x4U)
+#define UART0_S2_BRK13_SHIFT (2U)
+#define UART0_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_BRK13_SHIFT)) & UART0_S2_BRK13_MASK)
+#define UART0_S2_RWUID_MASK (0x8U)
+#define UART0_S2_RWUID_SHIFT (3U)
+#define UART0_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RWUID_SHIFT)) & UART0_S2_RWUID_MASK)
+#define UART0_S2_RXINV_MASK (0x10U)
+#define UART0_S2_RXINV_SHIFT (4U)
+#define UART0_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RXINV_SHIFT)) & UART0_S2_RXINV_MASK)
+#define UART0_S2_MSBF_MASK (0x20U)
+#define UART0_S2_MSBF_SHIFT (5U)
+#define UART0_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_MSBF_SHIFT)) & UART0_S2_MSBF_MASK)
+#define UART0_S2_RXEDGIF_MASK (0x40U)
+#define UART0_S2_RXEDGIF_SHIFT (6U)
+#define UART0_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RXEDGIF_SHIFT)) & UART0_S2_RXEDGIF_MASK)
+#define UART0_S2_LBKDIF_MASK (0x80U)
+#define UART0_S2_LBKDIF_SHIFT (7U)
+#define UART0_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_LBKDIF_SHIFT)) & UART0_S2_LBKDIF_MASK)
+
+/*! @name C3 - UART Control Register 3 */
+#define UART0_C3_PEIE_MASK (0x1U)
+#define UART0_C3_PEIE_SHIFT (0U)
+#define UART0_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_PEIE_SHIFT)) & UART0_C3_PEIE_MASK)
+#define UART0_C3_FEIE_MASK (0x2U)
+#define UART0_C3_FEIE_SHIFT (1U)
+#define UART0_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_FEIE_SHIFT)) & UART0_C3_FEIE_MASK)
+#define UART0_C3_NEIE_MASK (0x4U)
+#define UART0_C3_NEIE_SHIFT (2U)
+#define UART0_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_NEIE_SHIFT)) & UART0_C3_NEIE_MASK)
+#define UART0_C3_ORIE_MASK (0x8U)
+#define UART0_C3_ORIE_SHIFT (3U)
+#define UART0_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_ORIE_SHIFT)) & UART0_C3_ORIE_MASK)
+#define UART0_C3_TXINV_MASK (0x10U)
+#define UART0_C3_TXINV_SHIFT (4U)
+#define UART0_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_TXINV_SHIFT)) & UART0_C3_TXINV_MASK)
+#define UART0_C3_TXDIR_MASK (0x20U)
+#define UART0_C3_TXDIR_SHIFT (5U)
+#define UART0_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_TXDIR_SHIFT)) & UART0_C3_TXDIR_MASK)
+#define UART0_C3_R9T8_MASK (0x40U)
+#define UART0_C3_R9T8_SHIFT (6U)
+#define UART0_C3_R9T8(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_R9T8_SHIFT)) & UART0_C3_R9T8_MASK)
+#define UART0_C3_R8T9_MASK (0x80U)
+#define UART0_C3_R8T9_SHIFT (7U)
+#define UART0_C3_R8T9(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_R8T9_SHIFT)) & UART0_C3_R8T9_MASK)
+
+/*! @name D - UART Data Register */
+#define UART0_D_R0T0_MASK (0x1U)
+#define UART0_D_R0T0_SHIFT (0U)
+#define UART0_D_R0T0(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R0T0_SHIFT)) & UART0_D_R0T0_MASK)
+#define UART0_D_R1T1_MASK (0x2U)
+#define UART0_D_R1T1_SHIFT (1U)
+#define UART0_D_R1T1(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R1T1_SHIFT)) & UART0_D_R1T1_MASK)
+#define UART0_D_R2T2_MASK (0x4U)
+#define UART0_D_R2T2_SHIFT (2U)
+#define UART0_D_R2T2(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R2T2_SHIFT)) & UART0_D_R2T2_MASK)
+#define UART0_D_R3T3_MASK (0x8U)
+#define UART0_D_R3T3_SHIFT (3U)
+#define UART0_D_R3T3(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R3T3_SHIFT)) & UART0_D_R3T3_MASK)
+#define UART0_D_R4T4_MASK (0x10U)
+#define UART0_D_R4T4_SHIFT (4U)
+#define UART0_D_R4T4(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R4T4_SHIFT)) & UART0_D_R4T4_MASK)
+#define UART0_D_R5T5_MASK (0x20U)
+#define UART0_D_R5T5_SHIFT (5U)
+#define UART0_D_R5T5(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R5T5_SHIFT)) & UART0_D_R5T5_MASK)
+#define UART0_D_R6T6_MASK (0x40U)
+#define UART0_D_R6T6_SHIFT (6U)
+#define UART0_D_R6T6(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R6T6_SHIFT)) & UART0_D_R6T6_MASK)
+#define UART0_D_R7T7_MASK (0x80U)
+#define UART0_D_R7T7_SHIFT (7U)
+#define UART0_D_R7T7(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R7T7_SHIFT)) & UART0_D_R7T7_MASK)
+
+/*! @name MA1 - UART Match Address Registers 1 */
+#define UART0_MA1_MA_MASK (0xFFU)
+#define UART0_MA1_MA_SHIFT (0U)
+#define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART0_MA1_MA_SHIFT)) & UART0_MA1_MA_MASK)
+
+/*! @name MA2 - UART Match Address Registers 2 */
+#define UART0_MA2_MA_MASK (0xFFU)
+#define UART0_MA2_MA_SHIFT (0U)
+#define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART0_MA2_MA_SHIFT)) & UART0_MA2_MA_MASK)
+
+/*! @name C4 - UART Control Register 4 */
+#define UART0_C4_OSR_MASK (0x1FU)
+#define UART0_C4_OSR_SHIFT (0U)
+#define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_OSR_SHIFT)) & UART0_C4_OSR_MASK)
+#define UART0_C4_M10_MASK (0x20U)
+#define UART0_C4_M10_SHIFT (5U)
+#define UART0_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_M10_SHIFT)) & UART0_C4_M10_MASK)
+#define UART0_C4_MAEN2_MASK (0x40U)
+#define UART0_C4_MAEN2_SHIFT (6U)
+#define UART0_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_MAEN2_SHIFT)) & UART0_C4_MAEN2_MASK)
+#define UART0_C4_MAEN1_MASK (0x80U)
+#define UART0_C4_MAEN1_SHIFT (7U)
+#define UART0_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_MAEN1_SHIFT)) & UART0_C4_MAEN1_MASK)
+
+/*! @name C5 - UART Control Register 5 */
+#define UART0_C5_RESYNCDIS_MASK (0x1U)
+#define UART0_C5_RESYNCDIS_SHIFT (0U)
+#define UART0_C5_RESYNCDIS(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_RESYNCDIS_SHIFT)) & UART0_C5_RESYNCDIS_MASK)
+#define UART0_C5_BOTHEDGE_MASK (0x2U)
+#define UART0_C5_BOTHEDGE_SHIFT (1U)
+#define UART0_C5_BOTHEDGE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_BOTHEDGE_SHIFT)) & UART0_C5_BOTHEDGE_MASK)
+#define UART0_C5_RDMAE_MASK (0x20U)
+#define UART0_C5_RDMAE_SHIFT (5U)
+#define UART0_C5_RDMAE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_RDMAE_SHIFT)) & UART0_C5_RDMAE_MASK)
+#define UART0_C5_TDMAE_MASK (0x80U)
+#define UART0_C5_TDMAE_SHIFT (7U)
+#define UART0_C5_TDMAE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_TDMAE_SHIFT)) & UART0_C5_TDMAE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group UART0_Register_Masks */
+
+
+/* UART0 - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UART0_Type *)UART0_BASE)
+/** Array initializer of UART0 peripheral base addresses */
+#define UART0_BASE_ADDRS { UART0_BASE }
+/** Array initializer of UART0 peripheral base pointers */
+#define UART0_BASE_PTRS { UART0 }
+/** Interrupt vectors for the UART0 peripheral type */
+#define UART0_RX_TX_IRQS { UART0_IRQn }
+#define UART0_ERR_IRQS { UART0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UART0_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
+ uint8_t RESERVED_3[3];
+ __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
+ uint8_t RESERVED_4[3];
+ __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
+ uint8_t RESERVED_7[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
+ uint8_t RESERVED_8[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
+ uint8_t RESERVED_11[3];
+ __I uint8_t STAT; /**< Status register, offset: 0x90 */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t CTL; /**< Control register, offset: 0x94 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
+ uint8_t RESERVED_14[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
+ uint8_t RESERVED_16[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
+ uint8_t RESERVED_17[3];
+ __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_20[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_21[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
+ uint8_t RESERVED_22[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
+ uint8_t RESERVED_23[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
+ uint8_t RESERVED_24[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
+ uint8_t RESERVED_25[7];
+ __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/*! @name PERID - Peripheral ID register */
+#define USB_PERID_ID_MASK (0x3FU)
+#define USB_PERID_ID_SHIFT (0U)
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
+
+/*! @name IDCOMP - Peripheral ID Complement register */
+#define USB_IDCOMP_NID_MASK (0x3FU)
+#define USB_IDCOMP_NID_SHIFT (0U)
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
+
+/*! @name REV - Peripheral Revision register */
+#define USB_REV_REV_MASK (0xFFU)
+#define USB_REV_REV_SHIFT (0U)
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
+
+/*! @name ADDINFO - Peripheral Additional Info register */
+#define USB_ADDINFO_IEHOST_MASK (0x1U)
+#define USB_ADDINFO_IEHOST_SHIFT (0U)
+#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
+#define USB_ADDINFO_IRQNUM_MASK (0xF8U)
+#define USB_ADDINFO_IRQNUM_SHIFT (3U)
+#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK)
+
+/*! @name OTGISTAT - OTG Interrupt Status register */
+#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
+#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
+#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
+#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
+#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
+#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
+#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
+#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
+#define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
+#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
+#define USB_OTGISTAT_IDCHG_MASK (0x80U)
+#define USB_OTGISTAT_IDCHG_SHIFT (7U)
+#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
+
+/*! @name OTGICR - OTG Interrupt Control register */
+#define USB_OTGICR_AVBUSEN_MASK (0x1U)
+#define USB_OTGICR_AVBUSEN_SHIFT (0U)
+#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
+#define USB_OTGICR_BSESSEN_MASK (0x4U)
+#define USB_OTGICR_BSESSEN_SHIFT (2U)
+#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
+#define USB_OTGICR_SESSVLDEN_MASK (0x8U)
+#define USB_OTGICR_SESSVLDEN_SHIFT (3U)
+#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
+#define USB_OTGICR_LINESTATEEN_MASK (0x20U)
+#define USB_OTGICR_LINESTATEEN_SHIFT (5U)
+#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
+#define USB_OTGICR_ONEMSECEN_MASK (0x40U)
+#define USB_OTGICR_ONEMSECEN_SHIFT (6U)
+#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
+#define USB_OTGICR_IDEN_MASK (0x80U)
+#define USB_OTGICR_IDEN_SHIFT (7U)
+#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
+
+/*! @name OTGSTAT - OTG Status register */
+#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
+#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
+#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
+#define USB_OTGSTAT_BSESSEND_MASK (0x4U)
+#define USB_OTGSTAT_BSESSEND_SHIFT (2U)
+#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
+#define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
+#define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
+#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
+#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
+#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
+#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
+#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
+#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
+#define USB_OTGSTAT_ID_MASK (0x80U)
+#define USB_OTGSTAT_ID_SHIFT (7U)
+#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
+
+/*! @name OTGCTL - OTG Control register */
+#define USB_OTGCTL_OTGEN_MASK (0x4U)
+#define USB_OTGCTL_OTGEN_SHIFT (2U)
+#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
+#define USB_OTGCTL_DMLOW_MASK (0x10U)
+#define USB_OTGCTL_DMLOW_SHIFT (4U)
+#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
+#define USB_OTGCTL_DPLOW_MASK (0x20U)
+#define USB_OTGCTL_DPLOW_SHIFT (5U)
+#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
+#define USB_OTGCTL_DPHIGH_MASK (0x80U)
+#define USB_OTGCTL_DPHIGH_SHIFT (7U)
+#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
+
+/*! @name ISTAT - Interrupt Status register */
+#define USB_ISTAT_USBRST_MASK (0x1U)
+#define USB_ISTAT_USBRST_SHIFT (0U)
+#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK (0x2U)
+#define USB_ISTAT_ERROR_SHIFT (1U)
+#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK (0x4U)
+#define USB_ISTAT_SOFTOK_SHIFT (2U)
+#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK (0x8U)
+#define USB_ISTAT_TOKDNE_SHIFT (3U)
+#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK (0x10U)
+#define USB_ISTAT_SLEEP_SHIFT (4U)
+#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK (0x20U)
+#define USB_ISTAT_RESUME_SHIFT (5U)
+#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_ATTACH_MASK (0x40U)
+#define USB_ISTAT_ATTACH_SHIFT (6U)
+#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
+#define USB_ISTAT_STALL_MASK (0x80U)
+#define USB_ISTAT_STALL_SHIFT (7U)
+#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
+
+/*! @name INTEN - Interrupt Enable register */
+#define USB_INTEN_USBRSTEN_MASK (0x1U)
+#define USB_INTEN_USBRSTEN_SHIFT (0U)
+#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK (0x2U)
+#define USB_INTEN_ERROREN_SHIFT (1U)
+#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK (0x4U)
+#define USB_INTEN_SOFTOKEN_SHIFT (2U)
+#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK (0x8U)
+#define USB_INTEN_TOKDNEEN_SHIFT (3U)
+#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK (0x10U)
+#define USB_INTEN_SLEEPEN_SHIFT (4U)
+#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK (0x20U)
+#define USB_INTEN_RESUMEEN_SHIFT (5U)
+#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_ATTACHEN_MASK (0x40U)
+#define USB_INTEN_ATTACHEN_SHIFT (6U)
+#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
+#define USB_INTEN_STALLEN_MASK (0x80U)
+#define USB_INTEN_STALLEN_SHIFT (7U)
+#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
+
+/*! @name ERRSTAT - Error Interrupt Status register */
+#define USB_ERRSTAT_PIDERR_MASK (0x1U)
+#define USB_ERRSTAT_PIDERR_SHIFT (0U)
+#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
+#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
+#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK (0x4U)
+#define USB_ERRSTAT_CRC16_SHIFT (2U)
+#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK (0x8U)
+#define USB_ERRSTAT_DFN8_SHIFT (3U)
+#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK (0x10U)
+#define USB_ERRSTAT_BTOERR_SHIFT (4U)
+#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK (0x20U)
+#define USB_ERRSTAT_DMAERR_SHIFT (5U)
+#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK (0x80U)
+#define USB_ERRSTAT_BTSERR_SHIFT (7U)
+#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
+
+/*! @name ERREN - Error Interrupt Enable register */
+#define USB_ERREN_PIDERREN_MASK (0x1U)
+#define USB_ERREN_PIDERREN_SHIFT (0U)
+#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
+#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
+#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK (0x4U)
+#define USB_ERREN_CRC16EN_SHIFT (2U)
+#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK (0x8U)
+#define USB_ERREN_DFN8EN_SHIFT (3U)
+#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK (0x10U)
+#define USB_ERREN_BTOERREN_SHIFT (4U)
+#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK (0x20U)
+#define USB_ERREN_DMAERREN_SHIFT (5U)
+#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK (0x80U)
+#define USB_ERREN_BTSERREN_SHIFT (7U)
+#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
+
+/*! @name STAT - Status register */
+#define USB_STAT_ODD_MASK (0x4U)
+#define USB_STAT_ODD_SHIFT (2U)
+#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK (0x8U)
+#define USB_STAT_TX_SHIFT (3U)
+#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK (0xF0U)
+#define USB_STAT_ENDP_SHIFT (4U)
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
+
+/*! @name CTL - Control register */
+#define USB_CTL_USBENSOFEN_MASK (0x1U)
+#define USB_CTL_USBENSOFEN_SHIFT (0U)
+#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK (0x2U)
+#define USB_CTL_ODDRST_SHIFT (1U)
+#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK (0x4U)
+#define USB_CTL_RESUME_SHIFT (2U)
+#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK (0x8U)
+#define USB_CTL_HOSTMODEEN_SHIFT (3U)
+#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_RESET_MASK (0x10U)
+#define USB_CTL_RESET_SHIFT (4U)
+#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
+#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK (0x40U)
+#define USB_CTL_SE0_SHIFT (6U)
+#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK (0x80U)
+#define USB_CTL_JSTATE_SHIFT (7U)
+#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
+
+/*! @name ADDR - Address register */
+#define USB_ADDR_ADDR_MASK (0x7FU)
+#define USB_ADDR_ADDR_SHIFT (0U)
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK (0x80U)
+#define USB_ADDR_LSEN_SHIFT (7U)
+#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
+
+/*! @name BDTPAGE1 - BDT Page register 1 */
+#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
+#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
+
+/*! @name FRMNUML - Frame Number register Low */
+#define USB_FRMNUML_FRM_MASK (0xFFU)
+#define USB_FRMNUML_FRM_SHIFT (0U)
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
+
+/*! @name FRMNUMH - Frame Number register High */
+#define USB_FRMNUMH_FRM_MASK (0x7U)
+#define USB_FRMNUMH_FRM_SHIFT (0U)
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
+
+/*! @name TOKEN - Token register */
+#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
+#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK (0xF0U)
+#define USB_TOKEN_TOKENPID_SHIFT (4U)
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
+
+/*! @name SOFTHLD - SOF Threshold register */
+#define USB_SOFTHLD_CNT_MASK (0xFFU)
+#define USB_SOFTHLD_CNT_SHIFT (0U)
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
+
+/*! @name BDTPAGE2 - BDT Page Register 2 */
+#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
+#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
+
+/*! @name BDTPAGE3 - BDT Page Register 3 */
+#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
+#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
+
+/*! @name ENDPT - Endpoint Control register */
+#define USB_ENDPT_EPHSHK_MASK (0x1U)
+#define USB_ENDPT_EPHSHK_SHIFT (0U)
+#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK (0x2U)
+#define USB_ENDPT_EPSTALL_SHIFT (1U)
+#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK (0x4U)
+#define USB_ENDPT_EPTXEN_SHIFT (2U)
+#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK (0x8U)
+#define USB_ENDPT_EPRXEN_SHIFT (3U)
+#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
+#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
+#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
+#define USB_ENDPT_RETRYDIS_MASK (0x40U)
+#define USB_ENDPT_RETRYDIS_SHIFT (6U)
+#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
+#define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
+#define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
+#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
+
+/* The count of USB_ENDPT */
+#define USB_ENDPT_COUNT (16U)
+
+/*! @name USBCTRL - USB Control register */
+#define USB_USBCTRL_PDE_MASK (0x40U)
+#define USB_USBCTRL_PDE_SHIFT (6U)
+#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK (0x80U)
+#define USB_USBCTRL_SUSP_SHIFT (7U)
+#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
+
+/*! @name OBSERVE - USB OTG Observe register */
+#define USB_OBSERVE_DMPD_MASK (0x10U)
+#define USB_OBSERVE_DMPD_SHIFT (4U)
+#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK (0x40U)
+#define USB_OBSERVE_DPPD_SHIFT (6U)
+#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK (0x80U)
+#define USB_OBSERVE_DPPU_SHIFT (7U)
+#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
+
+/*! @name CONTROL - USB OTG Control register */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
+#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
+
+/*! @name USBTRC0 - USB Transceiver Control register 0 */
+#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
+#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
+#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
+#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
+#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
+#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK (0x80U)
+#define USB_USBTRC0_USBRESET_SHIFT (7U)
+#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
+
+/*! @name USBFRMADJUST - Frame Adjust Register */
+#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
+#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS { USB0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+ #else
+ #pragma pop
+ #endif
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header
+ #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDK Compatibility
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+#define FPTA_BASE FGPIOA_BASE
+#define FPTA FGPIOA
+#define FPTB_BASE FGPIOB_BASE
+#define FPTB FGPIOB
+#define FPTC_BASE FGPIOC_BASE
+#define FPTC FGPIOC
+#define FPTD_BASE FGPIOD_BASE
+#define FPTD FGPIOD
+#define FPTE_BASE FGPIOE_BASE
+#define FPTE FGPIOE
+#define PTA_BASE GPIOA_BASE
+#define PTA GPIOA
+#define PTB_BASE GPIOB_BASE
+#define PTB GPIOB
+#define PTC_BASE GPIOC_BASE
+#define PTC GPIOC
+#define PTD_BASE GPIOD_BASE
+#define PTD GPIOD
+#define PTE_BASE GPIOE_BASE
+#define PTE GPIOE
+#define I2C_FLT_STOPIE_MASK This_symbol_has_been_deprecated
+#define I2C_FLT_STOPIE_SHIFT This_symbol_has_been_deprecated
+#define I2S_RCR2_CLKMODE_MASK I2S_RCR2_MSEL_MASK
+#define I2S_RCR2_CLKMODE_SHIFT I2S_RCR2_MSEL_SHIFT
+#define I2S_RCR2_CLKMODE(x) I2S_RCR2_MSEL(x)
+#define I2S_TCR2_CLKMODE_MASK I2S_TCR2_MSEL_MASK
+#define I2S_TCR2_CLKMODE_SHIFT I2S_TCR2_MSEL_SHIFT
+#define I2S_TCR2_CLKMODE(x) I2S_TCR2_MSEL(x)
+#define MCG_S_LOLS_MASK MCG_S_LOLS0_MASK
+#define MCG_S_LOLS_SHIFT MCG_S_LOLS0_SHIFT
+#define NVIC_ISPR_SETPEND(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ISPR_SETPEND_SHIFT))&NVIC_ISPR_SETPEND_MASK)
+#define LPTimer_IRQn LPTMR0_IRQn
+#define LPTimer_IRQHandler LPTMR0_IRQHandler
+#define LLW_IRQn LLWU_IRQn
+#define LLW_IRQHandler LLWU_IRQHandler
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif /* _MKL26Z4_H_ */
+
--- /dev/null
+/*
+** ###################################################################
+** Version: rev. 1.11, 2015-05-27
+** Build: b180130
+**
+** Abstract:
+** Chip specific module features.
+**
+** The Clear BSD License
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2018 NXP
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without
+** modification, are permitted (subject to the limitations in the
+** disclaimer below) provided that the following conditions are met:
+**
+** * Redistributions of source code must retain the above copyright
+** notice, this list of conditions and the following disclaimer.
+**
+** * Redistributions in binary form must reproduce the above copyright
+** notice, this list of conditions and the following disclaimer in the
+** documentation and/or other materials provided with the distribution.
+**
+** * Neither the name of the copyright holder nor the names of its
+** contributors may be used to endorse or promote products derived from
+** this software without specific prior written permission.
+**
+** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2012-12-12)
+** Initial version.
+** - rev. 1.1 (2013-04-12)
+** SystemInit function fixed for clock configuration 1.
+** Name of the interrupt num. 31 updated to reflect proper function.
+** - rev. 1.2 (2014-01-30)
+** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum.
+** - rev. 1.3 (2014-05-27)
+** Updated to Kinetis SDK support standard.
+** MCG OSC clock select supported (MCG_C7[OSCSEL]).
+** - rev. 1.4 (2014-07-25)
+** System initialization updated:
+** - Prefix added to the system initialization parameterization constants to avoid name conflicts..
+** - VLLSx wake-up recovery added.
+** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes.
+** - rev. 1.5 (2014-08-28)
+** Update of system files - default clock configuration changed, fix of OSC initialization.
+** Update of startup files - possibility to override DefaultISR added.
+** - rev. 1.6 (2014-10-14)
+** Renamed interrupt vector LPTimer to LPTMR0
+** - rev. 1.7 (2015-01-21)
+** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
+** - rev. 1.8 (2015-02-18)
+** Renamed interrupt vector LLW to LLWU
+** - rev. 1.9 (2015-05-19)
+** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
+** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
+** Added features for PORT.
+** - rev. 1.10 (2015-05-25)
+** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
+** - rev. 1.11 (2015-05-27)
+** Several USB features added.
+**
+** ###################################################################
+*/
+
+#ifndef _MKL26Z4_FEATURES_H_
+#define _MKL26Z4_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief ADC16 availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC16_COUNT (1)
+/* @brief CMP availability on the SoC. */
+#define FSL_FEATURE_SOC_CMP_COUNT (1)
+/* @brief DAC availability on the SoC. */
+#define FSL_FEATURE_SOC_DAC_COUNT (1)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (1)
+/* @brief DMAMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+/* @brief FGPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_FGPIO_COUNT (5)
+/* @brief FTFA availability on the SoC. */
+#define FSL_FEATURE_SOC_FTFA_COUNT (1)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (5)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (2)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (1)
+/* @brief LLWU availability on the SoC. */
+#define FSL_FEATURE_SOC_LLWU_COUNT (1)
+/* @brief LPSCI availability on the SoC. */
+#define FSL_FEATURE_SOC_LPSCI_COUNT (1)
+/* @brief LPTMR availability on the SoC. */
+#define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+/* @brief MCG availability on the SoC. */
+#define FSL_FEATURE_SOC_MCG_COUNT (1)
+/* @brief MCM availability on the SoC. */
+#define FSL_FEATURE_SOC_MCM_COUNT (1)
+/* @brief MTB availability on the SoC. */
+#define FSL_FEATURE_SOC_MTB_COUNT (1)
+/* @brief MTBDWT availability on the SoC. */
+#define FSL_FEATURE_SOC_MTBDWT_COUNT (1)
+/* @brief OSC availability on the SoC. */
+#define FSL_FEATURE_SOC_OSC_COUNT (1)
+/* @brief PIT availability on the SoC. */
+#define FSL_FEATURE_SOC_PIT_COUNT (1)
+/* @brief PMC availability on the SoC. */
+#define FSL_FEATURE_SOC_PMC_COUNT (1)
+/* @brief PORT availability on the SoC. */
+#define FSL_FEATURE_SOC_PORT_COUNT (5)
+/* @brief RCM availability on the SoC. */
+#define FSL_FEATURE_SOC_RCM_COUNT (1)
+/* @brief ROM availability on the SoC. */
+#define FSL_FEATURE_SOC_ROM_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SIM availability on the SoC. */
+#define FSL_FEATURE_SOC_SIM_COUNT (1)
+/* @brief SMC availability on the SoC. */
+#define FSL_FEATURE_SOC_SMC_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (2)
+/* @brief TPM availability on the SoC. */
+#define FSL_FEATURE_SOC_TPM_COUNT (3)
+/* @brief TSI availability on the SoC. */
+#define FSL_FEATURE_SOC_TSI_COUNT (1)
+/* @brief UART availability on the SoC. */
+#define FSL_FEATURE_SOC_UART_COUNT (2)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (1)
+
+/* ADC16 module features */
+
+/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
+#define FSL_FEATURE_ADC16_HAS_PGA (0)
+/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
+/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
+/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
+#define FSL_FEATURE_ADC16_HAS_DMA (1)
+/* @brief Has differential mode (bitfield SC1x[DIFF]). */
+#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
+/* @brief Has FIFO (bit SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_HAS_FIFO (0)
+/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
+/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
+#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
+/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
+#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
+/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
+#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
+/* @brief Has HW averaging (bit SC3[AVGE]). */
+#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
+/* @brief Has offset correction (register OFS). */
+#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
+/* @brief Maximum ADC resolution. */
+#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
+/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
+#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
+
+/* CMP module features */
+
+/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
+#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
+/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
+#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
+/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
+#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
+/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
+#define FSL_FEATURE_CMP_HAS_DMA (1)
+/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
+#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1)
+/* @brief Has DAC Test function in CMP (register DACTEST). */
+#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
+
+/* COP module features */
+
+/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */
+#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (0)
+/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */
+#define FSL_FEATURE_COP_HAS_STOP_ENABLE (0)
+/* @brief Has more clock sources like MCGIRC */
+#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (0)
+/* @brief Has the timeout long and short mode bit (COPC[COPCLKSEL] and COPC[COPCLKS]) */
+#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (0)
+
+/* DAC module features */
+
+/* @brief Define the size of hardware buffer */
+#define FSL_FEATURE_DAC_BUFFER_SIZE (2)
+/* @brief Define whether the buffer supports watermark event detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (0)
+/* @brief Define whether the buffer supports watermark selection detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (0)
+/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (0)
+/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (0)
+/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (0)
+/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (0)
+/* @brief Define whether FIFO buffer mode is available or not. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
+/* @brief Define whether swing buffer mode is available or not.. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0)
+
+/* DMA module features */
+
+/* @brief Number of DMA channels. */
+#define FSL_FEATURE_DMA_MODULE_CHANNEL (4)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMA_COUNT * 4)
+
+/* DMAMUX module features */
+
+/* @brief Number of DMA channels (related to number of register CHCFGn). */
+#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4)
+/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
+#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
+
+/* FLASH module features */
+
+#if defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z128VLH4)
+ /* @brief Is of type FTFA. */
+ #define FSL_FEATURE_FLASH_IS_FTFA (1)
+ /* @brief Is of type FTFE. */
+ #define FSL_FEATURE_FLASH_IS_FTFE (0)
+ /* @brief Is of type FTFL. */
+ #define FSL_FEATURE_FLASH_IS_FTFL (0)
+ /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
+ /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+ #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
+ /* @brief Has EEPROM region protection (register FEPROT). */
+ #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
+ /* @brief Has data flash region protection (register FDPROT). */
+ #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
+ /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+ #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+ /* @brief Has flash cache control in FMC module. */
+ #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
+ /* @brief Has flash cache control in MCM module. */
+ #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
+ /* @brief Has flash cache control in MSCM module. */
+ #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
+ /* @brief Has prefetch speculation control in flash, such as kv5x. */
+ #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
+ /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
+ #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
+ /* @brief P-Flash start address. */
+ #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+ /* @brief P-Flash block count. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
+ /* @brief P-Flash block size. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072)
+ /* @brief P-Flash sector size. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
+ /* @brief P-Flash write unit size. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
+ /* @brief P-Flash data path width. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
+ /* @brief P-Flash block swap feature. */
+ #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+ /* @brief P-Flash protection region count. */
+ #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
+ /* @brief Has FlexNVM memory. */
+ #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+ /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+ /* @brief FlexNVM block count. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+ /* @brief FlexNVM block size. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+ /* @brief FlexNVM sector size. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+ /* @brief FlexNVM write unit size. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+ /* @brief FlexNVM data path width. */
+ #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+ /* @brief Has FlexRAM memory. */
+ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
+ /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+ #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
+ /* @brief FlexRAM size. */
+ #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
+ /* @brief Has 0x00 Read 1s Block command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
+ /* @brief Has 0x01 Read 1s Section command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+ /* @brief Has 0x02 Program Check command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+ /* @brief Has 0x03 Read Resource command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+ /* @brief Has 0x06 Program Longword command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
+ /* @brief Has 0x07 Program Phrase command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
+ /* @brief Has 0x08 Erase Flash Block command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
+ /* @brief Has 0x09 Erase Flash Sector command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+ /* @brief Has 0x0B Program Section command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
+ /* @brief Has 0x40 Read 1s All Blocks command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+ /* @brief Has 0x41 Read Once command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+ /* @brief Has 0x43 Program Once command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+ /* @brief Has 0x44 Erase All Blocks command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+ /* @brief Has 0x45 Verify Backdoor Access Key command. */
+ #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+ /* @brief Has 0x46 Swap Control command. */
+ #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+ /* @brief Has 0x49 Erase All Blocks Unsecure command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
+ /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+ /* @brief Has 0x4B Erase All Execute-only Segments command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+ /* @brief Has 0x80 Program Partition command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+ /* @brief Has 0x81 Set FlexRAM Function command. */
+ #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+ /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Erase sector command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Rrogram/Verify section command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Read resource command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Program check command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Program check command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Erase sector command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Read resource command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Program check command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+ /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+ /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+ /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
+ /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
+ /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
+ /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
+ /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
+ /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
+ /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
+ /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
+ /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+ /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+ /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+ /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+ /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+ /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
+#elif defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z128VMC4)
+ /* @brief Is of type FTFA. */
+ #define FSL_FEATURE_FLASH_IS_FTFA (1)
+ /* @brief Is of type FTFE. */
+ #define FSL_FEATURE_FLASH_IS_FTFE (0)
+ /* @brief Is of type FTFL. */
+ #define FSL_FEATURE_FLASH_IS_FTFL (0)
+ /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
+ /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+ #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
+ /* @brief Has EEPROM region protection (register FEPROT). */
+ #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
+ /* @brief Has data flash region protection (register FDPROT). */
+ #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
+ /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+ #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+ /* @brief Has flash cache control in FMC module. */
+ #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
+ /* @brief Has flash cache control in MCM module. */
+ #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
+ /* @brief Has flash cache control in MSCM module. */
+ #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
+ /* @brief Has prefetch speculation control in flash, such as kv5x. */
+ #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
+ /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
+ #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
+ /* @brief P-Flash start address. */
+ #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+ /* @brief P-Flash block count. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+ /* @brief P-Flash block size. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536)
+ /* @brief P-Flash sector size. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
+ /* @brief P-Flash write unit size. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
+ /* @brief P-Flash data path width. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
+ /* @brief P-Flash block swap feature. */
+ #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+ /* @brief P-Flash protection region count. */
+ #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
+ /* @brief Has FlexNVM memory. */
+ #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+ /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+ /* @brief FlexNVM block count. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+ /* @brief FlexNVM block size. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+ /* @brief FlexNVM sector size. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+ /* @brief FlexNVM write unit size. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+ /* @brief FlexNVM data path width. */
+ #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+ /* @brief Has FlexRAM memory. */
+ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
+ /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+ #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
+ /* @brief FlexRAM size. */
+ #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
+ /* @brief Has 0x00 Read 1s Block command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+ /* @brief Has 0x01 Read 1s Section command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+ /* @brief Has 0x02 Program Check command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+ /* @brief Has 0x03 Read Resource command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+ /* @brief Has 0x06 Program Longword command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
+ /* @brief Has 0x07 Program Phrase command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
+ /* @brief Has 0x08 Erase Flash Block command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+ /* @brief Has 0x09 Erase Flash Sector command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+ /* @brief Has 0x0B Program Section command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
+ /* @brief Has 0x40 Read 1s All Blocks command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+ /* @brief Has 0x41 Read Once command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+ /* @brief Has 0x43 Program Once command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+ /* @brief Has 0x44 Erase All Blocks command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+ /* @brief Has 0x45 Verify Backdoor Access Key command. */
+ #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+ /* @brief Has 0x46 Swap Control command. */
+ #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+ /* @brief Has 0x49 Erase All Blocks Unsecure command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
+ /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+ /* @brief Has 0x4B Erase All Execute-only Segments command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+ /* @brief Has 0x80 Program Partition command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+ /* @brief Has 0x81 Set FlexRAM Function command. */
+ #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+ /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Erase sector command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Rrogram/Verify section command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Read resource command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Program check command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Program check command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Erase sector command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Read resource command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Program check command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+ /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+ /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+ /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
+ /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
+ /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
+ /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
+ /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
+ /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
+ /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
+ /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
+ /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+ /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+ /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+ /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+ /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+ /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
+#elif defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL26Z256VMP4)
+ /* @brief Is of type FTFA. */
+ #define FSL_FEATURE_FLASH_IS_FTFA (1)
+ /* @brief Is of type FTFE. */
+ #define FSL_FEATURE_FLASH_IS_FTFE (0)
+ /* @brief Is of type FTFL. */
+ #define FSL_FEATURE_FLASH_IS_FTFL (0)
+ /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
+ /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+ #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
+ /* @brief Has EEPROM region protection (register FEPROT). */
+ #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
+ /* @brief Has data flash region protection (register FDPROT). */
+ #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
+ /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+ #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+ /* @brief Has flash cache control in FMC module. */
+ #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
+ /* @brief Has flash cache control in MCM module. */
+ #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
+ /* @brief Has flash cache control in MSCM module. */
+ #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
+ /* @brief Has prefetch speculation control in flash, such as kv5x. */
+ #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
+ /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
+ #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
+ /* @brief P-Flash start address. */
+ #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+ /* @brief P-Flash block count. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+ /* @brief P-Flash block size. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072)
+ /* @brief P-Flash sector size. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
+ /* @brief P-Flash write unit size. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
+ /* @brief P-Flash data path width. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
+ /* @brief P-Flash block swap feature. */
+ #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+ /* @brief P-Flash protection region count. */
+ #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
+ /* @brief Has FlexNVM memory. */
+ #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+ /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+ /* @brief FlexNVM block count. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+ /* @brief FlexNVM block size. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+ /* @brief FlexNVM sector size. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+ /* @brief FlexNVM write unit size. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+ /* @brief FlexNVM data path width. */
+ #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+ /* @brief Has FlexRAM memory. */
+ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
+ /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+ #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
+ /* @brief FlexRAM size. */
+ #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
+ /* @brief Has 0x00 Read 1s Block command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+ /* @brief Has 0x01 Read 1s Section command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+ /* @brief Has 0x02 Program Check command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+ /* @brief Has 0x03 Read Resource command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+ /* @brief Has 0x06 Program Longword command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
+ /* @brief Has 0x07 Program Phrase command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
+ /* @brief Has 0x08 Erase Flash Block command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+ /* @brief Has 0x09 Erase Flash Sector command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+ /* @brief Has 0x0B Program Section command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
+ /* @brief Has 0x40 Read 1s All Blocks command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+ /* @brief Has 0x41 Read Once command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+ /* @brief Has 0x43 Program Once command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+ /* @brief Has 0x44 Erase All Blocks command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+ /* @brief Has 0x45 Verify Backdoor Access Key command. */
+ #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+ /* @brief Has 0x46 Swap Control command. */
+ #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+ /* @brief Has 0x49 Erase All Blocks Unsecure command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
+ /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+ /* @brief Has 0x4B Erase All Execute-only Segments command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+ /* @brief Has 0x80 Program Partition command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+ /* @brief Has 0x81 Set FlexRAM Function command. */
+ #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+ /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Erase sector command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Rrogram/Verify section command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Read resource command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Program check command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Program check command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Erase sector command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Read resource command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Program check command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+ /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+ /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+ /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
+ /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
+ /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
+ /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
+ /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
+ /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
+ /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
+ /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
+ /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+ /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+ /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+ /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+ /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+ /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
+#elif defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z32VLH4)
+ /* @brief Is of type FTFA. */
+ #define FSL_FEATURE_FLASH_IS_FTFA (1)
+ /* @brief Is of type FTFE. */
+ #define FSL_FEATURE_FLASH_IS_FTFE (0)
+ /* @brief Is of type FTFL. */
+ #define FSL_FEATURE_FLASH_IS_FTFL (0)
+ /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
+ /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+ #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
+ /* @brief Has EEPROM region protection (register FEPROT). */
+ #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
+ /* @brief Has data flash region protection (register FDPROT). */
+ #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
+ /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+ #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+ /* @brief Has flash cache control in FMC module. */
+ #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
+ /* @brief Has flash cache control in MCM module. */
+ #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
+ /* @brief Has flash cache control in MSCM module. */
+ #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
+ /* @brief Has prefetch speculation control in flash, such as kv5x. */
+ #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
+ /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
+ #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
+ /* @brief P-Flash start address. */
+ #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+ /* @brief P-Flash block count. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
+ /* @brief P-Flash block size. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (32768)
+ /* @brief P-Flash sector size. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
+ /* @brief P-Flash write unit size. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
+ /* @brief P-Flash data path width. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
+ /* @brief P-Flash block swap feature. */
+ #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+ /* @brief P-Flash protection region count. */
+ #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
+ /* @brief Has FlexNVM memory. */
+ #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+ /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+ /* @brief FlexNVM block count. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+ /* @brief FlexNVM block size. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+ /* @brief FlexNVM sector size. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+ /* @brief FlexNVM write unit size. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+ /* @brief FlexNVM data path width. */
+ #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+ /* @brief Has FlexRAM memory. */
+ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
+ /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+ #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
+ /* @brief FlexRAM size. */
+ #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
+ /* @brief Has 0x00 Read 1s Block command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
+ /* @brief Has 0x01 Read 1s Section command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+ /* @brief Has 0x02 Program Check command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+ /* @brief Has 0x03 Read Resource command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+ /* @brief Has 0x06 Program Longword command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
+ /* @brief Has 0x07 Program Phrase command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
+ /* @brief Has 0x08 Erase Flash Block command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
+ /* @brief Has 0x09 Erase Flash Sector command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+ /* @brief Has 0x0B Program Section command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
+ /* @brief Has 0x40 Read 1s All Blocks command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+ /* @brief Has 0x41 Read Once command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+ /* @brief Has 0x43 Program Once command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+ /* @brief Has 0x44 Erase All Blocks command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+ /* @brief Has 0x45 Verify Backdoor Access Key command. */
+ #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+ /* @brief Has 0x46 Swap Control command. */
+ #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+ /* @brief Has 0x49 Erase All Blocks Unsecure command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
+ /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+ /* @brief Has 0x4B Erase All Execute-only Segments command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+ /* @brief Has 0x80 Program Partition command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+ /* @brief Has 0x81 Set FlexRAM Function command. */
+ #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+ /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Erase sector command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Rrogram/Verify section command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Read resource command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Program check command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Program check command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Erase sector command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Read resource command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Program check command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+ /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+ /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+ /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
+ /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
+ /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
+ /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
+ /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
+ /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
+ /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
+ /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
+ /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+ /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+ /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+ /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+ /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+ /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
+#elif defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z64VLH4)
+ /* @brief Is of type FTFA. */
+ #define FSL_FEATURE_FLASH_IS_FTFA (1)
+ /* @brief Is of type FTFE. */
+ #define FSL_FEATURE_FLASH_IS_FTFE (0)
+ /* @brief Is of type FTFL. */
+ #define FSL_FEATURE_FLASH_IS_FTFL (0)
+ /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
+ /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+ #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
+ /* @brief Has EEPROM region protection (register FEPROT). */
+ #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
+ /* @brief Has data flash region protection (register FDPROT). */
+ #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
+ /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+ #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+ /* @brief Has flash cache control in FMC module. */
+ #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
+ /* @brief Has flash cache control in MCM module. */
+ #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
+ /* @brief Has flash cache control in MSCM module. */
+ #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
+ /* @brief Has prefetch speculation control in flash, such as kv5x. */
+ #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
+ /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
+ #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
+ /* @brief P-Flash start address. */
+ #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+ /* @brief P-Flash block count. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
+ /* @brief P-Flash block size. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536)
+ /* @brief P-Flash sector size. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
+ /* @brief P-Flash write unit size. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
+ /* @brief P-Flash data path width. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
+ /* @brief P-Flash block swap feature. */
+ #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+ /* @brief P-Flash protection region count. */
+ #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
+ /* @brief Has FlexNVM memory. */
+ #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+ /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+ /* @brief FlexNVM block count. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+ /* @brief FlexNVM block size. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+ /* @brief FlexNVM sector size. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+ /* @brief FlexNVM write unit size. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+ /* @brief FlexNVM data path width. */
+ #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+ /* @brief Has FlexRAM memory. */
+ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
+ /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+ #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
+ /* @brief FlexRAM size. */
+ #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
+ /* @brief Has 0x00 Read 1s Block command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
+ /* @brief Has 0x01 Read 1s Section command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+ /* @brief Has 0x02 Program Check command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+ /* @brief Has 0x03 Read Resource command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+ /* @brief Has 0x06 Program Longword command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
+ /* @brief Has 0x07 Program Phrase command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
+ /* @brief Has 0x08 Erase Flash Block command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
+ /* @brief Has 0x09 Erase Flash Sector command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+ /* @brief Has 0x0B Program Section command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
+ /* @brief Has 0x40 Read 1s All Blocks command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+ /* @brief Has 0x41 Read Once command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+ /* @brief Has 0x43 Program Once command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+ /* @brief Has 0x44 Erase All Blocks command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+ /* @brief Has 0x45 Verify Backdoor Access Key command. */
+ #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+ /* @brief Has 0x46 Swap Control command. */
+ #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+ /* @brief Has 0x49 Erase All Blocks Unsecure command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
+ /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+ /* @brief Has 0x4B Erase All Execute-only Segments command. */
+ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+ /* @brief Has 0x80 Program Partition command. */
+ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+ /* @brief Has 0x81 Set FlexRAM Function command. */
+ #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+ /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Erase sector command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Rrogram/Verify section command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Read resource command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Program check command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+ /* @brief P-Flash Program check command address alignment. */
+ #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Erase sector command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Read resource command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM Program check command address alignment. */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+ /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+ /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+ /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+ /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+ /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
+ /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
+ /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
+ /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
+ /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
+ /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
+ /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
+ /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
+ /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+ /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+ /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+ /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+ /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+ /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
+#endif /* defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z128VLH4) */
+
+/* GPIO module features */
+
+/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
+#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1)
+/* @brief Has port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
+
+/* I2C module features */
+
+/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
+#define FSL_FEATURE_I2C_HAS_SMBUS (1)
+/* @brief Maximum supported baud rate in kilobit per second. */
+#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (100)
+/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
+#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (1)
+/* @brief Has DMA support (register bit C1[DMAEN]). */
+#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
+/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
+/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
+/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
+#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
+/* @brief Maximum width of the glitch filter in number of bus clocks. */
+#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
+/* @brief Has control of the drive capability of the I2C pins. */
+#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
+/* @brief Has double buffering support (register S2). */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
+/* @brief Has double buffer enable. */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0)
+
+/* SAI module features */
+
+/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
+#define FSL_FEATURE_SAI_FIFO_COUNT (1)
+/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
+#define FSL_FEATURE_SAI_CHANNEL_COUNT (1)
+/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
+#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (2)
+/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0)
+/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0)
+/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0)
+/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
+#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0)
+/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
+#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
+/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
+#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
+/* @brief Ihe interrupt source number */
+#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1)
+/* @brief Has register of MCR. */
+#define FSL_FEATURE_SAI_HAS_MCR (1)
+/* @brief Has register of MDR */
+#define FSL_FEATURE_SAI_HAS_MDR (1)
+
+/* LLWU module features */
+
+/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
+/* @brief Has pins 8-15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
+/* @brief Maximum number of internal modules connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+/* @brief Number of digital filters. */
+#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
+/* @brief Has MF register. */
+#define FSL_FEATURE_LLWU_HAS_MF (0)
+/* @brief Has PF register. */
+#define FSL_FEATURE_LLWU_HAS_PF (0)
+/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
+/* @brief Has no internal module wakeup flag register. */
+#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
+/* @brief Has external pin 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0)
+/* @brief Has external pin 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0)
+/* @brief Has external pin 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0)
+/* @brief Has external pin 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (0)
+/* @brief Has external pin 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0)
+/* @brief Has external pin 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
+/* @brief Has external pin 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
+/* @brief Has external pin 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
+/* @brief Has external pin 8 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
+/* @brief Has external pin 9 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
+/* @brief Has external pin 10 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
+/* @brief Has external pin 11 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0)
+/* @brief Has external pin 12 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
+/* @brief Has external pin 13 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0)
+/* @brief Has external pin 14 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
+/* @brief Has external pin 15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
+/* @brief Has external pin 16 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
+/* @brief Has external pin 17 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
+/* @brief Has external pin 18 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
+/* @brief Has external pin 19 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
+/* @brief Has external pin 20 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
+/* @brief Has external pin 21 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
+/* @brief Has external pin 22 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
+/* @brief Has external pin 23 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
+/* @brief Has external pin 24 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
+/* @brief Has external pin 25 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
+/* @brief Has external pin 26 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
+/* @brief Has external pin 27 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+/* @brief Has external pin 28 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+/* @brief Has external pin 29 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+/* @brief Has external pin 30 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+/* @brief Has external pin 31 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+/* @brief Has internal module 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+/* @brief Has internal module 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+/* @brief Has internal module 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0)
+/* @brief Has internal module 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
+/* @brief Has internal module 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
+/* @brief Has internal module 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+/* @brief Has internal module 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
+/* @brief Has internal module 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+/* @brief Has Version ID Register (LLWU_VERID). */
+#define FSL_FEATURE_LLWU_HAS_VERID (0)
+/* @brief Has Parameter Register (LLWU_PARAM). */
+#define FSL_FEATURE_LLWU_HAS_PARAM (0)
+/* @brief Width of registers of the LLWU. */
+#define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
+/* @brief Has DMA Enable register (LLWU_DE). */
+#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
+
+/* LPTMR module features */
+
+/* @brief Has shared interrupt handler with another LPTMR module. */
+#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+/* @brief Whether LPTMR counter is 32 bits width. */
+#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
+/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
+#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0)
+
+/* MCG module features */
+
+/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
+/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24)
+/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
+/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MIN (2000000)
+/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MAX (4000000)
+/* @brief The PLL clock is divided by 2 before VCO divider. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
+/* @brief FRDIV supports 1280. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
+/* @brief FRDIV supports 1536. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
+/* @brief MCGFFCLK divider. */
+#define FSL_FEATURE_MCG_FFCLK_DIV (1)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
+#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
+/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
+#define FSL_FEATURE_MCG_HAS_RTC_32K (0)
+/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_PLL1 (0)
+/* @brief Has 48MHz internal oscillator. */
+#define FSL_FEATURE_MCG_HAS_IRC_48M (0)
+/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_OSC1 (0)
+/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
+#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
+/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
+#define FSL_FEATURE_MCG_HAS_LOLRE (1)
+/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
+#define FSL_FEATURE_MCG_USE_OSCSEL (1)
+/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
+#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
+/* @brief TBD */
+#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
+/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */
+#define FSL_FEATURE_MCG_HAS_PLL (1)
+/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
+/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
+/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
+#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1)
+/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
+#define FSL_FEATURE_MCG_HAS_FLL (1)
+/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
+/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
+#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
+/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
+/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
+/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
+#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
+/* @brief Has external clock monitor (register bit C6[CME]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
+/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
+#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
+/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
+#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
+/* @brief Has PEI mode or PBI mode. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
+/* @brief Reset clock mode is BLPI. */
+#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
+
+/* OSC module features */
+
+/* @brief Has OSC1 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC1 (0)
+/* @brief Has OSC0 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC0 (1)
+/* @brief Has OSC external oscillator (without index). */
+#define FSL_FEATURE_OSC_HAS_OSC (0)
+/* @brief Number of OSC external oscillators. */
+#define FSL_FEATURE_OSC_OSC_COUNT (1)
+/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
+#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
+
+/* PIT module features */
+
+/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
+#define FSL_FEATURE_PIT_TIMER_COUNT (2)
+/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
+#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
+/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
+#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
+/* @brief Has timer enable control. */
+#define FSL_FEATURE_PIT_HAS_MDIS (1)
+
+/* PMC module features */
+
+/* @brief Has Bandgap Enable In VLPx Operation support. */
+#define FSL_FEATURE_PMC_HAS_BGEN (1)
+/* @brief Has Bandgap Buffer Enable. */
+#define FSL_FEATURE_PMC_HAS_BGBE (1)
+/* @brief Has Bandgap Buffer Drive Select. */
+#define FSL_FEATURE_PMC_HAS_BGBDS (0)
+/* @brief Has Low-Voltage Detect Voltage Select support. */
+#define FSL_FEATURE_PMC_HAS_LVDV (1)
+/* @brief Has Low-Voltage Warning Voltage Select support. */
+#define FSL_FEATURE_PMC_HAS_LVWV (1)
+/* @brief Has LPO. */
+#define FSL_FEATURE_PMC_HAS_LPO (0)
+/* @brief Has VLPx option PMC_REGSC[VLPO]. */
+#define FSL_FEATURE_PMC_HAS_VLPO (0)
+/* @brief Has acknowledge isolation support. */
+#define FSL_FEATURE_PMC_HAS_ACKISO (1)
+/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
+#define FSL_FEATURE_PMC_HAS_REGFPM (0)
+/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
+#define FSL_FEATURE_PMC_HAS_REGONS (1)
+/* @brief Has PMC_HVDSC1. */
+#define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
+/* @brief Has PMC_PARAM. */
+#define FSL_FEATURE_PMC_HAS_PARAM (0)
+/* @brief Has PMC_VERID. */
+#define FSL_FEATURE_PMC_HAS_VERID (0)
+
+/* PORT module features */
+
+/* @brief Has control lock (register bit PCR[LK]). */
+#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
+/* @brief Has open drain control (register bit PCR[ODE]). */
+#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
+/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
+#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
+/* @brief Has DMA request (register bit field PCR[IRQC] values). */
+#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
+/* @brief Has pull resistor selection available. */
+#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
+/* @brief Has pull resistor enable (register bit PCR[PE]). */
+#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
+/* @brief Has slew rate control (register bit PCR[SRE]). */
+#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
+/* @brief Has passive filter (register bit field PCR[PFE]). */
+#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
+/* @brief Has drive strength control (register bit PCR[DSE]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
+/* @brief Has separate drive strength register (HDRVE). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
+/* @brief Has glitch filter (register IOFLT). */
+#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
+/* @brief Defines width of PCR[MUX] field. */
+#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
+/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
+#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
+
+/* RCM module features */
+
+/* @brief Has Loss-of-Lock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOL (1)
+/* @brief Has Loss-of-Clock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOC (1)
+/* @brief Has JTAG generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_JTAG (0)
+/* @brief Has EzPort generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_EZPORT (0)
+/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
+#define FSL_FEATURE_RCM_HAS_EZPMS (0)
+/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
+#define FSL_FEATURE_RCM_HAS_BOOTROM (0)
+/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
+#define FSL_FEATURE_RCM_HAS_SSRS (0)
+/* @brief Has Version ID Register (RCM_VERID). */
+#define FSL_FEATURE_RCM_HAS_VERID (0)
+/* @brief Has Parameter Register (RCM_PARAM). */
+#define FSL_FEATURE_RCM_HAS_PARAM (0)
+/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
+#define FSL_FEATURE_RCM_HAS_SRIE (0)
+/* @brief Width of registers of the RCM. */
+#define FSL_FEATURE_RCM_REG_WIDTH (8)
+/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
+#define FSL_FEATURE_RCM_HAS_CORE1 (0)
+/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
+#define FSL_FEATURE_RCM_HAS_MDM_AP (1)
+/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
+#define FSL_FEATURE_RCM_HAS_WAKEUP (1)
+
+/* RTC module features */
+
+#if defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z128VLH4) || \
+ defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VFM4) || \
+ defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z64VLH4)
+ /* @brief Has wakeup pin. */
+ #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0)
+ /* @brief Has wakeup pin selection (bit field CR[WPS]). */
+ #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
+ /* @brief Has low power features (registers MER, MCLR and MCHR). */
+ #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+ /* @brief Has read/write access control (registers WAR and RAR). */
+ #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0)
+ /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+ #define FSL_FEATURE_RTC_HAS_SECURITY (0)
+ /* @brief Has RTC_CLKIN available. */
+ #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1)
+ /* @brief Has prescaler adjust for LPO. */
+ #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
+ /* @brief Has Clock Pin Enable field. */
+ #define FSL_FEATURE_RTC_HAS_CPE (0)
+ /* @brief Has Timer Seconds Interrupt Configuration field. */
+ #define FSL_FEATURE_RTC_HAS_TSIC (0)
+ /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
+ #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
+ /* @brief Has Tamper Interrupt Register (register TIR). */
+ #define FSL_FEATURE_RTC_HAS_TIR (0)
+ /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
+ #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0)
+ /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
+ #define FSL_FEATURE_RTC_HAS_TIR_SIE (0)
+ /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
+ #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0)
+ /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
+ #define FSL_FEATURE_RTC_HAS_SR_TIDF (0)
+ /* @brief Has Tamper Detect Register (register TDR). */
+ #define FSL_FEATURE_RTC_HAS_TDR (0)
+ /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
+ #define FSL_FEATURE_RTC_HAS_TDR_TPF (0)
+ /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
+ #define FSL_FEATURE_RTC_HAS_TDR_STF (0)
+ /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
+ #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0)
+ /* @brief Has Tamper Time Seconds Register (register TTSR). */
+ #define FSL_FEATURE_RTC_HAS_TTSR (0)
+ /* @brief Has Pin Configuration Register (register PCR). */
+ #define FSL_FEATURE_RTC_HAS_PCR (0)
+#elif defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLL4) || \
+ defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL26Z256VMP4)
+ /* @brief Has wakeup pin. */
+ #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+ /* @brief Has wakeup pin selection (bit field CR[WPS]). */
+ #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
+ /* @brief Has low power features (registers MER, MCLR and MCHR). */
+ #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+ /* @brief Has read/write access control (registers WAR and RAR). */
+ #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0)
+ /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+ #define FSL_FEATURE_RTC_HAS_SECURITY (0)
+ /* @brief Has RTC_CLKIN available. */
+ #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1)
+ /* @brief Has prescaler adjust for LPO. */
+ #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
+ /* @brief Has Clock Pin Enable field. */
+ #define FSL_FEATURE_RTC_HAS_CPE (0)
+ /* @brief Has Timer Seconds Interrupt Configuration field. */
+ #define FSL_FEATURE_RTC_HAS_TSIC (0)
+ /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
+ #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
+ /* @brief Has Tamper Interrupt Register (register TIR). */
+ #define FSL_FEATURE_RTC_HAS_TIR (0)
+ /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
+ #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0)
+ /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
+ #define FSL_FEATURE_RTC_HAS_TIR_SIE (0)
+ /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
+ #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0)
+ /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
+ #define FSL_FEATURE_RTC_HAS_SR_TIDF (0)
+ /* @brief Has Tamper Detect Register (register TDR). */
+ #define FSL_FEATURE_RTC_HAS_TDR (0)
+ /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
+ #define FSL_FEATURE_RTC_HAS_TDR_TPF (0)
+ /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
+ #define FSL_FEATURE_RTC_HAS_TDR_STF (0)
+ /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
+ #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0)
+ /* @brief Has Tamper Time Seconds Register (register TTSR). */
+ #define FSL_FEATURE_RTC_HAS_TTSR (0)
+ /* @brief Has Pin Configuration Register (register PCR). */
+ #define FSL_FEATURE_RTC_HAS_PCR (0)
+#endif /* defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z128VLH4) || \
+ defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VFM4) || \
+ defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z64VLH4) */
+
+/* SIM module features */
+
+/* @brief Has USB FS divider. */
+#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
+#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (1)
+/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
+/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
+/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
+/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
+/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
+/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
+/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
+/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
+/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
+/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
+/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
+/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
+#define FSL_FEATURE_SIM_OPT_HAS_ODE (1)
+/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
+#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
+/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
+#define FSL_FEATURE_SIM_OPT_UART_COUNT (3)
+/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (1)
+/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (1)
+/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (1)
+/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
+/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
+/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
+/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
+/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
+/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
+/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
+/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
+/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
+/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
+/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1)
+/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
+/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
+/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (1)
+/* @brief Has FTM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
+/* @brief Number of FTM modules. */
+#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
+/* @brief Number of FTM triggers with selectable source. */
+#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
+/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
+/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
+/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
+/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
+/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
+/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
+/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
+/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
+/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
+/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
+/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
+/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
+/* @brief Has TPM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
+/* @brief The highest TPM module index. */
+#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
+/* @brief Has TPM module with index 0. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
+/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1)
+/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1)
+/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
+/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1)
+/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2)
+/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1)
+/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1)
+/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
+/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
+/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
+/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
+/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
+/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
+/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
+/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
+/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
+/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
+/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
+/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
+/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
+/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
+/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
+/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1)
+/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
+/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
+/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
+/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1)
+/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0)
+/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
+/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
+/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
+/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
+/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
+/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
+/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
+/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
+/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
+/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
+/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
+/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3)
+/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
+/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
+/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
+/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
+/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
+/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
+/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
+/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
+/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
+/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
+/* @brief Has device die ID (register bit field SDID[DIEID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
+/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1)
+/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
+/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
+/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
+/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
+/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
+/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
+/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
+/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
+/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
+/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
+/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
+/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
+/* @brief Has miscellanious control register (register MCR). */
+#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
+/* @brief Has COP watchdog (registers COPC and SRVCOP). */
+#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1)
+/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
+#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
+/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
+#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
+
+/* SMC module features */
+
+/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
+#define FSL_FEATURE_SMC_HAS_PSTOPO (1)
+/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
+#define FSL_FEATURE_SMC_HAS_LPOPO (0)
+/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
+#define FSL_FEATURE_SMC_HAS_PORPO (1)
+/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
+#define FSL_FEATURE_SMC_HAS_LPWUI (0)
+/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
+#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
+/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
+/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1)
+/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
+#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
+/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
+#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
+/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
+#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
+#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has stop submode. */
+#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
+/* @brief Has stop submode 0(VLLS0). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
+/* @brief Has stop submode 1(VLLS1). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1)
+/* @brief Has stop submode 2(VLLS2). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0)
+/* @brief Has SMC_PARAM. */
+#define FSL_FEATURE_SMC_HAS_PARAM (0)
+/* @brief Has SMC_VERID. */
+#define FSL_FEATURE_SMC_HAS_VERID (0)
+/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
+#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
+/* @brief Has tamper reset (register bit SRS[TAMPER]). */
+#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
+/* @brief Has security violation reset (register bit SRS[SECVIO]). */
+#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
+
+/* SPI module features */
+
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_SPI_HAS_FIFO (1)
+/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). */
+#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_SPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0)
+/* @brief Receive/transmit FIFO size in number of 16-bit communication items. */
+#define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
+ ((x) == SPI0 ? (0) : \
+ ((x) == SPI1 ? (4) : (-1)))
+/* @brief Maximum transfer data width in bits. */
+#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
+/* @brief The data register name has postfix (L as low and H as high). */
+#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1)
+/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
+#define FSL_FEATURE_SPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
+/* @brief Has 16-bit data transfer support. */
+#define FSL_FEATURE_SPI_16BIT_TRANSFERS (1)
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16)
+
+/* TPM module features */
+
+/* @brief Bus clock is the source clock for the module. */
+#define FSL_FEATURE_TPM_BUS_CLOCK (0)
+/* @brief Number of channels. */
+#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
+ ((x) == TPM0 ? (6) : \
+ ((x) == TPM1 ? (2) : \
+ ((x) == TPM2 ? (2) : (-1))))
+/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
+#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
+/* @brief Has TPM_PARAM. */
+#define FSL_FEATURE_TPM_HAS_PARAM (0)
+/* @brief Has TPM_VERID. */
+#define FSL_FEATURE_TPM_HAS_VERID (0)
+/* @brief Has TPM_GLOBAL. */
+#define FSL_FEATURE_TPM_HAS_GLOBAL (0)
+/* @brief Has TPM_TRIG. */
+#define FSL_FEATURE_TPM_HAS_TRIG (0)
+/* @brief Has counter pause on trigger. */
+#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (0)
+/* @brief Has external trigger selection. */
+#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (0)
+/* @brief Has TPM_COMBINE register. */
+#define FSL_FEATURE_TPM_HAS_COMBINE (0)
+/* @brief Whether COMBINE register has effect. */
+#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (0)
+/* @brief Has TPM_POL. */
+#define FSL_FEATURE_TPM_HAS_POL (0)
+/* @brief Has TPM_FILTER register. */
+#define FSL_FEATURE_TPM_HAS_FILTER (0)
+/* @brief Whether FILTER register has effect. */
+#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (0)
+/* @brief Has TPM_QDCTRL register. */
+#define FSL_FEATURE_TPM_HAS_QDCTRL (0)
+/* @brief Whether QDCTRL register has effect. */
+#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (0)
+
+/* TSI module features */
+
+/* @brief TSI module version. */
+#define FSL_FEATURE_TSI_VERSION (4)
+/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */
+#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0)
+/* @brief Number of TSI channels. */
+#define FSL_FEATURE_TSI_CHANNEL_COUNT (16)
+
+/* LPSCI module features */
+
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_LPSCI_HAS_IRQ_EXTENDED_FUNCTIONS (1)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPSCI_HAS_LOW_POWER_UART_SUPPORT (1)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPSCI_HAS_EXTENDED_DATA_REGISTER_FLAGS (0)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPSCI_HAS_FIFO (0)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_LPSCI_HAS_MODEM_SUPPORT (0)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_LPSCI_HAS_IR_SUPPORT (0)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_LPSCI_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief If 10-bit mode is supported. */
+#define FSL_FEATURE_LPSCI_HAS_10BIT_DATA_SUPPORT (1)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_LPSCI_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPSCI_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPSCI_HAS_RX_RESYNC_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPSCI_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_LPSCI_IS_SCI (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPSCI_FIFO_SIZE (0)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_LPSCI_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
+/* @brief Maximal data width with parity bit. */
+#define FSL_FEATURE_LPSCI_MAX_DATA_WIDTH_WITH_PARITY (9)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_LPSCI_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPSCI_HAS_DMA_ENABLE (1)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_LPSCI_HAS_DMA_SELECT (0)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPSCI_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_LPSCI_HAS_SMART_CARD_SUPPORT (0)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_LPSCI_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_LPSCI_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_LPSCI_HAS_32BIT_REGISTERS (0)
+/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
+#define FSL_FEATURE_LPSCI_HAS_LIN_BREAK_DETECT (1)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_LPSCI_HAS_WAIT_MODE_OPERATION (0)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPSCI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+
+/* UART module features */
+
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_HAS_FIFO (0)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_UART_HAS_IR_SUPPORT (0)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief If 10-bit mode is supported. */
+#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_UART_IS_SCI (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_FIFO_SIZE (0)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
+/* @brief Maximal data width with parity bit. */
+#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (8)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (0)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (0)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
+/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
+#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+
+/* USB module features */
+
+/* @brief KHCI module instance count */
+#define FSL_FEATURE_USB_KHCI_COUNT (1)
+/* @brief HOST mode enabled */
+#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
+/* @brief OTG mode enabled */
+#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_KHCI_USB_RAM (0)
+/* @brief Has KEEP_ALIVE_CTRL register */
+#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
+/* @brief Has the Dynamic SOF threshold compare support */
+#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
+/* @brief Has the VBUS detect support */
+#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
+/* @brief Has the IRC48M module clock support */
+#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (0)
+/* @brief Number of endpoints supported */
+#define FSL_FEATURE_USB_ENDPT_COUNT (16)
+/* @brief Has STALL_IL/OL_DIS registers */
+#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (0)
+/* @brief Has STALL_IH/OH_DIS registers */
+#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (0)
+
+#endif /* _MKL26Z4_FEATURES_H_ */
+
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_COMMON_H_
+#define _FSL_COMMON_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+
+#if defined(__ICCARM__)
+#include <stddef.h>
+#endif
+
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Construct a status code value from a group and code number. */
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
+
+/*! @brief Construct the version number for drivers. */
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief common driver version 2.0.0. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/* Debug console type definition. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console base on LPC_USART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console base on SWO. */
+
+/*! @brief Status group numbers. */
+enum _status_groups
+{
+ kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
+ kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
+ kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
+ kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
+ kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
+ kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
+ kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
+ kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
+ kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
+ kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
+ kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
+ kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
+ kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
+ kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
+ kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
+ kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
+ kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
+ kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
+ kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
+ kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
+ kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
+ kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
+ kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
+ kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
+ kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
+ kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
+ kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
+ kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
+ kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */
+ kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
+ kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
+ kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
+ kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
+ kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
+ kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
+ kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
+ kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
+ kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
+ kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
+ kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
+ kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
+ kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
+ kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
+ kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
+ kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
+ kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
+ kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
+ kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
+ kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
+ kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
+ kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
+ kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
+ kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
+ kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
+ kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/
+ kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/
+ kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
+ kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
+ kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
+ kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */
+ kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
+ kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
+ kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
+ kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
+ kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
+ kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
+ kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
+ kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
+};
+
+/*! @brief Generic status return codes. */
+enum _generic_status
+{
+ kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
+ kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
+ kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
+ kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
+ kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
+ kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
+ kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
+};
+
+/*! @brief Type used for all status and error return values. */
+typedef int32_t status_t;
+
+/*
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
+ * defined in previous of this file.
+ */
+#include "fsl_clock.h"
+
+/*
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
+ */
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+ (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+#include "fsl_reset.h"
+#endif
+
+/*
+ * Macro guard for whether to use default weak IRQ implementation in drivers
+ */
+#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
+#endif
+
+/*! @name Min/max macros */
+/* @{ */
+#if !defined(MIN)
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#endif
+/* @} */
+
+/*! @brief Computes the number of elements in an array. */
+#if !defined(ARRAY_SIZE)
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#endif
+
+/*! @name UINT16_MAX/UINT32_MAX value */
+/* @{ */
+#if !defined(UINT16_MAX)
+#define UINT16_MAX ((uint16_t)-1)
+#endif
+
+#if !defined(UINT32_MAX)
+#define UINT32_MAX ((uint32_t)-1)
+#endif
+/* @} */
+
+/*! @name Timer utilities */
+/* @{ */
+/*! Macro to convert a microsecond period to raw count value */
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
+/*! Macro to convert a raw count value to microsecond */
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
+
+/*! Macro to convert a millisecond period to raw count value */
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
+/*! Macro to convert a raw count value to millisecond */
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
+/* @} */
+
+/*! @name Alignment variable definition macros */
+/* @{ */
+#if (defined(__ICCARM__))
+/**
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.
+ * http://supp.iar.com/Support/?note=24725
+ */
+_Pragma("diag_suppress=Pm120")
+#define SDK_PRAGMA(x) _Pragma(#x)
+ _Pragma("diag_error=Pm120")
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
+#endif
+#elif defined(__ARMCC_VERSION)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
+#endif
+#elif defined(__GNUC__)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
+#endif
+#else
+#error Toolchain not supported
+#define SDK_ALIGN(var, alignbytes) var
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) var
+#endif
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) var
+#endif
+#endif
+
+/*! Macro to change a value to a given size aligned value */
+#define SDK_SIZEALIGN(var, alignbytes) \
+ ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
+/* @} */
+
+/*! @name Non-cacheable region definition macros */
+/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
+ * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
+ * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
+ * will be initialized to zero in system startup.
+ */
+/* @{ */
+#if (defined(__ICCARM__))
+#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+#endif
+#elif(defined(__ARMCC_VERSION))
+#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+ __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+ __attribute__((section("NonCacheable.init"))) __align(alignbytes) var
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var
+#endif
+#elif(defined(__GNUC__))
+/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
+ */
+#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+ __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+ __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))
+#endif
+#else
+#error Toolchain not supported.
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
+#endif
+/* @} */
+
+/*! @name Time sensitive region */
+/* @{ */
+#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
+#if (defined(__ICCARM__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
+#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
+#elif(defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
+#elif(defined(__GNUC__))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+#else
+#if (defined(__ICCARM__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#elif(defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#elif(defined(__GNUC__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#else
+#error Toolchain not supported.
+#endif
+#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
+/* @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+ extern "C"
+{
+#endif
+
+ /*!
+ * @brief Enable specific interrupt.
+ *
+ * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt enabled successfully
+ * @retval kStatus_Fail Failed to enable the interrupt
+ */
+ static inline status_t EnableIRQ(IRQn_Type interrupt)
+ {
+ if (NotAvail_IRQn == interrupt)
+ {
+ return kStatus_Fail;
+ }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+ if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+ {
+ return kStatus_Fail;
+ }
+#endif
+
+#if defined(__GIC_PRIO_BITS)
+ GIC_EnableIRQ(interrupt);
+#else
+ NVIC_EnableIRQ(interrupt);
+#endif
+ return kStatus_Success;
+ }
+
+ /*!
+ * @brief Disable specific interrupt.
+ *
+ * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt disabled successfully
+ * @retval kStatus_Fail Failed to disable the interrupt
+ */
+ static inline status_t DisableIRQ(IRQn_Type interrupt)
+ {
+ if (NotAvail_IRQn == interrupt)
+ {
+ return kStatus_Fail;
+ }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+ if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+ {
+ return kStatus_Fail;
+ }
+#endif
+
+#if defined(__GIC_PRIO_BITS)
+ GIC_DisableIRQ(interrupt);
+#else
+ NVIC_DisableIRQ(interrupt);
+#endif
+ return kStatus_Success;
+ }
+
+ /*!
+ * @brief Disable the global IRQ
+ *
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask
+ * register for the EnableGlobalIRQ().
+ *
+ * @return Current primask value.
+ */
+ static inline uint32_t DisableGlobalIRQ(void)
+ {
+#if defined(CPSR_I_Msk)
+ uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
+
+ __disable_irq();
+
+ return cpsr;
+#else
+ uint32_t regPrimask = __get_PRIMASK();
+
+ __disable_irq();
+
+ return regPrimask;
+#endif
+ }
+
+ /*!
+ * @brief Enaable the global IRQ
+ *
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+ * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+ *
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+ * DisableGlobalIRQ().
+ */
+ static inline void EnableGlobalIRQ(uint32_t primask)
+ {
+#if defined(CPSR_I_Msk)
+ __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
+#else
+ __set_PRIMASK(primask);
+#endif
+ }
+
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+ /*!
+ * @brief install IRQ handler
+ *
+ * @param irq IRQ number
+ * @param irqHandler IRQ handler address
+ * @return The old IRQ handler address
+ */
+ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+ /*!
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Enable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+ void EnableDeepSleepIRQ(IRQn_Type interrupt);
+
+ /*!
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Disable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+ void DisableDeepSleepIRQ(IRQn_Type interrupt);
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+ /*!
+ * @brief Allocate memory with given alignment and aligned size.
+ *
+ * This is provided to support the dynamically allocated memory
+ * used in cache-able region.
+ * @param size The length required to malloc.
+ * @param alignbytes The alignment size.
+ * @retval The allocated memory.
+ */
+ void *SDK_Malloc(size_t size, size_t alignbytes);
+
+ /*!
+ * @brief Free memory.
+ *
+ * @param ptr The memory to be release.
+ */
+ void SDK_Free(void *ptr);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_COMMON_H_ */
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted (subject to the limitations in the
+ * disclaimer below) provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+ * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z128VFT4) || \
+ defined(CPU_MKL26Z128VLH4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z128VMC4) || \
+ defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z256VMC4) || \
+ defined(CPU_MKL26Z256VMP4) || defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z32VFT4) || \
+ defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z64VFT4) || \
+ defined(CPU_MKL26Z64VLH4))
+
+#define KL26Z4_SERIES
+
+/* CMSIS-style register definitions */
+#include "MKL26Z4.h"
+/* CPU specific feature definitions */
+#include "MKL26Z4_features.h"
+
+#else
+ #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __USB_H__
+#define __USB_H__
+
+#include <stdint.h>
+#include <stdio.h>
+#include "fsl_common.h"
+#include "usb_osa.h"
+#include "usb_misc.h"
+#include "usb_spec.h"
+
+/*!
+ * @addtogroup usb_drv
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Defines USB stack major version */
+#define USB_STACK_VERSION_MAJOR (2U)
+/*! @brief Defines USB stack minor version */
+#define USB_STACK_VERSION_MINOR (0U)
+/*! @brief Defines USB stack bugfix version */
+#define USB_STACK_VERSION_BUGFIX (1U)
+
+/*! @brief USB stack version definition */
+#define USB_MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+
+/*! @brief USB error code */
+typedef enum _usb_status
+{
+ kStatus_USB_Success = 0x00U, /*!< Success */
+ kStatus_USB_Error, /*!< Failed */
+
+ kStatus_USB_Busy, /*!< Busy */
+ kStatus_USB_InvalidHandle, /*!< Invalid handle */
+ kStatus_USB_InvalidParameter, /*!< Invalid parameter */
+ kStatus_USB_InvalidRequest, /*!< Invalid request */
+ kStatus_USB_ControllerNotFound, /*!< Controller cannot be found */
+ kStatus_USB_InvalidControllerInterface, /*!< Invalid controller interface */
+
+ kStatus_USB_NotSupported, /*!< Configuration is not supported */
+ kStatus_USB_Retry, /*!< Enumeration get configuration retry */
+ kStatus_USB_TransferStall, /*!< Transfer stalled */
+ kStatus_USB_TransferFailed, /*!< Transfer failed */
+ kStatus_USB_AllocFail, /*!< Allocation failed */
+ kStatus_USB_LackSwapBuffer, /*!< Insufficient swap buffer for KHCI */
+ kStatus_USB_TransferCancel, /*!< The transfer cancelled */
+ kStatus_USB_BandwidthFail, /*!< Allocate bandwidth failed */
+ kStatus_USB_MSDStatusFail, /*!< For MSD, the CSW status means fail */
+ kStatus_USB_EHCIAttached,
+ kStatus_USB_EHCIDetached,
+} usb_status_t;
+
+/*! @brief USB host handle type define */
+typedef void *usb_host_handle;
+
+/*! @brief USB device handle type define. For device stack it is the whole device handle; for host stack it is the
+ * attached device instance handle*/
+typedef void *usb_device_handle;
+
+/*! @brief USB OTG handle type define */
+typedef void *usb_otg_handle;
+
+/*! @brief USB controller ID */
+typedef enum _usb_controller_index
+{
+ kUSB_ControllerKhci0 = 0U, /*!< KHCI 0U */
+ kUSB_ControllerKhci1 = 1U, /*!< KHCI 1U, Currently, there are no platforms which have two KHCI IPs, this is reserved
+ to be used in the future. */
+ kUSB_ControllerEhci0 = 2U, /*!< EHCI 0U */
+ kUSB_ControllerEhci1 = 3U, /*!< EHCI 1U, Currently, there are no platforms which have two EHCI IPs, this is reserved
+ to be used in the future. */
+
+ kUSB_ControllerLpcIp3511Fs0 = 4U, /*!< LPC USB IP3511 FS controller 0 */
+ kUSB_ControllerLpcIp3511Fs1 =
+ 5U, /*!< LPC USB IP3511 FS controller 1, there are no platforms which have two IP3511 IPs, this is reserved
+ to be used in the future. */
+
+ kUSB_ControllerLpcIp3511Hs0 = 6U, /*!< LPC USB IP3511 HS controller 0 */
+ kUSB_ControllerLpcIp3511Hs1 =
+ 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which have two IP3511 IPs, this is reserved
+ to be used in the future. */
+
+ kUSB_ControllerOhci0 = 8U, /*!< OHCI 0U */
+ kUSB_ControllerOhci1 = 9U, /*!< OHCI 1U, Currently, there are no platforms which have two OHCI IPs, this is reserved
+ to be used in the future. */
+
+ kUSB_ControllerIp3516Hs0 = 10U, /*!< IP3516HS 0U */
+ kUSB_ControllerIp3516Hs1 =
+ 11U, /*!< IP3516HS 1U, Currently, there are no platforms which have two IP3516HS IPs, this is reserved
+ to be used in the future. */
+} usb_controller_index_t;
+
+/**
+* @brief USB stack version fields
+*/
+typedef struct _usb_version
+{
+ uint8_t major; /*!< Major */
+ uint8_t minor; /*!< Minor */
+ uint8_t bugfix; /*!< Bug fix */
+} usb_version_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*! @} */
+
+#endif /* __USB_H__ */
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __USB_DEVICE_H__
+#define __USB_DEVICE_H__
+
+/*!
+ * @addtogroup usb_device_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Defines Get/Set status Types */
+typedef enum _usb_device_status
+{
+ kUSB_DeviceStatusTestMode = 1U, /*!< Test mode */
+ kUSB_DeviceStatusSpeed, /*!< Current speed */
+ kUSB_DeviceStatusOtg, /*!< OTG status */
+ kUSB_DeviceStatusDevice, /*!< Device status */
+ kUSB_DeviceStatusEndpoint, /*!< Endpoint state usb_device_endpoint_status_t */
+ kUSB_DeviceStatusDeviceState, /*!< Device state */
+ kUSB_DeviceStatusAddress, /*!< Device address */
+ kUSB_DeviceStatusSynchFrame, /*!< Current frame */
+ kUSB_DeviceStatusBus, /*!< Bus status */
+ kUSB_DeviceStatusBusSuspend, /*!< Bus suspend */
+ kUSB_DeviceStatusBusSleep, /*!< Bus suspend */
+ kUSB_DeviceStatusBusResume, /*!< Bus resume */
+ kUSB_DeviceStatusRemoteWakeup, /*!< Remote wakeup state */
+ kUSB_DeviceStatusBusSleepResume, /*!< Bus resume */
+} usb_device_status_t;
+
+/*! @brief Defines USB 2.0 device state */
+typedef enum _usb_device_state
+{
+ kUSB_DeviceStateConfigured = 0U, /*!< Device state, Configured*/
+ kUSB_DeviceStateAddress, /*!< Device state, Address*/
+ kUSB_DeviceStateDefault, /*!< Device state, Default*/
+ kUSB_DeviceStateAddressing, /*!< Device state, Address setting*/
+ kUSB_DeviceStateTestMode, /*!< Device state, Test mode*/
+} usb_device_state_t;
+
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U))
+typedef enum _usb_dcd_detection_sequence_status
+{
+ kUSB_DcdDetectionNotEnabled = 0x0U,
+ kUSB_DcdDataPinDetectionCompleted = 0x01U,
+ kUSB_DcdChargingPortDetectionCompleted = 0x02U,
+ kUSB_DcdChargerTypeDetectionCompleted = 0x03U,
+} usb_dcd_detection_sequence_status_t;
+
+typedef enum _usb_dcd_detection_sequence_results
+{
+ kUSB_DcdDetectionNoResults = 0x0U,
+ kUSB_DcdDetectionStandardHost = 0x01U,
+ kUSB_DcdDetectionChargingPort = 0x02U,
+ kUSB_DcdDetectionDedicatedCharger = 0x03U,
+} usb_dcd_detection_sequence_results_t;
+#endif
+
+/*! @brief Defines endpoint state */
+typedef enum _usb_endpoint_status
+{
+ kUSB_DeviceEndpointStateIdle = 0U, /*!< Endpoint state, idle*/
+ kUSB_DeviceEndpointStateStalled, /*!< Endpoint state, stalled*/
+} usb_device_endpoint_status_t;
+
+/*! @brief Control endpoint index */
+#define USB_CONTROL_ENDPOINT (0U)
+/*! @brief Control endpoint maxPacketSize */
+#define USB_CONTROL_MAX_PACKET_SIZE (64U)
+
+#if (USB_DEVICE_CONFIG_EHCI && (USB_CONTROL_MAX_PACKET_SIZE != (64U)))
+#error For high speed, USB_CONTROL_MAX_PACKET_SIZE must be 64!!!
+#endif
+
+/*! @brief The setup packet size of USB control transfer. */
+#define USB_SETUP_PACKET_SIZE (8U)
+/*! @brief USB endpoint mask */
+#define USB_ENDPOINT_NUMBER_MASK (0x0FU)
+
+/*! @brief Default invalid value or the endpoint callback length of cancelled transfer */
+#define USB_UNINITIALIZED_VAL_32 (0xFFFFFFFFU)
+
+/*! @brief Available common EVENT types in device callback */
+typedef enum _usb_device_event
+{
+ kUSB_DeviceEventBusReset = 1U, /*!< USB bus reset signal detected */
+ kUSB_DeviceEventSuspend, /*!< USB bus suspend signal detected */
+ kUSB_DeviceEventResume, /*!< USB bus resume signal detected. The resume signal is driven by itself or a host */
+ kUSB_DeviceEventSleeped, /*!< USB bus LPM suspend signal detected */
+ kUSB_DeviceEventLPMResume, /*!< USB bus LPM resume signal detected. The resume signal is driven by itself or a host
+ */
+ kUSB_DeviceEventError, /*!< An error is happened in the bus. */
+ kUSB_DeviceEventDetach, /*!< USB device is disconnected from a host. */
+ kUSB_DeviceEventAttach, /*!< USB device is connected to a host. */
+ kUSB_DeviceEventSetConfiguration, /*!< Set configuration. */
+ kUSB_DeviceEventSetInterface, /*!< Set interface. */
+
+ kUSB_DeviceEventGetDeviceDescriptor, /*!< Get device descriptor. */
+ kUSB_DeviceEventGetConfigurationDescriptor, /*!< Get configuration descriptor. */
+ kUSB_DeviceEventGetStringDescriptor, /*!< Get string descriptor. */
+ kUSB_DeviceEventGetHidDescriptor, /*!< Get HID descriptor. */
+ kUSB_DeviceEventGetHidReportDescriptor, /*!< Get HID report descriptor. */
+ kUSB_DeviceEventGetHidPhysicalDescriptor, /*!< Get HID physical descriptor. */
+ kUSB_DeviceEventGetBOSDescriptor, /*!< Get configuration descriptor. */
+ kUSB_DeviceEventGetDeviceQualifierDescriptor, /*!< Get device qualifier descriptor. */
+ kUSB_DeviceEventVendorRequest, /*!< Vendor request. */
+ kUSB_DeviceEventSetRemoteWakeup, /*!< Enable or disable remote wakeup function. */
+ kUSB_DeviceEventGetConfiguration, /*!< Get current configuration index */
+ kUSB_DeviceEventGetInterface, /*!< Get current interface alternate setting value */
+ kUSB_DeviceEventSetBHNPEnable,
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U))
+ kUSB_DeviceEventDcdTimeOut, /*!< Dcd detect result is timeout */
+ kUSB_DeviceEventDcdUnknownType, /*!< Dcd detect result is unknown type */
+ kUSB_DeviceEventSDPDetected, /*!< The SDP facility is detected */
+ kUSB_DeviceEventChargingPortDetected, /*!< The charging port is detected */
+ kUSB_DeviceEventChargingHostDetected, /*!< The CDP facility is detected */
+ kUSB_DeviceEventDedicatedChargerDetected, /*!< The DCP facility is detected */
+#endif
+} usb_device_event_t;
+
+/*! @brief Endpoint callback message structure */
+typedef struct _usb_device_endpoint_callback_message_struct
+{
+ uint8_t *buffer; /*!< Transferred buffer */
+ uint32_t length; /*!< Transferred data length */
+ uint8_t isSetup; /*!< Is in a setup phase */
+} usb_device_endpoint_callback_message_struct_t;
+
+/*!
+ * @brief Endpoint callback function typedef.
+ *
+ * This callback function is used to notify the upper layer what the transfer result is.
+ * This callback pointer is passed when a specified endpoint is initialized by calling API #USB_DeviceInitEndpoint.
+ *
+ * @param handle The device handle. It equals to the value returned from #USB_DeviceInit.
+ * @param message The result of a transfer, which includes transfer buffer, transfer length, and whether is in a
+ * setup phase.
+ * phase for control pipe.
+ * @param callbackParam The parameter for this callback. It is same with
+ * usb_device_endpoint_callback_struct_t::callbackParam.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+typedef usb_status_t (*usb_device_endpoint_callback_t)(usb_device_handle handle,
+ usb_device_endpoint_callback_message_struct_t *message,
+ void *callbackParam);
+
+/*!
+ * @brief Device callback function typedef.
+ *
+ * This callback function is used to notify the upper layer that the device status has changed.
+ * This callback pointer is passed by calling API #USB_DeviceInit.
+ *
+ * @param handle The device handle. It equals the value returned from #USB_DeviceInit.
+ * @param callbackEvent The callback event type. See enumeration #usb_device_event_t.
+ * @param eventParam The event parameter for this callback. The parameter type is determined by the callback event.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+typedef usb_status_t (*usb_device_callback_t)(usb_device_handle handle, uint32_t callbackEvent, void *eventParam);
+
+/*! @brief Endpoint callback structure */
+typedef struct _usb_device_endpoint_callback_struct
+{
+ usb_device_endpoint_callback_t callbackFn; /*!< Endpoint callback function*/
+ void *callbackParam; /*!< Parameter for callback function*/
+ uint8_t isBusy;
+} usb_device_endpoint_callback_struct_t;
+
+/*! @brief Endpoint initialization structure */
+typedef struct _usb_device_endpoint_init_struct
+{
+ uint16_t maxPacketSize; /*!< Endpoint maximum packet size */
+ uint8_t endpointAddress; /*!< Endpoint address*/
+ uint8_t transferType; /*!< Endpoint transfer type*/
+ uint8_t zlt; /*!< ZLT flag*/
+} usb_device_endpoint_init_struct_t;
+
+/*! @brief Endpoint status structure */
+typedef struct _usb_device_endpoint_status_struct
+{
+ uint8_t endpointAddress; /*!< Endpoint address */
+ uint16_t endpointStatus; /*!< Endpoint status : idle or stalled */
+} usb_device_endpoint_status_struct_t;
+
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U))
+/*! @brief USB DCD charge timing specification structure */
+typedef struct _usb_device_dcd_charging_time
+{
+ uint16_t dcdSeqInitTime; /*!< The dcd sequence init time */
+ uint16_t dcdDbncTime; /*!< The debounce time period on DP signal */
+ uint16_t dcdDpSrcOnTime; /*!< The time period comparator enabled */
+ uint16_t dcdTimeWaitAfterPrD; /*!< The time period between primary and secondary detection */
+ uint8_t dcdTimeDMSrcOn; /*!< The amount of time that the modules enable the Vdm_src */
+} usb_device_dcd_charging_time_t;
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @name USB device APIs
+ * @{
+ */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Initializes the USB device stack.
+ *
+ * This function initializes the USB device module specified by the controllerId.
+ *
+ * @param[in] controllerId The controller ID of the USB IP. See the enumeration #usb_controller_index_t.
+ * @param[in] deviceCallback Function pointer of the device callback.
+ * @param[out] handle It is an out parameter used to return the pointer of the device handle to the caller.
+ *
+ * @retval kStatus_USB_Success The device is initialized successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer.
+ * @retval kStatus_USB_Busy Cannot allocate a device handle.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller according to the controller id.
+ * @retval kStatus_USB_InvalidControllerInterface The controller driver interfaces is invalid. There is an empty
+ * interface entity.
+ * @retval kStatus_USB_Error The macro USB_DEVICE_CONFIG_ENDPOINTS is more than the IP's endpoint number.
+ * Or, the device has been initialized.
+ * Or, the mutex or message queue is created failed.
+ */
+extern usb_status_t USB_DeviceInit(uint8_t controllerId,
+ usb_device_callback_t deviceCallback,
+ usb_device_handle *handle);
+
+/*!
+ * @brief Enables the device functionality.
+ *
+ * The function enables the device functionality, so that the device can be recognized by the host when the device
+ * detects that it has been connected to a host.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The device is run successfully.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid.
+ *
+ */
+extern usb_status_t USB_DeviceRun(usb_device_handle handle);
+
+/*!
+ * @brief Disables the device functionality.
+ *
+ * The function disables the device functionality. After this function called, even if the device is detached to the
+ * host,
+ * it can't work.
+ *
+ * @param[in] handle The device handle received from #USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The device is stopped successfully.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid.
+ */
+extern usb_status_t USB_DeviceStop(usb_device_handle handle);
+
+/*!
+ * @brief De-initializes the device controller.
+ *
+ * The function de-initializes the device controller specified by the handle.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The device is stopped successfully.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid.
+ */
+extern usb_status_t USB_DeviceDeinit(usb_device_handle handle);
+
+/*!
+ * @brief Sends data through a specified endpoint.
+ *
+ * The function is used to send data through a specified endpoint.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ * @param[in] endpointAddress Endpoint index.
+ * @param[in] buffer The memory address to hold the data need to be sent. The function is not reentrant.
+ * @param[in] length The data length need to be sent.
+ *
+ * @retval kStatus_USB_Success The send request is sent successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_Busy Cannot allocate DTDS for current transfer in EHCI driver.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_Error The device is doing reset.
+ *
+ * @note The return value indicates whether the sending request is successful or not. The transfer done is notified by
+ * the
+ * corresponding callback function.
+ * Currently, only one transfer request can be supported for one specific endpoint.
+ * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application
+ * should implement a queue on the application level.
+ * The subsequent transfer can begin only when the previous transfer is done (get notification through the endpoint
+ * callback).
+ */
+extern usb_status_t USB_DeviceSendRequest(usb_device_handle handle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*!
+ * @brief Receives data through a specified endpoint.
+ *
+ * The function is used to receive data through a specified endpoint. The function is not reentrant.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ * @param[in] endpointAddress Endpoint index.
+ * @param[in] buffer The memory address to save the received data.
+ * @param[in] length The data length want to be received.
+ *
+ * @retval kStatus_USB_Success The receive request is sent successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_Busy Cannot allocate DTDS for current transfer in EHCI driver.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_Error The device is doing reset.
+ *
+ * @note The return value indicates whether the receiving request is successful or not. The transfer done is notified by
+ * the
+ * corresponding callback function.
+ * Currently, only one transfer request can be supported for one specific endpoint.
+ * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application
+ * should implement a queue on the application level.
+ * The subsequent transfer can begin only when the previous transfer is done (get notification through the endpoint
+ * callback).
+ */
+extern usb_status_t USB_DeviceRecvRequest(usb_device_handle handle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*!
+ * @brief Cancels the pending transfer in a specified endpoint.
+ *
+ * The function is used to cancel the pending transfer in a specified endpoint.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT.
+ *
+ * @retval kStatus_USB_Success The transfer is cancelled.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer or the controller handle is invalid.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+extern usb_status_t USB_DeviceCancel(usb_device_handle handle, uint8_t endpointAddress);
+
+/*!
+ * @brief Initializes a specified endpoint.
+ *
+ * The function is used to initialize a specified endpoint. The corresponding endpoint callback is also initialized.
+ *
+ * @param[in] handle The device handle received from #USB_DeviceInit.
+ * @param[in] epInit Endpoint initialization structure. See the structure usb_device_endpoint_init_struct_t.
+ * @param[in] epCallback Endpoint callback structure. See the structure
+ * usb_device_endpoint_callback_struct_t.
+ *
+ * @retval kStatus_USB_Success The endpoint is initialized successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The epInit or epCallback is NULL pointer. Or the endpoint number is
+ * more than USB_DEVICE_CONFIG_ENDPOINTS.
+ * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+extern usb_status_t USB_DeviceInitEndpoint(usb_device_handle handle,
+ usb_device_endpoint_init_struct_t *epInit,
+ usb_device_endpoint_callback_struct_t *epCallback);
+
+/*!
+ * @brief Deinitializes a specified endpoint.
+ *
+ * The function is used to deinitializes a specified endpoint.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT.
+ *
+ * @retval kStatus_USB_Success The endpoint is de-initialized successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS.
+ * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+extern usb_status_t USB_DeviceDeinitEndpoint(usb_device_handle handle, uint8_t endpointAddress);
+
+/*!
+ * @brief Stalls a specified endpoint.
+ *
+ * The function is used to stall a specified endpoint.
+ *
+ * @param[in] handle The device handle received from #USB_DeviceInit.
+ * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT.
+ *
+ * @retval kStatus_USB_Success The endpoint is stalled successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+extern usb_status_t USB_DeviceStallEndpoint(usb_device_handle handle, uint8_t endpointAddress);
+
+/*!
+ * @brief Unstalls a specified endpoint.
+ *
+ * The function is used to unstall a specified endpoint.
+ *
+ * @param[in] handle The device handle received from #USB_DeviceInit.
+ * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT.
+ *
+ * @retval kStatus_USB_Success The endpoint is unstalled successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+extern usb_status_t USB_DeviceUnstallEndpoint(usb_device_handle handle, uint8_t endpointAddress);
+
+/*!
+ * @brief Gets the status of the selected item.
+ *
+ * The function is used to get the status of the selected item.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ * @param[in] type The selected item. See the structure #usb_device_status_t.
+ * @param[out] param The parameter type is determined by the selected item.
+ *
+ * @retval kStatus_USB_Success Get status successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The parameter is NULL pointer.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_Error Unsupported type.
+ */
+extern usb_status_t USB_DeviceGetStatus(usb_device_handle handle, usb_device_status_t type, void *param);
+
+/*!
+ * @brief Sets the status of the selected item.
+ *
+ * The function is used to set the status of the selected item.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ * @param[in] type The selected item. See the structure #usb_device_status_t.
+ * @param[in] param The parameter type is determined by the selected item.
+ *
+ * @retval kStatus_USB_Success Set status successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_Error Unsupported type or the parameter is NULL pointer.
+ */
+extern usb_status_t USB_DeviceSetStatus(usb_device_handle handle, usb_device_status_t type, void *param);
+
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U))
+/*!
+ * @brief Initializes the device dcd module.
+ *
+ * The function initializes the device dcd module.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ * @param[in] time_param The time parameter used to config the dcd timing registers.
+ *
+ * @retval kStatus_USB_Success The device is run successfully.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid.
+ *
+ */
+extern usb_status_t USB_DeviceDcdInitModule(usb_device_handle handle, void *time_param);
+
+/*!
+ * @brief De-initializes the device dcd module.
+ *
+ * The function de-initializes the device dcd module specified by the handle.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The device is stopped successfully.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid.
+ */
+extern usb_status_t USB_DeviceDcdDeinitModule(usb_device_handle handle);
+#endif
+/*!
+ * @brief Device task function.
+ *
+ * The function is used to handle the controller message.
+ * This function should not be called in the application directly.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+extern void USB_DeviceTaskFunction(void *deviceHandle);
+
+#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
+/*!
+ * @brief Device KHCI task function.
+ *
+ * The function is used to handle the KHCI controller message.
+ * In the bare metal environment, this function should be called periodically in the main function.
+ * In the RTOS environment, this function should be used as a function entry to create a task.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+#define USB_DeviceKhciTaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle)
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
+/*!
+ * @brief Device EHCI task function.
+ *
+ * The function is used to handle the EHCI controller message.
+ * In the bare metal environment, this function should be called periodically in the main function.
+ * In the RTOS environment, this function should be used as a function entry to create a task.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+#define USB_DeviceEhciTaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle)
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U))
+/*!
+ * @brief Device EHCI DCD ISR function.
+ *
+ * The function is the EHCI DCD interrupt service routine.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+extern void USB_DeviceDcdHSIsrFunction(void *deviceHandle);
+#endif
+#endif
+
+#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \
+ ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)))
+/*!
+ * @brief Device LPC ip3511 controller task function.
+ *
+ * The function is used to handle the LPC ip3511 controller message.
+ * In the bare metal environment, this function should be called periodically in the main function.
+ * In the RTOS environment, this function should be used as a function entry to create a task.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+#define USB_DeviceLpcIp3511TaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle)
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
+/*!
+ * @brief Device KHCI ISR function.
+ *
+ * The function is the KHCI interrupt service routine.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+extern void USB_DeviceKhciIsrFunction(void *deviceHandle);
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U))
+/*!
+ * @brief Device KHCI DCD ISR function.
+ *
+ * The function is the KHCI DCD interrupt service routine.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+extern void USB_DeviceDcdIsrFunction(void *deviceHandle);
+#endif
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
+/*!
+ * @brief Device EHCI ISR function.
+ *
+ * The function is the EHCI interrupt service routine.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+extern void USB_DeviceEhciIsrFunction(void *deviceHandle);
+#endif
+
+#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \
+ ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)))
+/*!
+ * @brief Device LPC USB ISR function.
+ *
+ * The function is the LPC USB interrupt service routine.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+extern void USB_DeviceLpcIp3511IsrFunction(void *deviceHandle);
+#endif
+
+/*!
+ * @brief Gets the device stack version function.
+ *
+ * The function is used to get the device stack version.
+ *
+ * @param[out] version The version structure pointer to keep the device stack version.
+ *
+ */
+extern void USB_DeviceGetVersion(uint32_t *version);
+
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+/*!
+ * @brief Update the hardware tick.
+ *
+ * The function is used to update the hardware tick.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ * @param[in] tick Current hardware tick(uint is ms).
+ *
+ */
+extern usb_status_t USB_DeviceUpdateHwTick(usb_device_handle handle, uint64_t tick);
+#endif
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __USB_DEVICE_H__ */
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _USB_DEVICE_CDC_ACM_H_
+#define _USB_DEVICE_CDC_ACM_H_ 1
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+
+#define USB_DEVICE_CONFIG_CDC_ACM_MAX_INSTANCE (1)
+
+#define USB_DEVICE_CONFIG_CDC_COMM_CLASS_CODE (0x02)
+#define USB_DEVICE_CONFIG_CDC_DATA_CLASS_CODE (0x0A)
+
+/* Class specific request Codes */
+#define USB_DEVICE_CDC_REQUEST_SEND_ENCAPSULATED_COMMAND (0x00)
+#define USB_DEVICE_CDC_REQUEST_GET_ENCAPSULATED_RESPONSE (0x01)
+#define USB_DEVICE_CDC_REQUEST_SET_COMM_FEATURE (0x02)
+#define USB_DEVICE_CDC_REQUEST_GET_COMM_FEATURE (0x03)
+#define USB_DEVICE_CDC_REQUEST_CLEAR_COMM_FEATURE (0x04)
+#define USB_DEVICE_CDC_REQUEST_SET_AUX_LINE_STATE (0x10)
+#define USB_DEVICE_CDC_REQUEST_SET_HOOK_STATE (0x11)
+#define USB_DEVICE_CDC_REQUEST_PULSE_SETUP (0x12)
+#define USB_DEVICE_CDC_REQUEST_SEND_PULSE (0x13)
+#define USB_DEVICE_CDC_REQUEST_SET_PULSE_TIME (0x14)
+#define USB_DEVICE_CDC_REQUEST_RING_AUX_JACK (0x15)
+#define USB_DEVICE_CDC_REQUEST_SET_LINE_CODING (0x20)
+#define USB_DEVICE_CDC_REQUEST_GET_LINE_CODING (0x21)
+#define USB_DEVICE_CDC_REQUEST_SET_CONTROL_LINE_STATE (0x22)
+#define USB_DEVICE_CDC_REQUEST_SEND_BREAK (0x23)
+#define USB_DEVICE_CDC_REQUEST_SET_RINGER_PARAMS (0x30)
+#define USB_DEVICE_CDC_REQUEST_GET_RINGER_PARAMS (0x31)
+#define USB_DEVICE_CDC_REQUEST_SET_OPERATION_PARAM (0x32)
+#define USB_DEVICE_CDC_REQUEST_GET_OPERATION_PARAM (0x33)
+#define USB_DEVICE_CDC_REQUEST_SET_LINE_PARAMS (0x34)
+#define USB_DEVICE_CDC_REQUEST_GET_LINE_PARAMS (0x35)
+#define USB_DEVICE_CDC_REQUEST_DIAL_DIGITS (0x36)
+#define USB_DEVICE_CDC_REQUEST_SET_UNIT_PARAMETER (0x37)
+#define USB_DEVICE_CDC_REQUEST_GET_UNIT_PARAMETER (0x38)
+#define USB_DEVICE_CDC_REQUEST_CLEAR_UNIT_PARAMETER (0x39)
+#define USB_DEVICE_CDC_REQUEST_GET_PROFILE (0x3A)
+#define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_MULTICAST_FILTERS (0x40)
+#define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_POW_PATTER_FILTER (0x41)
+#define USB_DEVICE_CDC_REQUEST_GET_ETHERNET_POW_PATTER_FILTER (0x42)
+#define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_PACKET_FILTER (0x43)
+#define USB_DEVICE_CDC_REQUEST_GET_ETHERNET_STATISTIC (0x44)
+#define USB_DEVICE_CDC_REQUEST_SET_ATM_DATA_FORMAT (0x50)
+#define USB_DEVICE_CDC_REQUEST_GET_ATM_DEVICE_STATISTICS (0x51)
+#define USB_DEVICE_CDC_REQUEST_SET_ATM_DEFAULT_VC (0x52)
+#define USB_DEVICE_CDC_REQUEST_GET_ATM_VC_STATISTICS (0x53)
+#define USB_DEVICE_CDC_REQUEST_MDLM_SPECIFIC_REQUESTS_MASK (0x7F)
+
+#define USB_DEVICE_CDC_REQUEST_GET_ABSTRACT_STATE (0x23)
+#define USB_DEVICE_CDC_REQUEST_GET_COUNTRY_SETTING (0x24)
+#define USB_DEVICE_CDC_REQUEST_SET_ABSTRACT_STATE (0x25)
+#define USB_DEVICE_CDC_REQUEST_SET_COUNTRY_SETTING (0x26)
+/* Class Specific Notification Codes */
+#define USB_DEVICE_CDC_REQUEST_NETWORK_CONNECTION_NOTIF (0x00)
+#define USB_DEVICE_CDC_REQUEST_RESPONSE_AVAIL_NOTIF (0x01)
+#define USB_DEVICE_CDC_REQUEST_AUX_JACK_HOOK_STATE_NOTIF (0x08)
+#define USB_DEVICE_CDC_REQUEST_RING_DETECT_NOTIF (0x09)
+#define USB_DEVICE_CDC_REQUEST_SERIAL_STATE_NOTIF (0x20)
+#define USB_DEVICE_CDC_REQUEST_CALL_STATE_CHANGE_NOTIF (0x28)
+#define USB_DEVICE_CDC_REQUEST_LINE_STATE_CHANGE_NOTIF (0x29)
+#define USB_DEVICE_CDC_REQUEST_CONNECTION_SPEED_CHANGE_NOTIF (0x2A)
+/* Communications Feature Selector Codes */
+#define USB_DEVICE_CDC_FEATURE_ABSTRACT_STATE (0x01)
+#define USB_DEVICE_CDC_FEATURE_COUNTRY_SETTING (0x02)
+/* Control Signal Bitmap Values */
+#define USB_DEVICE_CDC_CONTROL_SIG_BITMAP_CARRIER_ACTIVATION (0x02)
+#define USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE (0x01)
+/* UART State Bitmap Values */
+#define USB_DEVICE_CDC_UART_STATE_RX_CARRIER (0x01)
+#define USB_DEVICE_CDC_UART_STATE_TX_CARRIER (0x02)
+#define USB_DEVICE_CDC_UART_STATE_BREAK (0x04)
+#define USB_DEVICE_CDC_UART_STATE_RING_SIGNAL (0x08)
+#define USB_DEVICE_CDC_UART_STATE_FRAMING (0x10)
+#define USB_DEVICE_CDC_UART_STATE_PARITY (0x20)
+#define USB_DEVICE_CDC_UART_STATE_OVERRUN (0x40)
+
+#endif /* _USB_DEVICE_CDC_ACM_H_ */
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "usb_device_config.h"
+#include "usb.h"
+
+#include "usb_device.h"
+#include "usb_device_dci.h"
+#include "usb_device_ch9.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Standard request callback function typedef.
+ *
+ * This function is used to handle the standard request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+typedef usb_status_t (*usb_standard_request_callback_t)(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+
+/*******************************************************************************
+* Prototypes
+******************************************************************************/
+/*!
+ * @brief Get the setup packet buffer.
+ *
+ * The function is used to get the setup packet buffer to save the setup packet data.
+ *
+ * @param handle The device handle.
+ * @param setupBuffer It is an OUT parameter, return the setup buffer address to the caller.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceGetSetupBuffer(usb_device_handle handle, usb_setup_struct_t **setupBuffer);
+
+/*!
+ * @brief Handle the class request.
+ *
+ * The function is used to handle the class request.
+ *
+ * @param handle The device handle.
+ * @param setup The setup packet buffer address.
+ * @param length It is an OUT parameter, return the data length need to be sent to host.
+ * @param buffer It is an OUT parameter, return the data buffer address.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceProcessClassRequest(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint32_t *length,
+ uint8_t **buffer);
+
+/*!
+ * @brief Get the buffer to save the class specific data sent from host.
+ *
+ * The function is used to get the buffer to save the class specific data sent from host.
+ * The function will be called when the device receives a setup pakcet, and the host needs to send data to the device in
+ * the data stage.
+ *
+ * @param handle The device handle.
+ * @param setup The setup packet buffer address.
+ * @param length Pass the length the host needs to sent.
+ * @param buffer It is an OUT parameter, return the data buffer address to save the host's data.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceGetClassReceiveBuffer(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint32_t *length,
+ uint8_t **buffer);
+
+/* standard request */
+/*!
+ * @brief Get the descritpor.
+ *
+ * The function is used to get the descritpor, including the device descritpor, configuration descriptor, and string
+ * descriptor, etc.
+ *
+ * @param handle The device handle.
+ * @param setup The setup packet buffer address.
+ * @param length It is an OUT parameter, return the data length need to be sent to host.
+ * @param buffer It is an OUT parameter, return the data buffer address.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceGetDescriptor(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint32_t *length,
+ uint8_t **buffer);
+
+/*!
+ * @brief Set the device configuration.
+ *
+ * The function is used to set the device configuration.
+ *
+ * @param handle The device handle.
+ * @param configure The configuration value.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceSetConfigure(usb_device_handle handle, uint8_t configure);
+
+/*!
+ * @brief Get the device configuration.
+ *
+ * The function is used to get the device configuration.
+ *
+ * @param handle The device handle.
+ * @param configure It is an OUT parameter, save the current configuration value.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceGetConfigure(usb_device_handle handle, uint8_t *configure);
+
+/*!
+ * @brief Set an interface alternate setting.
+ *
+ * The function is used to set an interface alternate setting.
+ *
+ * @param handle The device handle.
+ * @param interface The interface index.
+ * @param alternateSetting The new alternate setting value.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceSetInterface(usb_device_handle handle, uint8_t interface, uint8_t alternateSetting);
+
+/*!
+ * @brief Get an interface alternate setting.
+ *
+ * The function is used to get an interface alternate setting.
+ *
+ * @param handle The device handle.
+ * @param interface The interface index.
+ * @param alternateSetting It is an OUT parameter, save the new alternate setting value of the interface.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceGetInterface(usb_device_handle handle, uint8_t interface, uint8_t *alternateSetting);
+
+/*!
+ * @brief Configure a specified endpoint status.
+ *
+ * The function is used to configure a specified endpoint status, idle or halt.
+ *
+ * @param handle The device handle.
+ * @param endpointAddress The endpoint address, the BIT7 is the direction, 0 - USB_OUT, 1 - USB_IN.
+ * @param status The new status of the endpoint, 0 - idle, 1 - halt.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceConfigureEndpointStatus(usb_device_handle handle,
+ uint8_t endpointAddress,
+ uint8_t status);
+
+/*!
+ * @brief Configure the device remote wakeup feature.
+ *
+ * The function is used to configure the device remote wakeup feature, enable or disbale the remote wakeup feature.
+ *
+ * @param handle The device handle.
+ * @param enable The new feature value of the device remote wakeup, 0 - disable, 1 - enable.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceConfigureRemoteWakeup(usb_device_handle handle, uint8_t enable);
+
+static usb_status_t USB_DeviceCh9GetStatus(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+static usb_status_t USB_DeviceCh9SetClearFeature(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+static usb_status_t USB_DeviceCh9SetAddress(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+static usb_status_t USB_DeviceCh9GetDescriptor(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+static usb_status_t USB_DeviceCh9GetConfiguration(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+static usb_status_t USB_DeviceCh9SetConfiguration(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+static usb_status_t USB_DeviceCh9GetInterface(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+static usb_status_t USB_DeviceCh9SetInterface(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+static usb_status_t USB_DeviceCh9SynchFrame(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* The function list to handle the standard request. */
+static const usb_standard_request_callback_t s_UsbDeviceStandardRequest[] = {
+ USB_DeviceCh9GetStatus,
+ USB_DeviceCh9SetClearFeature,
+ (usb_standard_request_callback_t)NULL,
+ USB_DeviceCh9SetClearFeature,
+ (usb_standard_request_callback_t)NULL,
+ USB_DeviceCh9SetAddress,
+ USB_DeviceCh9GetDescriptor,
+ (usb_standard_request_callback_t)NULL, /* USB_DeviceCh9SetDescriptor */
+ USB_DeviceCh9GetConfiguration,
+ USB_DeviceCh9SetConfiguration,
+ USB_DeviceCh9GetInterface,
+ USB_DeviceCh9SetInterface,
+ USB_DeviceCh9SynchFrame,
+};
+
+/*
+ * The internal global variable.
+ * This variable is used in:
+ * get status request
+ * get configuration request
+ * get interface request
+ * set interface request
+ * get sync frame request
+ */
+static uint16_t s_UsbDeviceStandardRx;
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+/*!
+ * @brief Handle get status request.
+ *
+ * This function is used to handle get status request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The requst is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state,
+ * or, the request is unsupported.
+ */
+static usb_status_t USB_DeviceCh9GetStatus(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ usb_status_t error = kStatus_USB_InvalidRequest;
+ uint8_t state;
+
+ USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if ((kUSB_DeviceStateAddress != state) && (kUSB_DeviceStateConfigured != state))
+ {
+ return error;
+ }
+
+ if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_DEVICE)
+ {
+ /* Get the device status */
+ error = USB_DeviceGetStatus(handle, kUSB_DeviceStatusDevice, &s_UsbDeviceStandardRx);
+ s_UsbDeviceStandardRx = s_UsbDeviceStandardRx & USB_GET_STATUS_DEVICE_MASK;
+ s_UsbDeviceStandardRx = USB_SHORT_TO_LITTLE_ENDIAN(s_UsbDeviceStandardRx);
+ /* The device status length must be USB_DEVICE_STATUS_SIZE. */
+ *length = USB_DEVICE_STATUS_SIZE;
+ }
+ else if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_INTERFACE)
+ {
+ /* Get the interface status */
+ error = kStatus_USB_Success;
+ s_UsbDeviceStandardRx = 0U;
+ /* The interface status length must be USB_INTERFACE_STATUS_SIZE. */
+ *length = USB_INTERFACE_STATUS_SIZE;
+ }
+ else if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_ENDPOINT)
+ {
+ /* Get the endpoint status */
+ usb_device_endpoint_status_struct_t endpointStatus;
+ endpointStatus.endpointAddress = (uint8_t)setup->wIndex;
+ endpointStatus.endpointStatus = kUSB_DeviceEndpointStateIdle;
+ error = USB_DeviceGetStatus(handle, kUSB_DeviceStatusEndpoint, &endpointStatus);
+ s_UsbDeviceStandardRx = endpointStatus.endpointStatus & USB_GET_STATUS_ENDPOINT_MASK;
+ s_UsbDeviceStandardRx = USB_SHORT_TO_LITTLE_ENDIAN(s_UsbDeviceStandardRx);
+ /* The endpoint status length must be USB_INTERFACE_STATUS_SIZE. */
+ *length = USB_ENDPOINT_STATUS_SIZE;
+ }
+ else
+ {
+ }
+ *buffer = (uint8_t *)&s_UsbDeviceStandardRx;
+
+ return error;
+}
+
+/*!
+ * @brief Handle set or clear device feature request.
+ *
+ * This function is used to handle set or clear device feature request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The requst is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state,
+ * or, the request is unsupported.
+ */
+static usb_status_t USB_DeviceCh9SetClearFeature(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ usb_status_t error = kStatus_USB_InvalidRequest;
+ uint8_t state;
+ uint8_t isSet = 0U;
+
+ USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if ((kUSB_DeviceStateAddress != state) && (kUSB_DeviceStateConfigured != state))
+ {
+ return error;
+ }
+
+ /* Identify the request is set or clear the feature. */
+ if (USB_REQUEST_STANDARD_SET_FEATURE == setup->bRequest)
+ {
+ isSet = 1U;
+ }
+
+ if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_DEVICE)
+ {
+ /* Set or Clear the device featrue. */
+ if (USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_REMOTE_WAKEUP == setup->wValue)
+ {
+ /* Set or Clear the device remote wakeup featrue. */
+ error = USB_DeviceConfigureRemoteWakeup(handle, isSet);
+ }
+#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U)) && \
+ (defined(USB_DEVICE_CONFIG_EHCI_TEST_MODE) && (USB_DEVICE_CONFIG_EHCI_TEST_MODE > 0U))
+ else if (USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_TEST_MODE == setup->wValue)
+ {
+ state = kUSB_DeviceStateTestMode;
+ error = USB_DeviceSetStatus(classHandle->handle, kUSB_DeviceStatusDeviceState, &state);
+ }
+#endif
+ else
+ {
+ }
+ }
+ else if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_ENDPOINT)
+ {
+ /* Set or Clear the endpoint featrue. */
+ if (USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT == setup->wValue)
+ {
+ if (USB_CONTROL_ENDPOINT == (setup->wIndex & USB_ENDPOINT_NUMBER_MASK))
+ {
+ /* Set or Clear the control endpoint status(halt or not). */
+ if (isSet)
+ {
+ USB_DeviceStallEndpoint(handle, (uint8_t)setup->wIndex);
+ }
+ else
+ {
+ USB_DeviceUnstallEndpoint(handle, (uint8_t)setup->wIndex);
+ }
+ }
+
+ /* Set or Clear the endpoint status featrue. */
+ error = USB_DeviceConfigureEndpointStatus(handle, setup->wIndex, isSet);
+ }
+ else
+ {
+ }
+ }
+ else
+ {
+ }
+
+ return error;
+}
+
+/*!
+ * @brief Handle set address request.
+ *
+ * This function is used to handle set address request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The requst is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state.
+ */
+static usb_status_t USB_DeviceCh9SetAddress(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ usb_status_t error = kStatus_USB_InvalidRequest;
+ uint8_t state;
+
+ USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if ((kUSB_DeviceStateAddressing != state) && (kUSB_DeviceStateAddress != state) &&
+ (kUSB_DeviceStateDefault != state))
+ {
+ return error;
+ }
+
+ if (kUSB_DeviceStateAddressing != state)
+ {
+ /* If the device address is not setting, pass the address and the device state will change to
+ * kUSB_DeviceStateAddressing internally. */
+ state = setup->wValue & 0xFFU;
+ error = USB_DeviceSetStatus(handle, kUSB_DeviceStatusAddress, &state);
+ }
+ else
+ {
+ /* If the device address is setting, set device address and the address will be write into the controller
+ * internally. */
+ error = USB_DeviceSetStatus(handle, kUSB_DeviceStatusAddress, NULL);
+ /* And then change the device state to kUSB_DeviceStateAddress. */
+ if (kStatus_USB_Success == error)
+ {
+ state = kUSB_DeviceStateAddress;
+ error = USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
+ }
+ }
+
+ return error;
+}
+
+/*!
+ * @brief Handle get descriptor request.
+ *
+ * This function is used to handle get descriptor request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The requst is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state,
+ * or, the request is unsupported.
+ */
+static usb_status_t USB_DeviceCh9GetDescriptor(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ uint8_t state;
+
+ USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if ((kUSB_DeviceStateAddress != state) && (kUSB_DeviceStateConfigured != state) &&
+ (kUSB_DeviceStateDefault != state))
+ {
+ return kStatus_USB_InvalidRequest;
+ }
+
+ return USB_DeviceGetDescriptor(handle, setup, length, buffer);
+}
+
+/*!
+ * @brief Handle get current configuration request.
+ *
+ * This function is used to handle get current configuration request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The requst is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state,
+ * or, the request is unsupported.
+ */
+static usb_status_t USB_DeviceCh9GetConfiguration(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ uint8_t state;
+
+ USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if ((kUSB_DeviceStateAddress != state) && ((kUSB_DeviceStateConfigured != state)))
+ {
+ return kStatus_USB_InvalidRequest;
+ }
+
+ *length = USB_CONFIGURE_SIZE;
+ *buffer = (uint8_t *)&s_UsbDeviceStandardRx;
+ return USB_DeviceGetConfigure(handle, (uint8_t *)&s_UsbDeviceStandardRx);
+}
+
+/*!
+ * @brief Handle set current configuration request.
+ *
+ * This function is used to handle set current configuration request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The requst is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state,
+ * or, the request is unsupported.
+ */
+static usb_status_t USB_DeviceCh9SetConfiguration(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ uint8_t state;
+
+ USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if ((kUSB_DeviceStateAddress != state) && (kUSB_DeviceStateConfigured != state))
+ {
+ return kStatus_USB_InvalidRequest;
+ }
+
+ /* The device state is changed to kUSB_DeviceStateConfigured */
+ state = kUSB_DeviceStateConfigured;
+ USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
+ if (!setup->wValue)
+ {
+ /* If the new configuration is zero, the device state is changed to kUSB_DeviceStateAddress */
+ state = kUSB_DeviceStateAddress;
+ USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
+ }
+
+ return USB_DeviceSetConfigure(handle, setup->wValue);
+}
+
+/*!
+ * @brief Handle get the alternate setting of a interface request.
+ *
+ * This function is used to handle get the alternate setting of a interface request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The requst is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state,
+ * or, the request is unsupported.
+ */
+static usb_status_t USB_DeviceCh9GetInterface(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ usb_status_t error = kStatus_USB_InvalidRequest;
+ uint8_t state;
+
+ USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if (state != kUSB_DeviceStateConfigured)
+ {
+ return error;
+ }
+ *length = USB_INTERFACE_SIZE;
+ *buffer = (uint8_t *)&s_UsbDeviceStandardRx;
+
+ return USB_DeviceGetInterface(handle, setup->wIndex & 0xFFU, (uint8_t *)&s_UsbDeviceStandardRx);
+}
+
+/*!
+ * @brief Handle set the alternate setting of a interface request.
+ *
+ * This function is used to handle set the alternate setting of a interface request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The requst is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state,
+ * or, the request is unsupported.
+ */
+static usb_status_t USB_DeviceCh9SetInterface(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ uint8_t state;
+
+ USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if (state != kUSB_DeviceStateConfigured)
+ {
+ return kStatus_USB_InvalidRequest;
+ }
+
+ return USB_DeviceSetInterface(handle, (setup->wIndex & 0xFFU), (setup->wValue & 0xFFU));
+}
+
+/*!
+ * @brief Handle get sync frame request.
+ *
+ * This function is used to handle get sync frame request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The requst is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state,
+ * or, the request is unsupported.
+ */
+static usb_status_t USB_DeviceCh9SynchFrame(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ usb_status_t error = kStatus_USB_InvalidRequest;
+ uint8_t state;
+
+ USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if (state != kUSB_DeviceStateConfigured)
+ {
+ return error;
+ }
+
+ s_UsbDeviceStandardRx = setup->wIndex;
+ /* Get the sync frame value */
+ error = USB_DeviceGetStatus(handle, kUSB_DeviceStatusSynchFrame, &s_UsbDeviceStandardRx);
+ *buffer = (uint8_t *)&s_UsbDeviceStandardRx;
+ *length = sizeof(s_UsbDeviceStandardRx);
+
+ return error;
+}
+
+/*!
+ * @brief Send the reponse to the host.
+ *
+ * This function is used to send the reponse to the host.
+ *
+ * There are two cases this function will be called.
+ * Case one when a setup packet is received in control endpoint callback function:
+ * 1. If there is not data phase in the setup transfer, the function will prime an IN transfer with the data
+ * length is zero for status phase.
+ * 2. If there is an IN data phase, the function will prime an OUT transfer with the actual length to need to
+ * send for data phase. And then prime an IN transfer with the data length is zero for status phase.
+ * 3. If there is an OUT data phase, the function will prime an IN transfer with the actual length to want to
+ * receive for data phase.
+ *
+ * Case two when is not a setup packet received in control endpoint callback function:
+ * 1. The function will prime an IN transfer with data length is zero for status phase.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param error The error code returned from the standard request fucntion.
+ * @param stage The stage of the control transfer.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceControlCallbackFeedback(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ usb_status_t error,
+ usb_device_control_read_write_sequence_t stage,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ usb_status_t errorCode = kStatus_USB_Error;
+ uint8_t direction = USB_IN;
+
+ if (kStatus_USB_InvalidRequest == error)
+ {
+ /* Stall the control pipe when the request is unsupported. */
+ if ((!((setup->bmRequestType & USB_REQUEST_TYPE_TYPE_MASK) == USB_REQUEST_TYPE_TYPE_STANDARD)) &&
+ ((setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_OUT) && (setup->wLength) &&
+ (kUSB_DeviceControlPipeSetupStage == stage))
+ {
+ direction = USB_OUT;
+ }
+ errorCode = USB_DeviceStallEndpoint(
+ handle,
+ (USB_CONTROL_ENDPOINT) | (uint8_t)((uint32_t)direction << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT));
+ }
+ else
+ {
+ if (*length > setup->wLength)
+ {
+ *length = setup->wLength;
+ }
+ errorCode = USB_DeviceSendRequest(handle, (USB_CONTROL_ENDPOINT), *buffer, *length);
+
+ if ((kStatus_USB_Success == errorCode) &&
+ (USB_REQUEST_TYPE_DIR_IN == (setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK)))
+ {
+ errorCode = USB_DeviceRecvRequest(handle, (USB_CONTROL_ENDPOINT), (uint8_t *)NULL, 0U);
+ }
+ }
+ return errorCode;
+}
+
+/*!
+ * @brief Control endpoint callback function.
+ *
+ * This callback function is used to notify uplayer the tranfser result of a transfer.
+ * This callback pointer is passed when a sepcified endpoint initialied by calling API USB_DeviceInitEndpoint.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The result of a transfer, includes transfer buffer, transfer length and whether is in setup
+ * phase for control pipe.
+ * @param callbackParam The paramter for this callback. It is same with
+ * usb_device_endpoint_callback_struct_t::callbackParam.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceControlCallback(usb_device_handle handle,
+ usb_device_endpoint_callback_message_struct_t *message,
+ void *callbackParam)
+{
+ usb_setup_struct_t *deviceSetup;
+ uint8_t *setupOutBuffer;
+ uint8_t *buffer = (uint8_t *)NULL;
+ uint32_t length = 0U;
+ usb_status_t error = kStatus_USB_InvalidRequest;
+ uint8_t state;
+
+ if (USB_UNINITIALIZED_VAL_32 == message->length)
+ {
+ return error;
+ }
+
+ USB_DeviceGetSetupBuffer(handle, &deviceSetup);
+ USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if (message->isSetup)
+ {
+ if ((USB_SETUP_PACKET_SIZE != message->length) || (NULL == message->buffer))
+ {
+ /* If a invalid setup is received, the control pipes should be de-init and init again.
+ * Due to the IP can not meet this require, it is revesed for feature.
+ */
+ /*
+ USB_DeviceDeinitEndpoint(handle,
+ USB_CONTROL_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT));
+ USB_DeviceDeinitEndpoint(handle,
+ USB_CONTROL_ENDPOINT | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT));
+ USB_DeviceControlPipeInit(handle);
+ */
+ return error;
+ }
+ /* Receive a setup request */
+ usb_setup_struct_t *setup = (usb_setup_struct_t *)(message->buffer);
+ /* Copy the setup packet to the application buffer */
+ deviceSetup->wValue = USB_SHORT_FROM_LITTLE_ENDIAN(setup->wValue);
+ deviceSetup->wIndex = USB_SHORT_FROM_LITTLE_ENDIAN(setup->wIndex);
+ deviceSetup->wLength = USB_SHORT_FROM_LITTLE_ENDIAN(setup->wLength);
+ deviceSetup->bRequest = setup->bRequest;
+ deviceSetup->bmRequestType = setup->bmRequestType;
+
+ if ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_MASK) == USB_REQUEST_TYPE_TYPE_STANDARD)
+ {
+ /* Handle the standard request */
+ if (s_UsbDeviceStandardRequest[deviceSetup->bRequest] != (usb_standard_request_callback_t)NULL)
+ {
+ error = s_UsbDeviceStandardRequest[deviceSetup->bRequest](handle, deviceSetup, &buffer, &length);
+ }
+ }
+ else
+ {
+ if ((deviceSetup->wLength) &&
+ ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_OUT))
+ {
+ /* Class or vendor request with the OUT data phase. */
+ if ((deviceSetup->wLength) &&
+ ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_CLASS) == USB_REQUEST_TYPE_TYPE_CLASS))
+ {
+ /* Get data buffer to receive the data from the host. */
+ length = deviceSetup->wLength;
+ error = USB_DeviceGetClassReceiveBuffer(handle, deviceSetup, &length, &setupOutBuffer);
+ length = 0U;
+ }
+ else
+ {
+ }
+ if (kStatus_USB_Success == error)
+ {
+ /* Prime an OUT transfer */
+ error = USB_DeviceRecvRequest(handle, USB_CONTROL_ENDPOINT, setupOutBuffer, deviceSetup->wLength);
+ return error;
+ }
+ }
+ else
+ {
+ /* Class or vendor request with the IN data phase. */
+ if (((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_CLASS) == USB_REQUEST_TYPE_TYPE_CLASS))
+ {
+ /* Get data buffer to response the host. */
+ error = USB_DeviceProcessClassRequest(handle, deviceSetup, &length, &buffer);
+ }
+ else
+ {
+ }
+ }
+ }
+ /* Send the reponse to the host. */
+ error = USB_DeviceControlCallbackFeedback(handle, deviceSetup, error, kUSB_DeviceControlPipeSetupStage, &buffer,
+ &length);
+ }
+ else if (kUSB_DeviceStateAddressing == state)
+ {
+ /* Set the device address to controller. */
+ error = s_UsbDeviceStandardRequest[deviceSetup->bRequest](handle, deviceSetup, &buffer, &length);
+ }
+#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U)) && \
+ (defined(USB_DEVICE_CONFIG_EHCI_TEST_MODE) && (USB_DEVICE_CONFIG_EHCI_TEST_MODE > 0U))
+ else if (kUSB_DeviceStateTestMode == state)
+ {
+ uint8_t portTestControl = (uint8_t)(deviceSetup->wIndex >> 8);
+ /* Set the controller.into test mode. */
+ error = USB_DeviceSetStatus(handle, kUSB_DeviceStatusTestMode, &portTestControl);
+ }
+#endif
+ else if ((message->length) && (deviceSetup->wLength) &&
+ ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_OUT))
+ {
+ if (((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_CLASS) == USB_REQUEST_TYPE_TYPE_CLASS))
+ {
+ /* Data received in OUT phase, and notify the class driver. */
+ error = USB_DeviceProcessClassRequest(handle, deviceSetup, &message->length, &message->buffer);
+ }
+ else
+ {
+ }
+ /* Send the reponse to the host. */
+ error = USB_DeviceControlCallbackFeedback(handle, deviceSetup, error, kUSB_DeviceControlPipeDataStage, &buffer,
+ &length);
+ }
+ else
+ {
+ }
+ return error;
+}
+
+/*!
+ * @brief Control endpoint initialization function.
+ *
+ * This callback function is used to initialize the control pipes.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param param The up layer handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceControlPipeInit(usb_device_handle handle)
+{
+ usb_device_endpoint_init_struct_t epInitStruct;
+ usb_device_endpoint_callback_struct_t endpointCallback;
+ usb_status_t error;
+
+ endpointCallback.callbackFn = USB_DeviceControlCallback;
+ endpointCallback.callbackParam = handle;
+
+ epInitStruct.zlt = 1U;
+ epInitStruct.transferType = USB_ENDPOINT_CONTROL;
+ epInitStruct.endpointAddress = USB_CONTROL_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT);
+ epInitStruct.maxPacketSize = USB_CONTROL_MAX_PACKET_SIZE;
+ /* Initialize the control IN pipe */
+ error = USB_DeviceInitEndpoint(handle, &epInitStruct, &endpointCallback);
+
+ if (kStatus_USB_Success != error)
+ {
+ return error;
+ }
+ epInitStruct.endpointAddress = USB_CONTROL_ENDPOINT | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT);
+ /* Initialize the control OUT pipe */
+ error = USB_DeviceInitEndpoint(handle, &epInitStruct, &endpointCallback);
+
+ if (kStatus_USB_Success != error)
+ {
+ USB_DeviceDeinitEndpoint(handle,
+ USB_CONTROL_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT));
+ return error;
+ }
+
+ return kStatus_USB_Success;
+}
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __USB_DEVICE_CH9_H__
+#define __USB_DEVICE_CH9_H__
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*!
+ * @addtogroup usb_device_ch9
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Defines USB device status size when the host request to get device status */
+#define USB_DEVICE_STATUS_SIZE (0x02U)
+
+/*! @brief Defines USB device interface status size when the host request to get interface status */
+#define USB_INTERFACE_STATUS_SIZE (0x02U)
+
+/*! @brief Defines USB device endpoint status size when the host request to get endpoint status */
+#define USB_ENDPOINT_STATUS_SIZE (0x02U)
+
+/*! @brief Defines USB device configuration size when the host request to get current configuration */
+#define USB_CONFIGURE_SIZE (0X01U)
+
+/*! @brief Defines USB device interface alternate setting size when the host request to get interface alternate setting
+ */
+#define USB_INTERFACE_SIZE (0X01U)
+
+/*! @brief Defines USB device status mask */
+#define USB_GET_STATUS_DEVICE_MASK (0x03U)
+
+/*! @brief Defines USB device interface status mask */
+#define USB_GET_STATUS_INTERFACE_MASK (0x03U)
+
+/*! @brief Defines USB device endpoint status mask */
+#define USB_GET_STATUS_ENDPOINT_MASK (0x03U)
+
+/*! @brief Control read and write sequence */
+typedef enum _usb_device_control_read_write_sequence
+{
+ kUSB_DeviceControlPipeSetupStage = 0U, /*!< Setup stage */
+ kUSB_DeviceControlPipeDataStage, /*!< Data stage */
+ kUSB_DeviceControlPipeStatusStage, /*!< status stage */
+} usb_device_control_read_write_sequence_t;
+
+/*******************************************************************************
+* API
+******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Initialize the control pipes.
+ *
+ * The function is used to initialize the control pipes. This function should be called when event
+ * kUSB_DeviceEventBusReset is received.
+ *
+ * @param handle The device handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceControlPipeInit(usb_device_handle handle);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __USB_DEVICE_CH9_H__ */
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016 - 2018 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _USB_DEVICE_CONFIG_H_
+#define _USB_DEVICE_CONFIG_H_
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*!
+ * @name Hardware instance define
+ * @{
+ */
+
+/*! @brief KHCI instance count */
+#define USB_DEVICE_CONFIG_KHCI (1U)
+
+/*! @brief EHCI instance count */
+#define USB_DEVICE_CONFIG_EHCI (0U)
+
+/*! @brief LPC USB IP3511 FS instance count */
+#define USB_DEVICE_CONFIG_LPCIP3511FS (0U)
+
+/*! @brief LPC USB IP3511 HS instance count */
+#define USB_DEVICE_CONFIG_LPCIP3511HS (0U)
+
+/*! @brief Device instance count, the sum of KHCI and EHCI instance counts*/
+#define USB_DEVICE_CONFIG_NUM \
+ (USB_DEVICE_CONFIG_KHCI + USB_DEVICE_CONFIG_EHCI + USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS)
+
+/* @} */
+
+/*!
+ * @addtogroup usb_device_configuration
+ * @{
+ */
+
+/*!
+ * @name class instance define
+ * @{
+ */
+
+/*! @brief HID instance count */
+#define USB_DEVICE_CONFIG_HID (0U)
+
+/*! @brief CDC ACM instance count */
+#define USB_DEVICE_CONFIG_CDC_ACM (1U)
+
+/*! @brief MSC instance count */
+#define USB_DEVICE_CONFIG_MSC (0U)
+
+/*! @brief Audio instance count */
+#define USB_DEVICE_CONFIG_AUDIO (0U)
+
+/*! @brief PHDC instance count */
+#define USB_DEVICE_CONFIG_PHDC (0U)
+
+/*! @brief Video instance count */
+#define USB_DEVICE_CONFIG_VIDEO (0U)
+
+/*! @brief CCID instance count */
+#define USB_DEVICE_CONFIG_CCID (0U)
+
+/*! @brief Printer instance count */
+#define USB_DEVICE_CONFIG_PRINTER (0U)
+
+/*! @brief DFU instance count */
+#define USB_DEVICE_CONFIG_DFU (0U)
+
+/* @} */
+
+/*! @brief Whether device is self power. 1U supported, 0U not supported */
+#define USB_DEVICE_CONFIG_SELF_POWER (1U)
+
+/*! @brief How many endpoints are supported in the stack. */
+#define USB_DEVICE_CONFIG_ENDPOINTS (4U)
+
+/*! @brief Whether the device task is enabled. */
+#define USB_DEVICE_CONFIG_USE_TASK (0U)
+
+/*! @brief How many the notification message are supported when the device task is enabled. */
+#define USB_DEVICE_CONFIG_MAX_MESSAGES (8U)
+
+/*! @brief Whether test mode enabled. */
+#define USB_DEVICE_CONFIG_USB20_TEST_MODE (0U)
+
+/*! @brief Whether device CV test is enabled. */
+#define USB_DEVICE_CONFIG_CV_TEST (0U)
+
+/*! @brief Whether device compliance test is enabled. If the macro is enabled,
+ the test mode and CV test macroes will be set.*/
+#define USB_DEVICE_CONFIG_COMPLIANCE_TEST (0U)
+
+#if ((defined(USB_DEVICE_CONFIG_COMPLIANCE_TEST)) && (USB_DEVICE_CONFIG_COMPLIANCE_TEST > 0U))
+
+/*! @brief Undefine the marco USB_DEVICE_CONFIG_USB20_TEST_MODE. */
+#undef USB_DEVICE_CONFIG_USB20_TEST_MODE
+/*! @brief Undefine the marco USB_DEVICE_CONFIG_CV_TEST. */
+#undef USB_DEVICE_CONFIG_CV_TEST
+
+/*! @brief enable the test mode. */
+#define USB_DEVICE_CONFIG_USB20_TEST_MODE (1U)
+
+/*! @brief enable the CV test */
+#define USB_DEVICE_CONFIG_CV_TEST (1U)
+
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
+
+/*! @brief The MAX buffer length for the KHCI DMA workaround.*/
+#define USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH (64U)
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
+/*! @brief How many the DTD are supported. */
+#define USB_DEVICE_CONFIG_EHCI_MAX_DTD (16U)
+
+/*! @brief Whether the EHCI ID pin detect feature enabled. */
+#define USB_DEVICE_CONFIG_EHCI_ID_PIN_DETECT (0U)
+#endif
+
+/*! @brief Whether the keep alive feature enabled. */
+#define USB_DEVICE_CONFIG_KEEP_ALIVE_MODE (0U)
+
+/*! @brief Whether the transfer buffer is cache-enabled or not. */
+#ifndef USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE
+#define USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE (0U)
+#endif
+/*! @brief Whether the low power mode is enabled or not. */
+#define USB_DEVICE_CONFIG_LOW_POWER_MODE (0U)
+
+#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+/*! @brief Whether device remote wakeup supported. 1U supported, 0U not supported */
+#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U)
+
+/*! @brief Whether LPM is supported. 1U supported, 0U not supported */
+#define USB_DEVICE_CONFIG_LPM_L1 (0U)
+#else
+/*! @brief The device remote wakeup is unsupported. */
+#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U)
+#endif
+
+/*! @brief Whether the device detached feature is enabled or not. */
+#define USB_DEVICE_CONFIG_DETACH_ENABLE (0U)
+
+/*! @brief Whether handle the USB bus error. */
+#define USB_DEVICE_CONFIG_ERROR_HANDLING (0U)
+
+/* @} */
+
+#endif /* _USB_DEVICE_CONFIG_H_ */
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 - 2017 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "usb_device_config.h"
+#include "usb.h"
+
+#include "usb_device.h"
+#include "usb_device_dci.h"
+
+#include "fsl_device_registers.h"
+
+#if ((defined(USB_DEVICE_CONFIG_NUM)) && (USB_DEVICE_CONFIG_NUM > 0U))
+
+#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
+#include "usb_device_khci.h"
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
+#include "usb_device_ehci.h"
+#endif
+
+#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \
+ ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)))
+#include "usb_device_lpcip3511.h"
+#endif
+
+#include "usb_device_ch9.h"
+#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
+#include "fsl_cache.h"
+#endif
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static usb_status_t USB_DeviceAllocateHandle(uint8_t controllerId, usb_device_struct_t **handle);
+static usb_status_t USB_DeviceFreeHandle(usb_device_struct_t *handle);
+static usb_status_t USB_DeviceGetControllerInterface(
+ uint8_t controllerId, const usb_device_controller_interface_struct_t **controllerInterface);
+static usb_status_t USB_DeviceTransfer(usb_device_handle handle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length);
+static usb_status_t USB_DeviceControl(usb_device_handle handle, usb_device_control_type_t type, void *param);
+static usb_status_t USB_DeviceResetNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message);
+#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+static usb_status_t USB_DeviceSuspendNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message);
+static usb_status_t USB_DeviceResumeNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message);
+#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U))
+static usb_status_t USB_DeviceSleepNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message);
+
+#endif
+#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */
+#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U))
+static usb_status_t USB_DeviceDetachNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message);
+static usb_status_t USB_DeviceAttachNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message);
+#endif
+static usb_status_t USB_DeviceNotification(usb_device_struct_t *handle, usb_device_callback_message_struct_t *message);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+USB_GLOBAL static usb_device_struct_t s_UsbDevice[USB_DEVICE_CONFIG_NUM];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Allocate a device handle.
+ *
+ * This function allocates a device handle.
+ *
+ * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t.
+ * @param handle It is out parameter, is used to return pointer of the device handle to the caller.
+ *
+ * @retval kStatus_USB_Success Get a device handle successfully.
+ * @retval kStatus_USB_Busy Cannot allocate a device handle.
+ * @retval kStatus_USB_Error The device has been initialized.
+ */
+static usb_status_t USB_DeviceAllocateHandle(uint8_t controllerId, usb_device_struct_t **handle)
+{
+ uint32_t count;
+ USB_OSA_SR_ALLOC();
+
+ USB_OSA_ENTER_CRITICAL();
+ /* Check the controller is initialized or not. */
+ for (count = 0U; count < USB_DEVICE_CONFIG_NUM; count++)
+ {
+ if ((NULL != s_UsbDevice[count].controllerHandle) && (controllerId == s_UsbDevice[count].controllerId))
+ {
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_Error;
+ }
+ }
+ /* Get a free device handle. */
+ for (count = 0U; count < USB_DEVICE_CONFIG_NUM; count++)
+ {
+ if (NULL == s_UsbDevice[count].controllerHandle)
+ {
+ s_UsbDevice[count].controllerId = controllerId;
+ *handle = &s_UsbDevice[count];
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_Success;
+ }
+ }
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_Busy;
+}
+
+/*!
+ * @brief Free a device handle.
+ *
+ * This function frees a device handle.
+ *
+ * @param handle The device handle.
+ *
+ * @retval kStatus_USB_Success Free device handle successfully.
+ */
+static usb_status_t USB_DeviceFreeHandle(usb_device_struct_t *handle)
+{
+ USB_OSA_SR_ALLOC();
+
+ USB_OSA_ENTER_CRITICAL();
+ handle->controllerHandle = NULL;
+ handle->controllerId = 0U;
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_Success;
+}
+
+#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
+/* KHCI device driver interface */
+static const usb_device_controller_interface_struct_t s_UsbDeviceKhciInterface = {
+ USB_DeviceKhciInit, USB_DeviceKhciDeinit, USB_DeviceKhciSend,
+ USB_DeviceKhciRecv, USB_DeviceKhciCancel, USB_DeviceKhciControl};
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
+/* EHCI device driver interface */
+static const usb_device_controller_interface_struct_t s_UsbDeviceEhciInterface = {
+ USB_DeviceEhciInit, USB_DeviceEhciDeinit, USB_DeviceEhciSend,
+ USB_DeviceEhciRecv, USB_DeviceEhciCancel, USB_DeviceEhciControl};
+#endif
+
+#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \
+ ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)))
+/* EHCI device driver interface */
+static const usb_device_controller_interface_struct_t s_UsbDeviceLpc3511IpInterface = {
+ USB_DeviceLpc3511IpInit, USB_DeviceLpc3511IpDeinit, USB_DeviceLpc3511IpSend,
+ USB_DeviceLpc3511IpRecv, USB_DeviceLpc3511IpCancel, USB_DeviceLpc3511IpControl};
+#endif
+
+/*!
+ * @brief Get the controller interface handle.
+ *
+ * This function is used to get the controller interface handle.
+ *
+ * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t.
+ * @param controllerInterface It is out parameter, is used to return pointer of the device controller handle to the
+ * caller.
+ *
+ * @retval kStatus_USB_Success Get a device handle successfully.
+ * @retval kStatus_USB_ControllerNotFound The controller id is invalided.
+ */
+static usb_status_t USB_DeviceGetControllerInterface(
+ uint8_t controllerId, const usb_device_controller_interface_struct_t **controllerInterface)
+{
+ usb_status_t error = kStatus_USB_ControllerNotFound;
+ switch (controllerId)
+ {
+#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
+ /* Get the KHCI controller driver interface */
+ case kUSB_ControllerKhci0:
+ case kUSB_ControllerKhci1:
+ *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceKhciInterface;
+ error = kStatus_USB_Success;
+ break;
+#endif
+#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
+ /* Get the EHCI controller driver interface */
+ case kUSB_ControllerEhci0:
+ case kUSB_ControllerEhci1:
+ error = kStatus_USB_Success;
+ *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceEhciInterface;
+ break;
+#endif
+#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \
+ ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)))
+ /* Get the EHCI controller driver interface */
+ case kUSB_ControllerLpcIp3511Fs0:
+ case kUSB_ControllerLpcIp3511Fs1:
+ case kUSB_ControllerLpcIp3511Hs0:
+ case kUSB_ControllerLpcIp3511Hs1:
+ error = kStatus_USB_Success;
+ *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceLpc3511IpInterface;
+ break;
+#endif
+ default:
+ break;
+ }
+ return error;
+}
+
+/*!
+ * @brief Start a new transfer.
+ *
+ * This function is used to start a new transfer.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param endpointAddress Endpoint address. Bit7 is direction, 0U - USB_OUT, 1U - USB_IN.
+ * @param buffer The memory address to be transferred, or the memory address to hold the data need to be
+ * sent.
+ * @param length The length of the data.
+ *
+ * @retval kStatus_USB_Success Get a device handle successfully.
+ * @retval kStatus_USB_InvalidHandle The device handle is invalided.
+ * @retval kStatus_USB_ControllerNotFound The controller interface is not found.
+ * @retval kStatus_USB_Error The device is doing reset.
+ */
+static usb_status_t USB_DeviceTransfer(usb_device_handle handle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle;
+ usb_status_t error = kStatus_USB_Error;
+ uint8_t endpoint = endpointAddress & USB_ENDPOINT_NUMBER_MASK;
+ uint8_t direction = (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >>
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT;
+ USB_OSA_SR_ALLOC();
+
+ if (NULL == deviceHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+ if (NULL != deviceHandle->controllerInterface)
+ {
+ if (deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy)
+ {
+ return kStatus_USB_Busy;
+ }
+ USB_OSA_ENTER_CRITICAL();
+ deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 1U;
+ USB_OSA_EXIT_CRITICAL();
+ if (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK)
+ {
+#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
+ if (length)
+ {
+ DCACHE_CleanByRange((uint32_t)buffer, length);
+ }
+#endif
+ /* Call the controller send interface, the callbackFn is initialized in
+ USB_DeviceGetControllerInterface */
+ error = deviceHandle->controllerInterface->deviceSend(deviceHandle->controllerHandle, endpointAddress,
+ buffer, length);
+ }
+ else
+ {
+#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
+ if (length)
+ {
+ DCACHE_CleanInvalidateByRange((uint32_t)buffer, length);
+ }
+#endif
+ /* Call the controller receive interface, the callbackFn is initialized in
+ USB_DeviceGetControllerInterface */
+ error = deviceHandle->controllerInterface->deviceRecv(deviceHandle->controllerHandle, endpointAddress,
+ buffer, length);
+ }
+ if (kStatus_USB_Success != error)
+ {
+ USB_OSA_ENTER_CRITICAL();
+ deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U;
+ USB_OSA_EXIT_CRITICAL();
+ }
+ }
+ else
+ {
+ error = kStatus_USB_ControllerNotFound;
+ }
+ return error;
+}
+
+/*!
+ * @brief Control the status of the selected item.
+ *
+ * This function is used to control the status of the selected item..
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param type The control type, please refer to the enumeration usb_device_control_type_t.
+ * @param param The param type is determined by the selected item.
+ *
+ * @retval kStatus_USB_Success Get a device handle successfully.
+ * @retval kStatus_USB_InvalidHandle The device handle is invalided.
+ * @retval kStatus_USB_ControllerNotFound The controller interface is not found.
+ * @retval kStatus_USB_Error Unsupport type.
+ * Or, the param is NULL pointer.
+ */
+static usb_status_t USB_DeviceControl(usb_device_handle handle, usb_device_control_type_t type, void *param)
+{
+ usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle;
+ usb_status_t error = kStatus_USB_Error;
+
+ if (NULL == deviceHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+ if (NULL != deviceHandle->controllerInterface)
+ {
+ /* Call the controller control interface. the controllerInterface is initialized in
+ USB_DeviceGetControllerInterface */
+ error = deviceHandle->controllerInterface->deviceControl(deviceHandle->controllerHandle, type, param);
+ }
+ else
+ {
+ error = kStatus_USB_ControllerNotFound;
+ }
+ return error;
+}
+
+/*!
+ * @brief Handle the reset notification.
+ *
+ * This function is used to handle the reset notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @retval kStatus_USB_Success Get a device handle successfully.
+ */
+static usb_status_t USB_DeviceResetNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+ USB_OSA_SR_ALLOC();
+#endif
+
+ handle->isResetting = 1U;
+
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+ /* Clear remote wakeup feature */
+ handle->remotewakeup = 0U;
+#endif
+
+#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+ USB_OSA_ENTER_CRITICAL();
+ handle->epCallbackDirectly = 1;
+ USB_OSA_EXIT_CRITICAL();
+#endif
+ /* Set the controller to default status. */
+ USB_DeviceControl(handle, kUSB_DeviceControlSetDefaultStatus, NULL);
+#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+ USB_OSA_ENTER_CRITICAL();
+ handle->epCallbackDirectly = 0;
+ USB_OSA_EXIT_CRITICAL();
+#endif
+
+ handle->state = kUSB_DeviceStateDefault;
+ handle->deviceAddress = 0U;
+
+ for (uint32_t count = 0U; count < (USB_DEVICE_CONFIG_ENDPOINTS * 2U); count++)
+ {
+ handle->epCallback[count].callbackFn = (usb_device_endpoint_callback_t)NULL;
+ handle->epCallback[count].callbackParam = NULL;
+ handle->epCallback[count].isBusy = 0U;
+ }
+
+ /* Call device callback to notify the application that the USB bus reset signal detected.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ handle->deviceCallback(handle, kUSB_DeviceEventBusReset, NULL);
+
+ handle->isResetting = 0U;
+ return kStatus_USB_Success;
+}
+
+#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+/*!
+ * @brief Handle the suspend notification.
+ *
+ * This function is used to handle the suspend notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceSuspendNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the USB bus suspend signal detected.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ return handle->deviceCallback(handle, kUSB_DeviceEventSuspend, NULL);
+}
+
+/*!
+ * @brief Handle the resume notification.
+ *
+ * This function is used to handle the resume notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceResumeNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the USB bus resume signal detected.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ return handle->deviceCallback(handle, kUSB_DeviceEventResume, NULL);
+}
+#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U))
+/*!
+ * @brief Handle the suspend notification.
+ *
+ * This function is used to handle the suspend notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceSleepNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the USB bus suspend signal detected.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ return handle->deviceCallback(handle, kUSB_DeviceEventSleeped, NULL);
+}
+#endif
+/*!
+ * @brief Handle the remotewakeup notification.
+ *
+ * This function is used to handle the remotewakeup notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param flag The buffer pointer to store remotewakeup flag.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceGetRemoteWakeUp(usb_device_struct_t *handle, uint8_t **flag)
+{
+ /* Call device callback to notify the application that the USB bus suspend signal detected. */
+ return USB_DeviceControl(handle, kUSB_DeviceControlGetRemoteWakeUp, flag);
+}
+
+#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */
+
+#if (defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U))
+usb_status_t USB_DeviceErrorNotification(usb_device_struct_t *handle, usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the USB bus error signal detected.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ return handle->deviceCallback(handle, kUSB_DeviceEventError, NULL);
+}
+#endif /* USB_DEVICE_CONFIG_ERROR_HANDLING */
+
+#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U))
+/*!
+ * @brief Handle the detach notification.
+ *
+ * This function is used to handle the detach notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceDetachNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the device is disconnected from a host.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ return handle->deviceCallback(handle, kUSB_DeviceEventDetach, NULL);
+}
+
+/*!
+ * @brief Handle the attach notification.
+ *
+ * This function is used to handle the attach notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceAttachNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the device is connected to a host.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ return handle->deviceCallback(handle, kUSB_DeviceEventAttach, NULL);
+}
+#endif
+
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \
+ ((defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U)) || \
+ (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)))
+/*!
+ * @brief Handle the dcd module timeout notification.
+ *
+ * This function is used to handle the dcd module timeout notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceDcdTimeOutNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the device charger detect timeout happened.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ return handle->deviceCallback(handle, kUSB_DeviceEventDcdTimeOut, NULL);
+}
+
+/*!
+ * @brief Handle the dcd module unknown port type notification.
+ *
+ * This function is used to handle the dcd module unknown port type notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceDcdUnknownPortTypeNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the device charger detect unknown port type happened.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ return handle->deviceCallback(handle, kUSB_DeviceEventDcdUnknownType, NULL);
+}
+
+/*!
+ * @brief Handle the SDP facility is detected notification.
+ *
+ * This function is used to handle the SDP facility is detectednotification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceDcdSDPDetectNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the SDP facility is detected.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ return handle->deviceCallback(handle, kUSB_DeviceEventSDPDetected, NULL);
+}
+
+/*!
+ * @brief Handle the charging port is detected notification.
+ *
+ * This function is used to handle the charging port is detectednotification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceDcdChargingPortDetectNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the charing port is detected.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ return handle->deviceCallback(handle, kUSB_DeviceEventChargingPortDetected, NULL);
+}
+
+/*!
+ * @brief Handle the CDP facility is detected notification.
+ *
+ * This function is used to handle the CDP facility is detectednotification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceDcdChargingHostDetectNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the CDP facility is detected.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ return handle->deviceCallback(handle, kUSB_DeviceEventChargingHostDetected, NULL);
+}
+
+/*!
+ * @brief Handle the DCP facility is detected notification.
+ *
+ * This function is used to handle the DCP facility is detectednotification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+
+static usb_status_t USB_DeviceDcdDedicatedChargerDetectNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the DCP facility is detected.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ return handle->deviceCallback(handle, kUSB_DeviceEventDedicatedChargerDetected, NULL);
+}
+#endif
+
+/*!
+ * @brief Handle the attach notification.
+ *
+ * This function is used to handle the attach notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceNotification(usb_device_struct_t *handle, usb_device_callback_message_struct_t *message)
+{
+ uint8_t endpoint = message->code & USB_ENDPOINT_NUMBER_MASK;
+ uint8_t direction = (message->code & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >>
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT;
+ usb_status_t error = kStatus_USB_Error;
+
+ switch (message->code)
+ {
+ case kUSB_DeviceNotifyBusReset:
+ error = USB_DeviceResetNotification(handle, message);
+ break;
+#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+ case kUSB_DeviceNotifySuspend:
+ error = USB_DeviceSuspendNotification(handle, message);
+ break;
+ case kUSB_DeviceNotifyResume:
+ error = USB_DeviceResumeNotification(handle, message);
+ break;
+#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U))
+ case kUSB_DeviceNotifyLPMSleep:
+ error = USB_DeviceSleepNotification(handle, message);
+ break;
+#endif
+#endif
+
+#if (defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U))
+ case kUSB_DeviceNotifyError:
+ error = USB_DeviceErrorNotification(handle, message);
+ break;
+#endif
+
+#if USB_DEVICE_CONFIG_DETACH_ENABLE
+ case kUSB_DeviceNotifyDetach:
+ error = USB_DeviceDetachNotification(handle, message);
+ break;
+ case kUSB_DeviceNotifyAttach:
+ error = USB_DeviceAttachNotification(handle, message);
+ break;
+#endif
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \
+ ((defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U)) || \
+ (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)))
+ case kUSB_DeviceNotifyDcdTimeOut:
+ error = USB_DeviceDcdTimeOutNotification(handle, message);
+ break;
+ case kUSB_DeviceNotifyDcdUnknownPortType:
+ error = USB_DeviceDcdUnknownPortTypeNotification(handle, message);
+ break;
+ case kUSB_DeviceNotifySDPDetected:
+ error = USB_DeviceDcdSDPDetectNotification(handle, message);
+ break;
+ case kUSB_DeviceNotifyChargingPortDetected:
+ error = USB_DeviceDcdChargingPortDetectNotification(handle, message);
+ break;
+ case kUSB_DeviceNotifyChargingHostDetected:
+ error = USB_DeviceDcdChargingHostDetectNotification(handle, message);
+ break;
+ case kUSB_DeviceNotifyDedicatedChargerDetected:
+ error = USB_DeviceDcdDedicatedChargerDetectNotification(handle, message);
+ break;
+#endif
+
+ default:
+ if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS)
+ {
+ if (handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn)
+ {
+ usb_device_endpoint_callback_message_struct_t endpointCallbackMessage;
+ endpointCallbackMessage.buffer = message->buffer;
+ endpointCallbackMessage.length = message->length;
+ endpointCallbackMessage.isSetup = message->isSetup;
+ if (message->isSetup)
+ {
+ handle->epCallback[0].isBusy = 0U;
+ handle->epCallback[1].isBusy = 0U;
+ }
+ else
+ {
+ handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U;
+ }
+ /* Call endpoint callback, callbackFn is in the third parameter of USB_DeviceInitEndpoint */
+ error = handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn(
+ handle, &endpointCallbackMessage,
+ handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam);
+ }
+ }
+ break;
+ }
+ return error;
+}
+
+/*!
+ * @brief Notify the device that the controller status changed.
+ *
+ * This function is used to notify the device that the controller status changed.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceNotificationTrigger(void *handle, void *msg)
+{
+ usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle;
+ usb_device_callback_message_struct_t *message = (usb_device_callback_message_struct_t *)msg;
+
+ if ((NULL == msg) || (NULL == handle))
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+ /* The device callback is invalid or not. */
+ if (!deviceHandle->deviceCallback)
+ {
+ return kStatus_USB_Error;
+ }
+
+#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+ if (deviceHandle->epCallbackDirectly)
+ {
+ if ((message->code & USB_ENDPOINT_NUMBER_MASK) && (!(message->code & 0x70U)))
+ {
+ return USB_DeviceNotification(deviceHandle, message);
+ }
+ }
+
+ /* Add the message to message queue when the device task is enabled. */
+ if (kStatus_USB_OSA_Success != USB_OsaMsgqSend(deviceHandle->notificationQueue, (void *)message))
+ {
+ return kStatus_USB_Busy;
+ }
+ return kStatus_USB_Success;
+#else
+ /* Handle the notification by calling USB_DeviceNotification. */
+ return USB_DeviceNotification(deviceHandle, message);
+#endif
+}
+
+/*!
+ * @brief Initialize the USB device stack.
+ *
+ * This function initializes the USB device module specified by the controllerId.
+ *
+ * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t.
+ * @param deviceCallback Function pointer of the device callback.
+ * @param handle It is out parameter, is used to return pointer of the device handle to the caller.
+ *
+ * @retval kStatus_USB_Success The device is initialized successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer.
+ * @retval kStatus_USB_Busy Cannot allocate a device handle.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller according to the controller id.
+ * @retval kStatus_USB_InvalidControllerInterface The controller driver interfaces is invaild, There is an empty
+ * interface entity.
+ * @retval kStatus_USB_Error The macro USB_DEVICE_CONFIG_ENDPOINTS is more than IP's endpoint number.
+ * Or, the device has been initialized.
+ * Or, the message queue is created failed.
+ */
+usb_status_t USB_DeviceInit(uint8_t controllerId, usb_device_callback_t deviceCallback, usb_device_handle *handle)
+{
+ usb_device_struct_t *deviceHandle = NULL;
+ usb_status_t error;
+ uint32_t count;
+
+ if (NULL == handle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+ /* Allocate a device handle by using the controller id. */
+ error = USB_DeviceAllocateHandle(controllerId, &deviceHandle);
+
+ if (kStatus_USB_Success != error)
+ {
+ return error;
+ }
+
+ /* Save the device callback */
+ deviceHandle->deviceCallback = deviceCallback;
+ /* Save the controller id */
+ deviceHandle->controllerId = controllerId;
+ /* Clear the device address */
+ deviceHandle->deviceAddress = 0U;
+ /* Clear the device reset state */
+ deviceHandle->isResetting = 0U;
+
+ /* Initialize the enpoints */
+ for (count = 0U; count < (USB_DEVICE_CONFIG_ENDPOINTS * 2U); count++)
+ {
+ deviceHandle->epCallback[count].callbackFn = (usb_device_endpoint_callback_t)NULL;
+ deviceHandle->epCallback[count].callbackParam = NULL;
+ deviceHandle->epCallback[count].isBusy = 0U;
+ }
+
+ /* Get the controller interface according to the controller id */
+ error = USB_DeviceGetControllerInterface(controllerId, &deviceHandle->controllerInterface);
+ if (kStatus_USB_Success != error)
+ {
+ USB_DeviceFreeHandle(deviceHandle);
+ return error;
+ }
+ if (NULL == deviceHandle->controllerInterface)
+ {
+ USB_DeviceFreeHandle(deviceHandle);
+ return kStatus_USB_ControllerNotFound;
+ }
+ if (((usb_device_controller_init_t)NULL == deviceHandle->controllerInterface->deviceInit) ||
+ ((usb_device_controller_deinit_t)NULL == deviceHandle->controllerInterface->deviceDeinit) ||
+ ((usb_device_controller_send_t)NULL == deviceHandle->controllerInterface->deviceSend) ||
+ ((usb_device_controller_recv_t)NULL == deviceHandle->controllerInterface->deviceRecv) ||
+ ((usb_device_controller_cancel_t)NULL == deviceHandle->controllerInterface->deviceCancel) ||
+ ((usb_device_controller_control_t)NULL == deviceHandle->controllerInterface->deviceControl))
+ {
+ USB_DeviceFreeHandle(deviceHandle);
+ return kStatus_USB_InvalidControllerInterface;
+ }
+
+#if USB_DEVICE_CONFIG_USE_TASK
+ /* Create a message queue when the device handle is enabled. */
+ if (kStatus_USB_OSA_Success !=
+ USB_OsaMsgqCreate(&deviceHandle->notificationQueue, USB_DEVICE_CONFIG_MAX_MESSAGES,
+ (1U + (sizeof(usb_device_callback_message_struct_t) - 1U) / sizeof(uint32_t))))
+ {
+ USB_DeviceDeinit(deviceHandle);
+ return kStatus_USB_Error;
+ }
+#endif
+
+ *handle = deviceHandle;
+
+ /* Initialize the controller, the callbackFn is initialized in USB_DeviceGetControllerInterface */
+ error = deviceHandle->controllerInterface->deviceInit(controllerId, deviceHandle, &deviceHandle->controllerHandle);
+ if (kStatus_USB_Success != error)
+ {
+ USB_DeviceDeinit(deviceHandle);
+ *handle = NULL;
+ return error;
+ }
+ /* Set the device to deafult state */
+ deviceHandle->state = kUSB_DeviceStateDefault;
+
+ return error;
+}
+
+/*!
+ * @brief Enable the device functionality.
+ *
+ * The function enables the device functionality, so that the device can be recognized by the host when the device
+ * detects that it has been connected to a host.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The device is run successfully.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid.
+ *
+ */
+usb_status_t USB_DeviceRun(usb_device_handle handle)
+{
+ return USB_DeviceControl(handle, kUSB_DeviceControlRun, NULL);
+}
+/*!
+ * @brief Disable the device functionality.
+ *
+ * The function disables the device functionality, after this function called, even the device is detached to the host,
+ * and the device can't work.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The device is stopped successfully.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid.
+ */
+usb_status_t USB_DeviceStop(usb_device_handle handle)
+{
+ return USB_DeviceControl(handle, kUSB_DeviceControlStop, NULL);
+}
+/*!
+ * @brief De-initialize the device controller.
+ *
+ * The function de-initializes the device controller specified by the handle.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The device is stopped successfully.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid.
+ */
+usb_status_t USB_DeviceDeinit(usb_device_handle handle)
+{
+ usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle;
+
+ if (NULL == deviceHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+ /* De-initialize the controller */
+ if (NULL != deviceHandle->controllerInterface)
+ {
+ /* the callbackFn is initialized in USB_DeviceGetControllerInterface */
+ deviceHandle->controllerInterface->deviceDeinit(deviceHandle->controllerHandle);
+ deviceHandle->controllerInterface = (usb_device_controller_interface_struct_t *)NULL;
+ }
+
+#if USB_DEVICE_CONFIG_USE_TASK
+ /* Destroy the message queue. */
+ if (NULL != deviceHandle->notificationQueue)
+ {
+ USB_OsaMsgqDestroy(deviceHandle->notificationQueue);
+ deviceHandle->notificationQueue = NULL;
+ }
+#endif
+
+ /* Free the device handle. */
+ USB_DeviceFreeHandle(deviceHandle);
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief Send data through a specified endpoint.
+ *
+ * The function is used to send data through a specified endpoint.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param endpointAddress Endpoint index.
+ * @param buffer The memory address to hold the data need to be sent.
+ * @param length The data length need to be sent.
+ *
+ * @retval kStatus_USB_Success The send request is sent successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_Busy Cannot allocate dtds for current tansfer in EHCI driver.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_Error The device is doing reset.
+ *
+ * @note The return value just means if the sending request is successful or not; the transfer done is notified by the
+ * corresponding callback function.
+ * Currently, only one transfer request can be supported for one specific endpoint.
+ * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application
+ * should implement a queue in the application level.
+ * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint
+ * callback).
+ */
+usb_status_t USB_DeviceSendRequest(usb_device_handle handle, uint8_t endpointAddress, uint8_t *buffer, uint32_t length)
+{
+ return USB_DeviceTransfer(handle, (endpointAddress & USB_ENDPOINT_NUMBER_MASK) |
+ (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT),
+ buffer, length);
+}
+
+/*!
+ * @brief Receive data through a specified endpoint.
+ *
+ * The function is used to receive data through a specified endpoint.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param endpointAddress Endpoint index.
+ * @param buffer The memory address to save the received data.
+ * @param length The data length want to be received.
+ *
+ * @retval kStatus_USB_Success The receive request is sent successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_Busy Cannot allocate dtds for current tansfer in EHCI driver.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_Error The device is doing reset.
+ *
+ * @note The return value just means if the receiving request is successful or not; the transfer done is notified by the
+ * corresponding callback function.
+ * Currently, only one transfer request can be supported for one specific endpoint.
+ * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application
+ * should implement a queue in the application level.
+ * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint
+ * callback).
+ */
+usb_status_t USB_DeviceRecvRequest(usb_device_handle handle, uint8_t endpointAddress, uint8_t *buffer, uint32_t length)
+{
+ return USB_DeviceTransfer(handle, (endpointAddress & USB_ENDPOINT_NUMBER_MASK) |
+ (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT),
+ buffer, length);
+}
+
+/*!
+ * @brief Cancel the pending transfer in a specified endpoint.
+ *
+ * The function is used to cancel the pending transfer in a specified endpoint.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT.
+ *
+ * @retval kStatus_USB_Success The transfer is cancelled.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+usb_status_t USB_DeviceCancel(usb_device_handle handle, uint8_t endpointAddress)
+{
+ usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle;
+ usb_status_t error = kStatus_USB_Error;
+
+ if (NULL == deviceHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+ if (NULL != deviceHandle->controllerInterface)
+ {
+ /* the callbackFn is initialized in USB_DeviceGetControllerInterface */
+ error = deviceHandle->controllerInterface->deviceCancel(deviceHandle->controllerHandle, endpointAddress);
+ }
+ else
+ {
+ error = kStatus_USB_ControllerNotFound;
+ }
+ return error;
+}
+
+/*!
+ * @brief Initialize a specified endpoint.
+ *
+ * The function is used to initialize a specified endpoint and the corresponding endpoint callback is also initialized.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param epInit Endpoint initizlization structure. Please refer to the structure usb_device_endpoint_init_struct_t.
+ * @param epCallback Endpoint callback structure. Please refer to the structure
+ * usb_device_endpoint_callback_struct_t.
+ *
+ * @retval kStatus_USB_Success The endpoint is initialized successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The epInit or epCallback is NULL pointer. Or the endpoint number is
+ * more than USB_DEVICE_CONFIG_ENDPOINTS.
+ * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+usb_status_t USB_DeviceInitEndpoint(usb_device_handle handle,
+ usb_device_endpoint_init_struct_t *epInit,
+ usb_device_endpoint_callback_struct_t *epCallback)
+{
+ usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle;
+ uint8_t endpoint;
+ uint8_t direction;
+
+ if (!deviceHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+ if ((!epInit) || (!epCallback))
+ {
+ return kStatus_USB_InvalidParameter;
+ }
+
+ endpoint = epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK;
+ direction = (epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >>
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT;
+
+ if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS)
+ {
+ deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn = epCallback->callbackFn;
+ deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam =
+ epCallback->callbackParam;
+ deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U;
+ }
+ else
+ {
+ return kStatus_USB_InvalidParameter;
+ }
+ return USB_DeviceControl(handle, kUSB_DeviceControlEndpointInit, epInit);
+}
+
+/*!
+ * @brief De-initizlize a specified endpoint.
+ *
+ * The function is used to de-initizlize a specified endpoint.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT.
+ *
+ * @retval kStatus_USB_Success The endpoint is de-initialized successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS.
+ * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+usb_status_t USB_DeviceDeinitEndpoint(usb_device_handle handle, uint8_t endpointAddress)
+{
+ usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle;
+ uint8_t endpoint = endpointAddress & USB_ENDPOINT_NUMBER_MASK;
+ uint8_t direction = (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >>
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT;
+ usb_status_t error = kStatus_USB_Error;
+#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+ USB_OSA_SR_ALLOC();
+#endif
+
+ if (!deviceHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+ USB_OSA_ENTER_CRITICAL();
+ deviceHandle->epCallbackDirectly = 1;
+ USB_OSA_EXIT_CRITICAL();
+#endif
+ error = USB_DeviceControl(handle, kUSB_DeviceControlEndpointDeinit, &endpointAddress);
+#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+ USB_OSA_ENTER_CRITICAL();
+ deviceHandle->epCallbackDirectly = 0;
+ USB_OSA_EXIT_CRITICAL();
+#endif
+
+ if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS)
+ {
+ deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn =
+ (usb_device_endpoint_callback_t)NULL;
+ deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam = NULL;
+ deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U;
+ }
+ else
+ {
+ return kStatus_USB_InvalidParameter;
+ }
+ return error;
+}
+
+/*!
+ * @brief Stall a specified endpoint.
+ *
+ * The function is used to stall a specified endpoint.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT.
+ *
+ * @retval kStatus_USB_Success The endpoint is stalled successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+usb_status_t USB_DeviceStallEndpoint(usb_device_handle handle, uint8_t endpointAddress)
+{
+ if ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) < USB_DEVICE_CONFIG_ENDPOINTS)
+ {
+ return USB_DeviceControl(handle, kUSB_DeviceControlEndpointStall, &endpointAddress);
+ }
+ else
+ {
+ return kStatus_USB_InvalidParameter;
+ }
+}
+
+/*!
+ * @brief Un-stall a specified endpoint.
+ *
+ * The function is used to un-stall a specified endpoint.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT.
+ *
+ * @retval kStatus_USB_Success The endpoint is un-stalled successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+usb_status_t USB_DeviceUnstallEndpoint(usb_device_handle handle, uint8_t endpointAddress)
+{
+ if ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) < USB_DEVICE_CONFIG_ENDPOINTS)
+ {
+ return USB_DeviceControl(handle, kUSB_DeviceControlEndpointUnstall, &endpointAddress);
+ }
+ else
+ {
+ return kStatus_USB_InvalidParameter;
+ }
+}
+
+/*!
+ * @brief Get the status of the selected item.
+ *
+ * The function is used to get the status of the selected item.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param type The selected item. Please refer to the structure usb_device_status_t.
+ * @param param The param type is determined by the selected item.
+ *
+ * @retval kStatus_USB_Success Get status successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The param is NULL pointer.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_Error Unsupported type.
+ */
+usb_status_t USB_DeviceGetStatus(usb_device_handle handle, usb_device_status_t type, void *param)
+{
+ uint8_t *temp8;
+ usb_status_t error = kStatus_USB_Error;
+
+ if (NULL == param)
+ {
+ return kStatus_USB_InvalidParameter;
+ }
+ switch (type)
+ {
+ case kUSB_DeviceStatusSpeed:
+ error = USB_DeviceControl(handle, kUSB_DeviceControlGetSpeed, param);
+ break;
+ case kUSB_DeviceStatusOtg:
+ error = USB_DeviceControl(handle, kUSB_DeviceControlGetOtgStatus, param);
+ break;
+ case kUSB_DeviceStatusDeviceState:
+ temp8 = (uint8_t *)param;
+ error = kStatus_USB_Success;
+ *temp8 = ((usb_device_struct_t *)handle)->state;
+ break;
+ case kUSB_DeviceStatusAddress:
+ temp8 = (uint8_t *)param;
+ error = kStatus_USB_Success;
+ *temp8 = ((usb_device_struct_t *)handle)->deviceAddress;
+ break;
+ case kUSB_DeviceStatusDevice:
+ error = USB_DeviceControl(handle, kUSB_DeviceControlGetDeviceStatus, param);
+ break;
+ case kUSB_DeviceStatusEndpoint:
+ error = USB_DeviceControl(handle, kUSB_DeviceControlGetEndpointStatus, param);
+ break;
+ case kUSB_DeviceStatusSynchFrame:
+ error = USB_DeviceControl(handle, kUSB_DeviceControlGetSynchFrame, param);
+ break;
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+ case kUSB_DeviceStatusRemoteWakeup:
+ temp8 = (uint8_t *)param;
+ error = kStatus_USB_Success;
+ *temp8 = ((usb_device_struct_t *)handle)->remotewakeup;
+ break;
+#endif
+ default:
+ break;
+ }
+ return error;
+}
+
+/*!
+ * @brief Set the status of the selected item.
+ *
+ * The function is used to set the status of the selected item.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param type The selected item. Please refer to the structure usb_device_status_t.
+ * @param param The param type is determined by the selected item.
+ *
+ * @retval kStatus_USB_Success Set status successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_Error Unsupported type, or the param is NULL pointer.
+ */
+usb_status_t USB_DeviceSetStatus(usb_device_handle handle, usb_device_status_t type, void *param)
+{
+ usb_status_t error = kStatus_USB_Error;
+ switch (type)
+ {
+#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) || \
+ (defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) && \
+ (defined(USB_DEVICE_CONFIG_USB20_TEST_MODE) && (USB_DEVICE_CONFIG_USB20_TEST_MODE > 0U))
+ case kUSB_DeviceStatusTestMode:
+ error = USB_DeviceControl(handle, kUSB_DeviceControlSetTestMode, param);
+ break;
+#endif
+ case kUSB_DeviceStatusOtg:
+ error = USB_DeviceControl(handle, kUSB_DeviceControlSetOtgStatus, param);
+ break;
+ case kUSB_DeviceStatusDeviceState:
+ if (NULL != param)
+ {
+ error = kStatus_USB_Success;
+ ((usb_device_struct_t *)handle)->state = (uint8_t)(*(uint8_t *)param);
+ }
+ break;
+ case kUSB_DeviceStatusAddress:
+ if (kUSB_DeviceStateAddressing != ((usb_device_struct_t *)handle)->state)
+ {
+ if (NULL != param)
+ {
+ error = kStatus_USB_Success;
+ ((usb_device_struct_t *)handle)->deviceAddress = (uint8_t)(*(uint8_t *)param);
+ ((usb_device_struct_t *)handle)->state = kUSB_DeviceStateAddressing;
+ }
+ }
+ else
+ {
+ error = USB_DeviceControl(handle, kUSB_DeviceControlSetDeviceAddress,
+ &((usb_device_struct_t *)handle)->deviceAddress);
+ }
+ break;
+ case kUSB_DeviceStatusBusResume:
+ error = USB_DeviceControl(handle, kUSB_DeviceControlResume, param);
+ break;
+ case kUSB_DeviceStatusBusSleepResume:
+ error = USB_DeviceControl(handle, kUSB_DeviceControlSleepResume, param);
+ break;
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+ case kUSB_DeviceStatusRemoteWakeup:
+ if (NULL != param)
+ {
+ error = kStatus_USB_Success;
+ ((usb_device_struct_t *)handle)->remotewakeup = (uint8_t)(*(uint8_t *)param);
+ }
+ break;
+#endif
+ case kUSB_DeviceStatusBusSuspend:
+ error = USB_DeviceControl(handle, kUSB_DeviceControlSuspend, param);
+ break;
+ case kUSB_DeviceStatusBusSleep:
+ error = USB_DeviceControl(handle, kUSB_DeviceControlSleep, param);
+ break;
+ default:
+ break;
+ }
+ return error;
+}
+
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \
+ ((defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U)) || \
+ (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)))
+/*!
+ * @brief Initializes the device dcd module.
+ *
+ * The function initializes the device dcd module.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The device is run successfully.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid.
+ *
+ */
+usb_status_t USB_DeviceDcdInitModule(usb_device_handle handle, void *time_param)
+{
+ return USB_DeviceControl(handle, kUSB_DeviceControlDcdInitModule, time_param);
+}
+
+/*!
+ * @brief De-initializes the device dcd module.
+ *
+ * The function de-intializes the device dcd module.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The device is run successfully.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid.
+ *
+ */
+usb_status_t USB_DeviceDcdDeinitModule(usb_device_handle handle)
+{
+ return USB_DeviceControl(handle, kUSB_DeviceControlDcdDeinitModule, NULL);
+}
+#endif
+
+#if USB_DEVICE_CONFIG_USE_TASK
+/*!
+ * @brief Device task function.
+ *
+ * The function is used to handle controller message.
+ * This function should not be called in applicartion directly.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ */
+void USB_DeviceTaskFunction(void *deviceHandle)
+{
+ usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle;
+ static usb_device_callback_message_struct_t message;
+
+ if (deviceHandle)
+ {
+ /* Get the message from the queue */
+ if (kStatus_USB_OSA_Success == USB_OsaMsgqRecv(handle->notificationQueue, (uint32_t *)&message, 0U))
+ {
+ /* Handle the message */
+ USB_DeviceNotification(handle, &message);
+ }
+ }
+}
+#endif
+
+/*!
+ * @brief Get dvice stack version function.
+ *
+ * The function is used to get dvice stack version.
+ *
+ * @param[out] version The version structure pointer to keep the device stack version.
+ *
+ */
+void USB_DeviceGetVersion(uint32_t *version)
+{
+ if (version)
+ {
+ *version =
+ (uint32_t)USB_MAKE_VERSION(USB_STACK_VERSION_MAJOR, USB_STACK_VERSION_MINOR, USB_STACK_VERSION_BUGFIX);
+ }
+}
+
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+/*!
+ * @brief Update the hardware tick.
+ *
+ * The function is used to update the hardware tick.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ * @param[in] tick Current hardware tick.
+ *
+ */
+usb_status_t USB_DeviceUpdateHwTick(usb_device_handle handle, uint64_t tick)
+{
+ usb_device_struct_t *deviceHandle;
+ usb_status_t status = kStatus_USB_Success;
+
+ if (handle == NULL)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+ deviceHandle = (usb_device_struct_t *)handle;
+
+ deviceHandle->hwTick = tick;
+
+ return status;
+}
+#endif
+#endif /* USB_DEVICE_CONFIG_NUM */
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __USB_DEVICE_DCI_H__
+#define __USB_DEVICE_DCI_H__
+
+/*!
+ * @addtogroup usb_device_controller_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Macro to define controller handle */
+#define usb_device_controller_handle usb_device_handle
+
+/*! @brief Available notify types for device notification */
+typedef enum _usb_device_notification
+{
+ kUSB_DeviceNotifyBusReset = 0x10U, /*!< Reset signal detected */
+ kUSB_DeviceNotifySuspend, /*!< Suspend signal detected */
+ kUSB_DeviceNotifyResume, /*!< Resume signal detected */
+ kUSB_DeviceNotifyLPMSleep, /*!< LPM signal detected */
+ kUSB_DeviceNotifyLPMResume, /*!< Resume signal detected */
+ kUSB_DeviceNotifyError, /*!< Errors happened in bus */
+ kUSB_DeviceNotifyDetach, /*!< Device disconnected from a host */
+ kUSB_DeviceNotifyAttach, /*!< Device connected to a host */
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U))
+ kUSB_DeviceNotifyDcdTimeOut, /*!< Device charger detection timeout */
+ kUSB_DeviceNotifyDcdUnknownPortType, /*!< Device charger detection unknown port type */
+ kUSB_DeviceNotifySDPDetected, /*!< The SDP facility is detected */
+ kUSB_DeviceNotifyChargingPortDetected, /*!< The charging port is detected */
+ kUSB_DeviceNotifyChargingHostDetected, /*!< The CDP facility is detected */
+ kUSB_DeviceNotifyDedicatedChargerDetected, /*!< The DCP facility is detected */
+#endif
+} usb_device_notification_t;
+
+/*! @brief Device notification message structure */
+typedef struct _usb_device_callback_message_struct
+{
+ uint8_t *buffer; /*!< Transferred buffer */
+ uint32_t length; /*!< Transferred data length */
+ uint8_t code; /*!< Notification code */
+ uint8_t isSetup; /*!< Is in a setup phase */
+} usb_device_callback_message_struct_t;
+
+/*! @brief Control type for controller */
+typedef enum _usb_device_control_type
+{
+ kUSB_DeviceControlRun = 0U, /*!< Enable the device functionality */
+ kUSB_DeviceControlStop, /*!< Disable the device functionality */
+ kUSB_DeviceControlEndpointInit, /*!< Initialize a specified endpoint */
+ kUSB_DeviceControlEndpointDeinit, /*!< De-initialize a specified endpoint */
+ kUSB_DeviceControlEndpointStall, /*!< Stall a specified endpoint */
+ kUSB_DeviceControlEndpointUnstall, /*!< Unstall a specified endpoint */
+ kUSB_DeviceControlGetDeviceStatus, /*!< Get device status */
+ kUSB_DeviceControlGetEndpointStatus, /*!< Get endpoint status */
+ kUSB_DeviceControlSetDeviceAddress, /*!< Set device address */
+ kUSB_DeviceControlGetSynchFrame, /*!< Get current frame */
+ kUSB_DeviceControlResume, /*!< Drive controller to generate a resume signal in USB bus */
+ kUSB_DeviceControlSleepResume, /*!< Drive controller to generate a LPM resume signal in USB bus */
+ kUSB_DeviceControlSuspend, /*!< Drive controller to enetr into suspend mode */
+ kUSB_DeviceControlSleep, /*!< Drive controller to enetr into sleep mode */
+ kUSB_DeviceControlSetDefaultStatus, /*!< Set controller to default status */
+ kUSB_DeviceControlGetSpeed, /*!< Get current speed */
+ kUSB_DeviceControlGetOtgStatus, /*!< Get OTG status */
+ kUSB_DeviceControlSetOtgStatus, /*!< Set OTG status */
+ kUSB_DeviceControlSetTestMode, /*!< Drive xCHI into test mode */
+ kUSB_DeviceControlGetRemoteWakeUp, /*!< Get flag of LPM Remote Wake-up Enabled by USB host. */
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U))
+ kUSB_DeviceControlDcdInitModule,
+ kUSB_DeviceControlDcdDeinitModule,
+#endif
+} usb_device_control_type_t;
+
+/*! @brief USB device controller initialization function typedef */
+typedef usb_status_t (*usb_device_controller_init_t)(uint8_t controllerId,
+ usb_device_handle handle,
+ usb_device_controller_handle *controllerHandle);
+
+/*! @brief USB device controller de-initialization function typedef */
+typedef usb_status_t (*usb_device_controller_deinit_t)(usb_device_controller_handle controllerHandle);
+
+/*! @brief USB device controller send data function typedef */
+typedef usb_status_t (*usb_device_controller_send_t)(usb_device_controller_handle controllerHandle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*! @brief USB device controller receive data function typedef */
+typedef usb_status_t (*usb_device_controller_recv_t)(usb_device_controller_handle controllerHandle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*! @brief USB device controller cancel transfer function in a specified endpoint typedef */
+typedef usb_status_t (*usb_device_controller_cancel_t)(usb_device_controller_handle controllerHandle,
+ uint8_t endpointAddress);
+
+/*! @brief USB device controller control function typedef */
+typedef usb_status_t (*usb_device_controller_control_t)(usb_device_controller_handle controllerHandle,
+ usb_device_control_type_t command,
+ void *param);
+
+/*! @brief USB device controller interface structure */
+typedef struct _usb_device_controller_interface_struct
+{
+ usb_device_controller_init_t deviceInit; /*!< Controller initialization */
+ usb_device_controller_deinit_t deviceDeinit; /*!< Controller de-initialization */
+ usb_device_controller_send_t deviceSend; /*!< Controller send data */
+ usb_device_controller_recv_t deviceRecv; /*!< Controller receive data */
+ usb_device_controller_cancel_t deviceCancel; /*!< Controller cancel transfer */
+ usb_device_controller_control_t deviceControl; /*!< Controller control */
+} usb_device_controller_interface_struct_t;
+
+/*! @brief USB device status structure */
+typedef struct _usb_device_struct
+{
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+ volatile uint64_t hwTick; /*!< Current hw tick(ms)*/
+#endif
+ usb_device_controller_handle controllerHandle; /*!< Controller handle */
+ const usb_device_controller_interface_struct_t *controllerInterface; /*!< Controller interface handle */
+#if USB_DEVICE_CONFIG_USE_TASK
+ usb_osa_msgq_handle notificationQueue; /*!< Message queue */
+#endif
+ usb_device_callback_t deviceCallback; /*!< Device callback function pointer */
+ usb_device_endpoint_callback_struct_t
+ epCallback[USB_DEVICE_CONFIG_ENDPOINTS << 1U]; /*!< Endpoint callback function structure */
+ uint8_t deviceAddress; /*!< Current device address */
+ uint8_t controllerId; /*!< Controller ID */
+ uint8_t state; /*!< Current device state */
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+ uint8_t remotewakeup; /*!< Remote wakeup is enabled or not */
+#endif
+ uint8_t isResetting; /*!< Is doing device reset or not */
+#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+ uint8_t epCallbackDirectly; /*!< Whether call ep callback directly when the task is enabled */
+#endif
+} usb_device_struct_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*! @}*/
+
+#endif /* __USB_DEVICE_DCI_H__ */
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "usb_device_config.h"
+#include "usb.h"
+#include "usb_device.h"
+
+#include "usb_device_cdc_acm.h"
+
+#include "usb_device_descriptor.h"
+
+/*******************************************************************************
+* Variables
+******************************************************************************/
+uint8_t g_currentConfigure = 0;
+uint8_t g_interface[USB_CDC_VCOM_INTERFACE_COUNT];
+
+/* Define device descriptor */
+uint8_t g_UsbDeviceDescriptor[USB_DESCRIPTOR_LENGTH_DEVICE] = {
+ /* Size of this descriptor in bytes */
+ USB_DESCRIPTOR_LENGTH_DEVICE,
+ /* DEVICE Descriptor Type */
+ USB_DESCRIPTOR_TYPE_DEVICE,
+ /* USB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). */
+ USB_SHORT_GET_LOW(USB_DEVICE_SPECIFIC_BCD_VERSION), USB_SHORT_GET_HIGH(USB_DEVICE_SPECIFIC_BCD_VERSION),
+ /* Class code (assigned by the USB-IF). */
+ USB_DEVICE_CLASS,
+ /* Subclass code (assigned by the USB-IF). */
+ USB_DEVICE_SUBCLASS,
+ /* Protocol code (assigned by the USB-IF). */
+ USB_DEVICE_PROTOCOL,
+ /* Maximum packet size for endpoint zero (only 8, 16, 32, or 64 are valid) */
+ USB_CONTROL_MAX_PACKET_SIZE,
+ /* Vendor ID (assigned by the USB-IF) */
+ 0xC9U, 0x1FU,
+ /* Product ID (assigned by the manufacturer) */
+ 0x94, 0x00,
+ /* Device release number in binary-coded decimal */
+ USB_SHORT_GET_LOW(USB_DEVICE_DEMO_BCD_VERSION), USB_SHORT_GET_HIGH(USB_DEVICE_DEMO_BCD_VERSION),
+ /* Index of string descriptor describing manufacturer */
+ 0x01,
+ /* Index of string descriptor describing product */
+ 0x02,
+ /* Index of string descriptor describing the device's serial number */
+ 0x00,
+ /* Number of possible configurations */
+ USB_DEVICE_CONFIGURATION_COUNT,
+};
+
+/* Define configuration descriptor */
+uint8_t g_UsbDeviceConfigurationDescriptor[USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL] = {
+ /* Size of this descriptor in bytes */
+ USB_DESCRIPTOR_LENGTH_CONFIGURE,
+ /* CONFIGURATION Descriptor Type */
+ USB_DESCRIPTOR_TYPE_CONFIGURE,
+ /* Total length of data returned for this configuration. */
+ USB_SHORT_GET_LOW(USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL),
+ USB_SHORT_GET_HIGH(USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL),
+ /* Number of interfaces supported by this configuration */
+ USB_CDC_VCOM_INTERFACE_COUNT,
+ /* Value to use as an argument to the SetConfiguration() request to select this configuration */
+ USB_CDC_VCOM_CONFIGURE_INDEX,
+ /* Index of string descriptor describing this configuration */
+ 0,
+ /* Configuration characteristics D7: Reserved (set to one) D6: Self-powered D5: Remote Wakeup D4...0: Reserved
+ (reset to zero) */
+ (USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_MASK) |
+ (USB_DEVICE_CONFIG_SELF_POWER << USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_SHIFT) |
+ (USB_DEVICE_CONFIG_REMOTE_WAKEUP << USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_SHIFT),
+ /* Maximum power consumption of the USB * device from the bus in this specific * configuration when the device is
+ fully * operational. Expressed in 2 mA units * (i.e., 50 = 100 mA). */
+ USB_DEVICE_MAX_POWER,
+
+ /* Communication Interface Descriptor */
+ USB_DESCRIPTOR_LENGTH_INTERFACE, USB_DESCRIPTOR_TYPE_INTERFACE, USB_CDC_VCOM_COMM_INTERFACE_INDEX, 0x00,
+ USB_CDC_VCOM_ENDPOINT_CIC_COUNT, USB_CDC_VCOM_CIC_CLASS, USB_CDC_VCOM_CIC_SUBCLASS, USB_CDC_VCOM_CIC_PROTOCOL,
+ 0x00, /* Interface Description String Index*/
+
+ /* CDC Class-Specific descriptor */
+ USB_DESCRIPTOR_LENGTH_CDC_HEADER_FUNC, /* Size of this descriptor in bytes */
+ USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */
+ USB_CDC_HEADER_FUNC_DESC, 0x10,
+ 0x01, /* USB Class Definitions for Communications the Communication specification version 1.10 */
+
+ USB_DESCRIPTOR_LENGTH_CDC_CALL_MANAG, /* Size of this descriptor in bytes */
+ USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */
+ USB_CDC_CALL_MANAGEMENT_FUNC_DESC,
+ 0x01, /*Bit 0: Whether device handle call management itself 1, Bit 1: Whether device can send/receive call
+ management information over a Data Class Interface 0 */
+ 0x01, /* Indicates multiplexed commands are handled via data interface */
+
+ USB_DESCRIPTOR_LENGTH_CDC_ABSTRACT, /* Size of this descriptor in bytes */
+ USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */
+ USB_CDC_ABSTRACT_CONTROL_FUNC_DESC,
+ 0x06, /* Bit 0: Whether device supports the request combination of Set_Comm_Feature, Clear_Comm_Feature, and
+ Get_Comm_Feature 0, Bit 1: Whether device supports the request combination of Set_Line_Coding,
+ Set_Control_Line_State, Get_Line_Coding, and the notification Serial_State 1, Bit ... */
+
+ USB_DESCRIPTOR_LENGTH_CDC_UNION_FUNC, /* Size of this descriptor in bytes */
+ USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */
+ USB_CDC_UNION_FUNC_DESC, 0x00, /* The interface number of the Communications or Data Class interface */
+ 0x01, /* Interface number of subordinate interface in the Union */
+
+ /*Notification Endpoint descriptor */
+ USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT, USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT | (USB_IN << 7U),
+ USB_ENDPOINT_INTERRUPT, USB_SHORT_GET_LOW(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE),
+ USB_SHORT_GET_HIGH(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE), FS_CDC_VCOM_INTERRUPT_IN_INTERVAL,
+
+ /* Data Interface Descriptor */
+ USB_DESCRIPTOR_LENGTH_INTERFACE, USB_DESCRIPTOR_TYPE_INTERFACE, USB_CDC_VCOM_DATA_INTERFACE_INDEX, 0x00,
+ USB_CDC_VCOM_ENDPOINT_DIC_COUNT, USB_CDC_VCOM_DIC_CLASS, USB_CDC_VCOM_DIC_SUBCLASS, USB_CDC_VCOM_DIC_PROTOCOL,
+ 0x00, /* Interface Description String Index*/
+
+ /*Bulk IN Endpoint descriptor */
+ USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT, USB_CDC_VCOM_BULK_IN_ENDPOINT | (USB_IN << 7U),
+ USB_ENDPOINT_BULK, USB_SHORT_GET_LOW(FS_CDC_VCOM_BULK_IN_PACKET_SIZE),
+ USB_SHORT_GET_HIGH(FS_CDC_VCOM_BULK_IN_PACKET_SIZE), 0x00, /* The polling interval value is every 0 Frames */
+
+ /*Bulk OUT Endpoint descriptor */
+ USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT, USB_CDC_VCOM_BULK_OUT_ENDPOINT | (USB_OUT << 7U),
+ USB_ENDPOINT_BULK, USB_SHORT_GET_LOW(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE),
+ USB_SHORT_GET_HIGH(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE), 0x00, /* The polling interval value is every 0 Frames */
+};
+
+/* Define string descriptor */
+uint8_t g_UsbDeviceString0[USB_DESCRIPTOR_LENGTH_STRING0] = {sizeof(g_UsbDeviceString0), USB_DESCRIPTOR_TYPE_STRING,
+ 0x09, 0x04};
+
+uint8_t g_UsbDeviceString1[USB_DESCRIPTOR_LENGTH_STRING1] = {
+ sizeof(g_UsbDeviceString1),
+ USB_DESCRIPTOR_TYPE_STRING,
+ 'N',
+ 0x00U,
+ 'X',
+ 0x00U,
+ 'P',
+ 0x00U,
+ ' ',
+ 0x00U,
+ 'S',
+ 0x00U,
+ 'E',
+ 0x00U,
+ 'M',
+ 0x00U,
+ 'I',
+ 0x00U,
+ 'C',
+ 0x00U,
+ 'O',
+ 0x00U,
+ 'N',
+ 0x00U,
+ 'D',
+ 0x00U,
+ 'U',
+ 0x00U,
+ 'C',
+ 0x00U,
+ 'T',
+ 0x00U,
+ 'O',
+ 0x00U,
+ 'R',
+ 0x00U,
+ 'S',
+ 0x00U,
+};
+
+uint8_t g_UsbDeviceString2[USB_DESCRIPTOR_LENGTH_STRING2] = {sizeof(g_UsbDeviceString2),
+ USB_DESCRIPTOR_TYPE_STRING,
+ 'M',
+ 0,
+ 'C',
+ 0,
+ 'U',
+ 0,
+ ' ',
+ 0,
+ 'V',
+ 0,
+ 'I',
+ 0,
+ 'R',
+ 0,
+ 'T',
+ 0,
+ 'U',
+ 0,
+ 'A',
+ 0,
+ 'L',
+ 0,
+ ' ',
+ 0,
+ 'C',
+ 0,
+ 'O',
+ 0,
+ 'M',
+ 0,
+ ' ',
+ 0,
+ 'D',
+ 0,
+ 'E',
+ 0,
+ 'M',
+ 0,
+ 'O',
+ 0};
+
+uint8_t *g_UsbDeviceStringDescriptorArray[USB_DEVICE_STRING_COUNT] = {g_UsbDeviceString0, g_UsbDeviceString1,
+ g_UsbDeviceString2};
+
+/* Define string descriptor size */
+uint32_t g_UsbDeviceStringDescriptorLength[USB_DEVICE_STRING_COUNT] = {
+ sizeof(g_UsbDeviceString0), sizeof(g_UsbDeviceString1), sizeof(g_UsbDeviceString2)};
+usb_language_t g_UsbDeviceLanguage[USB_DEVICE_LANGUAGE_COUNT] = {{
+ g_UsbDeviceStringDescriptorArray, g_UsbDeviceStringDescriptorLength, (uint16_t)0x0409,
+}};
+
+usb_language_list_t g_UsbDeviceLanguageList = {
+ g_UsbDeviceString0, sizeof(g_UsbDeviceString0), g_UsbDeviceLanguage, USB_DEVICE_LANGUAGE_COUNT,
+};
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+/*!
+ * @brief Get the descritpor.
+ *
+ * The function is used to get the descritpor, including the device descritpor, configuration descriptor, and string
+ * descriptor, etc.
+ *
+ * @param handle The device handle.
+ * @param setup The setup packet buffer address.
+ * @param length It is an OUT parameter, return the data length need to be sent to host.
+ * @param buffer It is an OUT parameter, return the data buffer address.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceGetDescriptor(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint32_t *length,
+ uint8_t **buffer)
+{
+ uint8_t descriptorType = (uint8_t)((setup->wValue & 0xFF00U) >> 8U);
+ uint8_t descriptorIndex = (uint8_t)((setup->wValue & 0x00FFU));
+ usb_status_t ret = kStatus_USB_Success;
+ if (USB_REQUEST_STANDARD_GET_DESCRIPTOR != setup->bRequest)
+ {
+ return kStatus_USB_InvalidRequest;
+ }
+ switch (descriptorType)
+ {
+ case USB_DESCRIPTOR_TYPE_STRING:
+ {
+ if (descriptorIndex == 0)
+ {
+ *buffer = (uint8_t *)g_UsbDeviceLanguageList.languageString;
+ *length = g_UsbDeviceLanguageList.stringLength;
+ }
+ else
+ {
+ uint8_t langId = 0;
+ uint8_t langIndex = USB_DEVICE_STRING_COUNT;
+
+ for (; langId < USB_DEVICE_LANGUAGE_COUNT; langId++)
+ {
+ if (setup->wIndex == g_UsbDeviceLanguageList.languageList[langId].languageId)
+ {
+ if (descriptorIndex < USB_DEVICE_STRING_COUNT)
+ {
+ langIndex = descriptorIndex;
+ }
+ break;
+ }
+ }
+
+ if (USB_DEVICE_STRING_COUNT == langIndex)
+ {
+ langId = 0;
+ }
+ *buffer = (uint8_t *)g_UsbDeviceLanguageList.languageList[langId].string[langIndex];
+ *length = g_UsbDeviceLanguageList.languageList[langId].length[langIndex];
+ }
+ }
+ break;
+ case USB_DESCRIPTOR_TYPE_DEVICE:
+ {
+ *buffer = g_UsbDeviceDescriptor;
+ *length = USB_DESCRIPTOR_LENGTH_DEVICE;
+ }
+ break;
+ case USB_DESCRIPTOR_TYPE_CONFIGURE:
+ {
+ *buffer = g_UsbDeviceConfigurationDescriptor;
+ *length = USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL;
+ }
+ break;
+ default:
+ ret = kStatus_USB_InvalidRequest;
+ break;
+ } /* End Switch */
+ return ret;
+}
+
+/*!
+ * @brief Set the device configuration.
+ *
+ * The function is used to set the device configuration.
+ *
+ * @param handle The device handle.
+ * @param configure The configuration value.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceSetConfigure(usb_device_handle handle, uint8_t configure)
+{
+ if (!configure)
+ {
+ return kStatus_USB_Error;
+ }
+ g_currentConfigure = configure;
+ return USB_DeviceCallback(handle, kUSB_DeviceEventSetConfiguration, &configure);
+}
+
+/*!
+ * @brief Get the device configuration.
+ *
+ * The function is used to get the device configuration.
+ *
+ * @param handle The device handle.
+ * @param configure It is an OUT parameter, save the current configuration value.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceGetConfigure(usb_device_handle handle, uint8_t *configure)
+{
+ *configure = g_currentConfigure;
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief Set an interface alternate setting.
+ *
+ * The function is used to set an interface alternate setting.
+ *
+ * @param handle The device handle.
+ * @param interface The interface index.
+ * @param alternateSetting The new alternate setting value.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceSetInterface(usb_device_handle handle, uint8_t interface, uint8_t alternateSetting)
+{
+ g_interface[interface] = alternateSetting;
+ return USB_DeviceCallback(handle, kUSB_DeviceEventSetInterface, &interface);
+}
+
+/*!
+ * @brief Get an interface alternate setting.
+ *
+ * The function is used to get an interface alternate setting.
+ *
+ * @param handle The device handle.
+ * @param interface The interface index.
+ * @param alternateSetting It is an OUT parameter, save the new alternate setting value of the interface.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceGetInterface(usb_device_handle handle, uint8_t interface, uint8_t *alternateSetting)
+{
+ *alternateSetting = g_interface[interface];
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief USB device set speed function.
+ *
+ * This function sets the speed of the USB device.
+ *
+ * Due to the difference of HS and FS descriptors, the device descriptors and configurations need to be updated to match
+ * current speed.
+ * As the default, the device descriptors and configurations are configured by using FS parameters for both EHCI and
+ * KHCI.
+ * When the EHCI is enabled, the application needs to call this fucntion to update device by using current speed.
+ * The updated information includes endpoint max packet size, endpoint interval, etc.
+ *
+ * @param handle The USB device handle.
+ * @param speed Speed type. USB_SPEED_HIGH/USB_SPEED_FULL/USB_SPEED_LOW.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceSetSpeed(usb_device_handle handle, uint8_t speed)
+{
+ usb_descriptor_union_t *ptr1;
+ usb_descriptor_union_t *ptr2;
+
+ ptr1 = (usb_descriptor_union_t *)(&g_UsbDeviceConfigurationDescriptor[0]);
+ ptr2 = (usb_descriptor_union_t *)(&g_UsbDeviceConfigurationDescriptor[USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL - 1]);
+
+ while (ptr1 < ptr2)
+ {
+ if (ptr1->common.bDescriptorType == USB_DESCRIPTOR_TYPE_ENDPOINT)
+ {
+ if (USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT == (ptr1->endpoint.bEndpointAddress & 0x0FU))
+ {
+ if (USB_SPEED_HIGH == speed)
+ {
+ ptr1->endpoint.bInterval = HS_CDC_VCOM_INTERRUPT_IN_INTERVAL;
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE,
+ ptr1->endpoint.wMaxPacketSize);
+ }
+ else
+ {
+ ptr1->endpoint.bInterval = FS_CDC_VCOM_INTERRUPT_IN_INTERVAL;
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE,
+ ptr1->endpoint.wMaxPacketSize);
+ }
+ }
+ else if (USB_CDC_VCOM_BULK_IN_ENDPOINT == (ptr1->endpoint.bEndpointAddress & 0x0FU))
+ {
+ if (USB_SPEED_HIGH == speed)
+ {
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_BULK_IN_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize);
+ }
+ else
+ {
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_BULK_IN_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize);
+ }
+ }
+ else if (USB_CDC_VCOM_BULK_OUT_ENDPOINT == (ptr1->endpoint.bEndpointAddress & 0x0FU))
+ {
+ if (USB_SPEED_HIGH == speed)
+ {
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_BULK_OUT_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize);
+ }
+ else
+ {
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize);
+ }
+ }
+ else
+ {
+ }
+ }
+ ptr1 = (usb_descriptor_union_t *)((uint8_t *)ptr1 + ptr1->common.bLength);
+ }
+ return kStatus_USB_Success;
+}
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _USB_DEVICE_DESCRIPTOR_H_
+#define _USB_DEVICE_DESCRIPTOR_H_ 1
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+#define USB_DEVICE_SPECIFIC_BCD_VERSION (0x0200)
+#define USB_DEVICE_DEMO_BCD_VERSION (0x0101U)
+
+/* Communication Class Codes */
+#define CDC_COMM_CLASS (0x02)
+/* Data Class Codes */
+#define CDC_DATA_CLASS (0x0A)
+
+/* Communication Class SubClass Codes */
+#define USB_CDC_DIRECT_LINE_CONTROL_MODEL (0x01)
+#define USB_CDC_ABSTRACT_CONTROL_MODEL (0x02)
+#define USB_CDC_TELEPHONE_CONTROL_MODEL (0x03)
+#define USB_CDC_MULTI_CHANNEL_CONTROL_MODEL (0x04)
+#define USB_CDC_CAPI_CONTROL_MOPDEL (0x05)
+#define USB_CDC_ETHERNET_NETWORKING_CONTROL_MODEL (0x06)
+#define USB_CDC_ATM_NETWORKING_CONTROL_MODEL (0x07)
+#define USB_CDC_WIRELESS_HANDSET_CONTROL_MODEL (0x08)
+#define USB_CDC_DEVICE_MANAGEMENT (0x09)
+#define USB_CDC_MOBILE_DIRECT_LINE_MODEL (0x0A)
+#define USB_CDC_OBEX (0x0B)
+#define USB_CDC_ETHERNET_EMULATION_MODEL (0x0C)
+
+/* Communication Class Protocol Codes */
+#define USB_CDC_NO_CLASS_SPECIFIC_PROTOCOL (0x00) /*also for Data Class Protocol Code */
+#define USB_CDC_AT_250_PROTOCOL (0x01)
+#define USB_CDC_AT_PCCA_101_PROTOCOL (0x02)
+#define USB_CDC_AT_PCCA_101_ANNEX_O (0x03)
+#define USB_CDC_AT_GSM_7_07 (0x04)
+#define USB_CDC_AT_3GPP_27_007 (0x05)
+#define USB_CDC_AT_TIA_CDMA (0x06)
+#define USB_CDC_ETHERNET_EMULATION_PROTOCOL (0x07)
+#define USB_CDC_EXTERNAL_PROTOCOL (0xFE)
+#define USB_CDC_VENDOR_SPECIFIC (0xFF) /*also for Data Class Protocol Code */
+
+/* Data Class Protocol Codes */
+#define USB_CDC_PYHSICAL_INTERFACE_PROTOCOL (0x30)
+#define USB_CDC_HDLC_PROTOCOL (0x31)
+#define USB_CDC_TRANSPARENT_PROTOCOL (0x32)
+#define USB_CDC_MANAGEMENT_PROTOCOL (0x50)
+#define USB_CDC_DATA_LINK_Q931_PROTOCOL (0x51)
+#define USB_CDC_DATA_LINK_Q921_PROTOCOL (0x52)
+#define USB_CDC_DATA_COMPRESSION_V42BIS (0x90)
+#define USB_CDC_EURO_ISDN_PROTOCOL (0x91)
+#define USB_CDC_RATE_ADAPTION_ISDN_V24 (0x92)
+#define USB_CDC_CAPI_COMMANDS (0x93)
+#define USB_CDC_HOST_BASED_DRIVER (0xFD)
+#define USB_CDC_UNIT_FUNCTIONAL (0xFE)
+
+/* Descriptor SubType in Communications Class Functional Descriptors */
+#define USB_CDC_HEADER_FUNC_DESC (0x00)
+#define USB_CDC_CALL_MANAGEMENT_FUNC_DESC (0x01)
+#define USB_CDC_ABSTRACT_CONTROL_FUNC_DESC (0x02)
+#define USB_CDC_DIRECT_LINE_FUNC_DESC (0x03)
+#define USB_CDC_TELEPHONE_RINGER_FUNC_DESC (0x04)
+#define USB_CDC_TELEPHONE_REPORT_FUNC_DESC (0x05)
+#define USB_CDC_UNION_FUNC_DESC (0x06)
+#define USB_CDC_COUNTRY_SELECT_FUNC_DESC (0x07)
+#define USB_CDC_TELEPHONE_MODES_FUNC_DESC (0x08)
+#define USB_CDC_TERMINAL_FUNC_DESC (0x09)
+#define USB_CDC_NETWORK_CHANNEL_FUNC_DESC (0x0A)
+#define USB_CDC_PROTOCOL_UNIT_FUNC_DESC (0x0B)
+#define USB_CDC_EXTENSION_UNIT_FUNC_DESC (0x0C)
+#define USB_CDC_MULTI_CHANNEL_FUNC_DESC (0x0D)
+#define USB_CDC_CAPI_CONTROL_FUNC_DESC (0x0E)
+#define USB_CDC_ETHERNET_NETWORKING_FUNC_DESC (0x0F)
+#define USB_CDC_ATM_NETWORKING_FUNC_DESC (0x10)
+#define USB_CDC_WIRELESS_CONTROL_FUNC_DESC (0x11)
+#define USB_CDC_MOBILE_DIRECT_LINE_FUNC_DESC (0x12)
+#define USB_CDC_MDLM_DETAIL_FUNC_DESC (0x13)
+#define USB_CDC_DEVICE_MANAGEMENT_FUNC_DESC (0x14)
+#define USB_CDC_OBEX_FUNC_DESC (0x15)
+#define USB_CDC_COMMAND_SET_FUNC_DESC (0x16)
+#define USB_CDC_COMMAND_SET_DETAIL_FUNC_DESC (0x17)
+#define USB_CDC_TELEPHONE_CONTROL_FUNC_DESC (0x18)
+#define USB_CDC_OBEX_SERVICE_ID_FUNC_DESC (0x19)
+
+/* usb descritpor length */
+#define USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL (67)
+#define USB_DESCRIPTOR_LENGTH_CDC_HEADER_FUNC (5)
+#define USB_DESCRIPTOR_LENGTH_CDC_CALL_MANAG (5)
+#define USB_DESCRIPTOR_LENGTH_CDC_ABSTRACT (4)
+#define USB_DESCRIPTOR_LENGTH_CDC_UNION_FUNC (5)
+
+#define USB_DEVICE_CONFIGURATION_COUNT (1)
+#define USB_DEVICE_STRING_COUNT (3)
+#define USB_DEVICE_LANGUAGE_COUNT (1)
+
+#define USB_CDC_VCOM_CONFIGURE_INDEX (1)
+
+#define USB_CDC_VCOM_ENDPOINT_CIC_COUNT (1)
+#define USB_CDC_VCOM_ENDPOINT_DIC_COUNT (2)
+#define USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT (1)
+#define USB_CDC_VCOM_BULK_IN_ENDPOINT (2)
+#define USB_CDC_VCOM_BULK_OUT_ENDPOINT (3)
+#define USB_CDC_VCOM_INTERFACE_COUNT (2)
+#define USB_CDC_VCOM_COMM_INTERFACE_INDEX (0)
+#define USB_CDC_VCOM_DATA_INTERFACE_INDEX (1)
+
+#define HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE (16)
+#define FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE (16)
+#define HS_CDC_VCOM_INTERRUPT_IN_INTERVAL (0x07) /* 2^(7-1) = 8ms */
+#define FS_CDC_VCOM_INTERRUPT_IN_INTERVAL (0x08)
+#define HS_CDC_VCOM_BULK_IN_PACKET_SIZE (512)
+#define FS_CDC_VCOM_BULK_IN_PACKET_SIZE (64)
+#define HS_CDC_VCOM_BULK_OUT_PACKET_SIZE (512)
+#define FS_CDC_VCOM_BULK_OUT_PACKET_SIZE (64)
+
+#define USB_DESCRIPTOR_LENGTH_STRING0 (4)
+#define USB_DESCRIPTOR_LENGTH_STRING1 (38)
+#define USB_DESCRIPTOR_LENGTH_STRING2 (42)
+
+#define USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE (0x24)
+#define USB_DESCRIPTOR_TYPE_CDC_CS_ENDPOINT (0x25)
+
+#define USB_DEVICE_CLASS (0x02)
+#define USB_DEVICE_SUBCLASS (0x00)
+#define USB_DEVICE_PROTOCOL (0x00)
+
+#define USB_DEVICE_MAX_POWER (0x32)
+
+#define USB_CDC_VCOM_CIC_CLASS (CDC_COMM_CLASS)
+#define USB_CDC_VCOM_CIC_SUBCLASS (USB_CDC_ABSTRACT_CONTROL_MODEL)
+#define USB_CDC_VCOM_CIC_PROTOCOL (USB_CDC_NO_CLASS_SPECIFIC_PROTOCOL)
+
+#define USB_CDC_VCOM_DIC_CLASS (CDC_DATA_CLASS)
+#define USB_CDC_VCOM_DIC_SUBCLASS (0x00)
+#define USB_CDC_VCOM_DIC_PROTOCOL (USB_CDC_NO_CLASS_SPECIFIC_PROTOCOL)
+
+/*******************************************************************************
+* API
+******************************************************************************/
+/*!
+ * @brief USB device callback function.
+ *
+ * This function handles the usb device specific requests.
+ *
+ * @param handle The USB device handle.
+ * @param event The USB device event type.
+ * @param param The parameter of the device specific request.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceCallback(usb_device_handle handle, uint32_t event, void *param);
+
+/*!
+ * @brief USB device set speed function.
+ *
+ * This function sets the speed of the USB device.
+ *
+ * Due to the difference of HS and FS descriptors, the device descriptors and configurations need to be updated to match
+ * current speed.
+ * As the default, the device descriptors and configurations are configured by using FS parameters for both EHCI and
+ * KHCI.
+ * When the EHCI is enabled, the application needs to call this fucntion to update device by using current speed.
+ * The updated information includes endpoint max packet size, endpoint interval, etc.
+ *
+ * @param handle The USB device handle.
+ * @param speed Speed type. USB_SPEED_HIGH/USB_SPEED_FULL/USB_SPEED_LOW.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceSetSpeed(usb_device_handle handle, uint8_t speed);
+
+#endif /* _USB_DEVICE_DESCRIPTOR_H_ */
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 - 2018 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "usb_device_config.h"
+#include "usb.h"
+
+#include "usb_device.h"
+
+#include "fsl_device_registers.h"
+
+#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
+
+#include "usb_khci.h"
+#include "usb_device_dci.h"
+
+#include "usb_device_khci.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM > 0U)
+
+/* USB_STACK_USE_DEDICATED_RAM */
+#if defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U)
+
+#if (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL)
+#if (FSL_FEATURE_USB_KHCI_USB_RAM > 512U)
+#else
+#error The dedicated RAM length is not more than 512 Bytes, the SOC does not support this case.
+#endif
+#endif /* USB_STACK_USE_DEDICATED_RAM */
+
+#else
+#error The SOC does not suppoort dedicated RAM case.
+#endif /* USB_STACK_USE_DEDICATED_RAM */
+
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static usb_status_t USB_DeviceKhciEndpointTransfer(
+ usb_device_khci_state_struct_t *khciState, uint8_t endpoint, uint8_t direction, uint8_t *buffer, uint32_t length);
+static void USB_DeviceKhciPrimeNextSetup(usb_device_khci_state_struct_t *khciState);
+static void USB_DeviceKhciSetDefaultState(usb_device_khci_state_struct_t *khciState);
+static usb_status_t USB_DeviceKhciEndpointInit(usb_device_khci_state_struct_t *khciState,
+ usb_device_endpoint_init_struct_t *epInit);
+static usb_status_t USB_DeviceKhciEndpointDeinit(usb_device_khci_state_struct_t *khciState, uint8_t ep);
+static usb_status_t USB_DeviceKhciEndpointStall(usb_device_khci_state_struct_t *khciState, uint8_t ep);
+static usb_status_t USB_DeviceKhciEndpointUnstall(usb_device_khci_state_struct_t *khciState, uint8_t ep);
+static void USB_DeviceKhciInterruptTokenDone(usb_device_khci_state_struct_t *khciState);
+static void USB_DeviceKhciInterruptReset(usb_device_khci_state_struct_t *khciState);
+#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+static void USB_DeviceKhciInterruptSleep(usb_device_khci_state_struct_t *khciState);
+static void USB_DeviceKhciInterruptResume(usb_device_khci_state_struct_t *khciState);
+#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */
+static void USB_DeviceKhciInterruptStall(usb_device_khci_state_struct_t *khciState);
+#if defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U)
+static void USB_DeviceKhciInterruptError(usb_device_khci_state_struct_t *khciState);
+#endif /* USB_DEVICE_CONFIG_ERROR_HANDLING */
+
+extern usb_status_t USB_DeviceNotificationTrigger(void *handle, void *msg);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Apply for BDT buffer, 512-byte alignment */
+USB_BDT USB_RAM_ADDRESS_ALIGNMENT(512) static uint8_t s_UsbDeviceKhciBdtBuffer[USB_DEVICE_CONFIG_KHCI][512U];
+
+/* Apply for khci device state structure */
+USB_GLOBAL USB_RAM_ADDRESS_ALIGNMENT(USB_DATA_ALIGN_SIZE) static usb_device_khci_state_struct_t
+ s_UsbDeviceKhciState[USB_DEVICE_CONFIG_KHCI];
+
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \
+ (defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U))
+/* Apply for device dcd state structure */
+USB_GLOBAL USB_RAM_ADDRESS_ALIGNMENT(USB_DATA_ALIGN_SIZE) static usb_device_dcd_state_struct_t
+ s_UsbDeviceDcdState[USB_DEVICE_CONFIG_KHCI];
+#endif
+
+/* Apply for KHCI DMA aligned buffer when marco USB_DEVICE_CONFIG_KHCI_DMA_ALIGN enabled */
+USB_GLOBAL USB_RAM_ADDRESS_ALIGNMENT(USB_DATA_ALIGN_SIZE) static uint32_t s_UsbDeviceKhciDmaAlignBuffer
+ [USB_DEVICE_CONFIG_KHCI][((USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH - 1U) >> 2U) + 1U];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Write the BDT to start a transfer.
+ *
+ * The function is used to start a transfer by writing the BDT.
+ *
+ * @param khciState Pointer of the device KHCI state structure.
+ * @param endpoint Endpoint number.
+ * @param direction The direction of the endpoint, 0U - USB_OUT, 1U - USB_IN.
+ * @param buffer The memory address to save the received data, or the memory address to hold the data need to
+ * be sent.
+ * @param length The length of the data.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceKhciEndpointTransfer(
+ usb_device_khci_state_struct_t *khciState, uint8_t endpoint, uint8_t direction, uint8_t *buffer, uint32_t length)
+{
+ uint32_t index = ((uint32_t)endpoint << 1U) | (uint32_t)direction;
+ USB_OSA_SR_ALLOC();
+
+ /* Enter critical */
+ USB_OSA_ENTER_CRITICAL();
+
+ /* Flag the endpoint is busy. */
+ khciState->endpointState[index].stateUnion.stateBitField.transferring = 1U;
+
+ /* Add the data buffer address to the BDT. */
+ USB_KHCI_BDT_SET_ADDRESS((uint32_t)khciState->bdt, endpoint, direction,
+ khciState->endpointState[index].stateUnion.stateBitField.bdtOdd, (uint32_t)buffer);
+
+ /* Change the BDT control field to start the transfer. */
+ USB_KHCI_BDT_SET_CONTROL(
+ (uint32_t)khciState->bdt, endpoint, direction, khciState->endpointState[index].stateUnion.stateBitField.bdtOdd,
+ USB_LONG_TO_LITTLE_ENDIAN(USB_KHCI_BDT_BC(length) | USB_KHCI_BDT_OWN | USB_KHCI_BDT_DTS |
+ USB_KHCI_BDT_DATA01(khciState->endpointState[index].stateUnion.stateBitField.data0)));
+
+ /* Exit critical */
+ USB_OSA_EXIT_CRITICAL();
+
+ /* Clear the token busy state */
+ khciState->registerBase->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief Prime a next setup transfer.
+ *
+ * The function is used to prime a buffer in control out pipe to wait for receiving the host's setup packet.
+ *
+ * @param khciState Pointer of the device KHCI state structure.
+ *
+ */
+static void USB_DeviceKhciPrimeNextSetup(usb_device_khci_state_struct_t *khciState)
+{
+/* Update the endpoint state */
+/* Save the buffer address used to receive the setup packet. */
+#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \
+ defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \
+ defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U)
+ /* In case of lowpower mode enabled, it requires to put the setup packet buffer(16 bytes) into the USB RAM so
+ * that the setup packet would wake up the USB.
+ */
+ khciState->endpointState[(USB_CONTROL_ENDPOINT << 1U) | USB_OUT].transferBuffer =
+ (uint8_t *)(khciState->bdt + 0x200U - 0x10U) +
+ khciState->endpointState[(USB_CONTROL_ENDPOINT << 1U) | USB_OUT].stateUnion.stateBitField.bdtOdd *
+ USB_SETUP_PACKET_SIZE;
+#else
+ khciState->endpointState[(USB_CONTROL_ENDPOINT << 1U) | USB_OUT].transferBuffer =
+ (uint8_t *)&khciState->setupPacketBuffer[0] +
+ khciState->endpointState[(USB_CONTROL_ENDPOINT << 1U) | USB_OUT].stateUnion.stateBitField.bdtOdd *
+ USB_SETUP_PACKET_SIZE;
+#endif
+ /* Clear the transferred length. */
+ khciState->endpointState[(USB_CONTROL_ENDPOINT << 1U) | USB_OUT].transferDone = 0U;
+ /* Save the data length expected to get from a host. */
+ khciState->endpointState[(USB_CONTROL_ENDPOINT << 1U) | USB_OUT].transferLength = USB_SETUP_PACKET_SIZE;
+ /* Save the data buffer DMA align flag. */
+ khciState->endpointState[(USB_CONTROL_ENDPOINT << 1U) | USB_OUT].stateUnion.stateBitField.dmaAlign = 1U;
+ /* Set the DATA0/1 to DATA0. */
+ khciState->endpointState[(USB_CONTROL_ENDPOINT << 1U) | USB_OUT].stateUnion.stateBitField.data0 = 0U;
+
+ USB_DeviceKhciEndpointTransfer(khciState, USB_CONTROL_ENDPOINT, USB_OUT,
+ khciState->endpointState[(USB_CONTROL_ENDPOINT << 1U) | USB_OUT].transferBuffer,
+ USB_SETUP_PACKET_SIZE);
+}
+
+/*!
+ * @brief Set device controller state to default state.
+ *
+ * The function is used to set device controller state to default state.
+ * The function will be called when USB_DeviceKhciInit called or the control type kUSB_DeviceControlGetEndpointStatus
+ * received in USB_DeviceKhciControl.
+ *
+ * @param khciState Pointer of the device KHCI state structure.
+ *
+ */
+static void USB_DeviceKhciSetDefaultState(usb_device_khci_state_struct_t *khciState)
+{
+ uint8_t interruptFlag;
+
+ /* Clear the error state register */
+ khciState->registerBase->ERRSTAT = 0xFFU;
+
+ /* Setting this bit to 1U resets all the BDT ODD ping/pong fields to 0U, which then specifies the EVEN BDT bank. */
+ khciState->registerBase->CTL |= USB_CTL_ODDRST_MASK;
+
+ /* Clear the device address */
+ khciState->registerBase->ADDR = 0U;
+
+ /* Clear the endpoint state and disable the endpoint */
+ for (uint8_t count = 0U; count < USB_DEVICE_CONFIG_ENDPOINTS; count++)
+ {
+ USB_KHCI_BDT_SET_CONTROL((uint32_t)khciState->bdt, count, USB_OUT, 0U, 0U);
+ USB_KHCI_BDT_SET_CONTROL((uint32_t)khciState->bdt, count, USB_OUT, 1U, 0U);
+ USB_KHCI_BDT_SET_CONTROL((uint32_t)khciState->bdt, count, USB_IN, 0U, 0U);
+ USB_KHCI_BDT_SET_CONTROL((uint32_t)khciState->bdt, count, USB_IN, 1U, 0U);
+
+ khciState->endpointState[((uint32_t)count << 1U) | USB_OUT].stateUnion.state = 0U;
+ khciState->endpointState[((uint32_t)count << 1U) | USB_IN].stateUnion.state = 0U;
+ khciState->registerBase->ENDPOINT[count].ENDPT = 0x00U;
+ }
+ khciState->isDmaAlignBufferInusing = 0U;
+
+ /* Clear the BDT odd reset flag */
+ khciState->registerBase->CTL &= ~USB_CTL_ODDRST_MASK;
+
+ /* Enable all error */
+ khciState->registerBase->ERREN = 0xFFU;
+
+ /* Enable reset, sof, token, stall interrupt */
+ interruptFlag = kUSB_KhciInterruptReset
+#if 0U
+ | kUSB_KhciInterruptSofToken
+#endif
+ | kUSB_KhciInterruptTokenDone | kUSB_KhciInterruptStall;
+
+#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+ /* Enable suspend interruprt */
+ interruptFlag |= kUSB_KhciInterruptSleep;
+#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */
+
+#if defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U)
+ /* Enable error interruprt */
+ interruptFlag |= kUSB_KhciInterruptError;
+#endif /* USB_DEVICE_CONFIG_ERROR_HANDLING */
+ /* Write the interrupt enable register */
+ khciState->registerBase->INTEN = interruptFlag;
+
+ /* Clear reset flag */
+ khciState->isResetting = 0U;
+
+ khciState->registerBase->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
+}
+
+/*!
+ * @brief Initialize a specified endpoint.
+ *
+ * The function is used to initialize a specified endpoint.
+ *
+ * @param khciState Pointer of the device KHCI state structure.
+ * @param epInit The endpoint initialization structure pointer.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceKhciEndpointInit(usb_device_khci_state_struct_t *khciState,
+ usb_device_endpoint_init_struct_t *epInit)
+{
+ uint16_t maxPacketSize = epInit->maxPacketSize;
+ uint8_t endpoint = (epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK);
+ uint8_t direction = (epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >>
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT;
+ uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | (uint8_t)direction;
+
+ /* Make the endpoint max packet size align with USB Specification 2.0. */
+ if (USB_ENDPOINT_ISOCHRONOUS == epInit->transferType)
+ {
+ if (maxPacketSize > USB_DEVICE_MAX_FS_ISO_MAX_PACKET_SIZE)
+ {
+ maxPacketSize = USB_DEVICE_MAX_FS_ISO_MAX_PACKET_SIZE;
+ }
+ }
+ else
+ {
+ if (maxPacketSize > USB_DEVICE_MAX_FS_NONE_ISO_MAX_PACKET_SIZE)
+ {
+ maxPacketSize = USB_DEVICE_MAX_FS_NONE_ISO_MAX_PACKET_SIZE;
+ }
+ /* Enable an endpoint to perform handshaking during a transaction to this endpoint. */
+ khciState->registerBase->ENDPOINT[endpoint].ENDPT |= USB_ENDPT_EPHSHK_MASK;
+ }
+ /* Set the endpoint idle */
+ khciState->endpointState[index].stateUnion.stateBitField.transferring = 0U;
+ /* Save the max packet size of the endpoint */
+ khciState->endpointState[index].stateUnion.stateBitField.maxPacketSize = maxPacketSize;
+ /* Set the data toggle to DATA0 */
+ khciState->endpointState[index].stateUnion.stateBitField.data0 = 0U;
+ /* Clear the endpoint stalled state */
+ khciState->endpointState[index].stateUnion.stateBitField.stalled = 0U;
+ /* Set the ZLT field */
+ khciState->endpointState[index].stateUnion.stateBitField.zlt = epInit->zlt;
+ /* Enable the endpoint. */
+ khciState->registerBase->ENDPOINT[endpoint].ENDPT |=
+ (USB_IN == direction) ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
+#if defined(FSL_FEATURE_USB_KHCI_HAS_STALL_LOW) && (FSL_FEATURE_USB_KHCI_HAS_STALL_LOW > 0U)
+ /*control endpoint bidirection stall default state shoule be enable, iso doesn't support stall*/
+ if ((USB_ENDPOINT_BULK == epInit->transferType) || (USB_ENDPOINT_INTERRUPT == epInit->transferType))
+ {
+ if(USB_IN == direction)
+ {
+ if (endpoint < 8)
+ {
+ khciState->registerBase->STALL_IL_DIS |= (1<<endpoint);
+ }
+#if defined(FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH) && (FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH > 0U)
+ else if ((endpoint >= 8) && (endpoint < 16))
+ {
+ khciState->registerBase->STALL_IH_DIS |= (1<<(endpoint-8));
+ }
+#endif
+ }
+ else
+ {
+ if (endpoint < 8)
+ {
+ khciState->registerBase->STALL_OL_DIS |= (1<<endpoint);
+ }
+#if defined(FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH) && (FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH > 0U)
+ else if ((endpoint >= 8) && (endpoint < 16))
+ {
+ khciState->registerBase->STALL_OH_DIS |= (1<<(endpoint-8));
+ }
+#endif
+ }
+ }
+ else if ((USB_ENDPOINT_CONTROL == epInit->transferType))
+ {
+ khciState->registerBase->STALL_IL_DIS &= ~(1<<endpoint);
+ khciState->registerBase->STALL_OL_DIS &= ~(1<<endpoint);
+ }
+ else
+ {
+ }
+#endif
+
+ /* Prime a transfer to receive next setup packet when the endpoint is control out endpoint. */
+ if ((USB_CONTROL_ENDPOINT == endpoint) && (USB_OUT == direction))
+ {
+ USB_DeviceKhciPrimeNextSetup(khciState);
+ }
+
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief De-initialize a specified endpoint.
+ *
+ * The function is used to de-initialize a specified endpoint.
+ * Current transfer of the endpoint will be canceled and the specified endpoint will be disabled.
+ *
+ * @param khciState Pointer of the device KHCI state structure.
+ * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceKhciEndpointDeinit(usb_device_khci_state_struct_t *khciState, uint8_t ep)
+{
+ uint8_t endpoint = (ep & USB_ENDPOINT_NUMBER_MASK);
+ uint8_t direction =
+ (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT;
+ uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | (uint8_t)direction;
+
+ /* Cancel the transfer of the endpoint */
+ USB_DeviceKhciCancel(khciState, ep);
+
+ /* Disable the endpoint */
+ khciState->registerBase->ENDPOINT[endpoint].ENDPT = 0x00U;
+ /* Clear the max packet size */
+ khciState->endpointState[index].stateUnion.stateBitField.maxPacketSize = 0U;
+
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief Stall a specified endpoint.
+ *
+ * The function is used to stall a specified endpoint.
+ * Current transfer of the endpoint will be canceled and the specified endpoint will be stalled.
+ *
+ * @param khciState Pointer of the device KHCI state structure.
+ * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceKhciEndpointStall(usb_device_khci_state_struct_t *khciState, uint8_t ep)
+{
+ uint8_t endpoint = ep & USB_ENDPOINT_NUMBER_MASK;
+ uint8_t direction =
+ (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT;
+ uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | (uint8_t)direction;
+
+ /* Cancel the transfer of the endpoint */
+ USB_DeviceKhciCancel(khciState, ep);
+
+ /* Set endpoint stall flag. */
+ khciState->endpointState[index].stateUnion.stateBitField.stalled = 1U;
+#if defined(FSL_FEATURE_USB_KHCI_HAS_STALL_LOW) && (FSL_FEATURE_USB_KHCI_HAS_STALL_LOW > 0U)
+ if (USB_CONTROL_ENDPOINT != endpoint)
+ {
+ if(USB_IN == direction)
+ {
+ if (endpoint < 8)
+ {
+ khciState->registerBase->STALL_IL_DIS &= ~(1<<endpoint);
+ }
+#if defined(FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH) && (FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH > 0U)
+ else if ((endpoint >= 8) && (endpoint < 16))
+ {
+ khciState->registerBase->STALL_IH_DIS &= ~(1<<(endpoint-8));
+ }
+#endif
+ }
+ else
+ {
+ if (endpoint < 8)
+ {
+ khciState->registerBase->STALL_OL_DIS &= ~(1<<endpoint);
+ }
+#if defined(FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH) && (FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH > 0U)
+ else if ((endpoint >= 8) && (endpoint < 16))
+ {
+ khciState->registerBase->STALL_OH_DIS &= ~(1<<(endpoint-8));
+ }
+#endif
+ }
+ }
+#endif
+ /* Set endpoint stall in BDT. And then if the host send a IN/OUT tanscation, the device will response a STALL state.
+ */
+ USB_KHCI_BDT_SET_CONTROL(
+ (uint32_t)khciState->bdt, endpoint, direction, khciState->endpointState[index].stateUnion.stateBitField.bdtOdd,
+ USB_LONG_TO_LITTLE_ENDIAN(
+ (uint32_t)(USB_KHCI_BDT_BC(khciState->endpointState[index].stateUnion.stateBitField.maxPacketSize) |
+ USB_KHCI_BDT_DTS | USB_KHCI_BDT_STALL | USB_KHCI_BDT_OWN)));
+
+ khciState->registerBase->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
+
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief Un-stall a specified endpoint.
+ *
+ * The function is used to un-stall a specified endpoint.
+ * Current transfer of the endpoint will be canceled and the specified endpoint will be un-stalled.
+ *
+ * @param khciState Pointer of the device KHCI state structure.
+ * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceKhciEndpointUnstall(usb_device_khci_state_struct_t *khciState, uint8_t ep)
+{
+ uint8_t endpoint = ep & USB_ENDPOINT_NUMBER_MASK;
+ uint8_t direction =
+ (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT;
+ uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | (uint8_t)direction;
+
+ /* Clear the endpoint stall state */
+ khciState->endpointState[index].stateUnion.stateBitField.stalled = 0U;
+ /* Reset the endpoint data toggle to DATA0 */
+ khciState->endpointState[index].stateUnion.stateBitField.data0 = 0U;
+
+ /* Clear stall state in BDT */
+ for (uint8_t i = 0U; i < 2U; i++)
+ {
+ USB_KHCI_BDT_SET_CONTROL(
+ (uint32_t)khciState->bdt, endpoint, direction, i,
+ USB_LONG_TO_LITTLE_ENDIAN(
+ (uint32_t)(USB_KHCI_BDT_BC(khciState->endpointState[index].stateUnion.stateBitField.maxPacketSize) |
+ USB_KHCI_BDT_DTS | USB_KHCI_BDT_DATA01(0U))));
+ }
+
+ /* Clear stall state in endpoint control register */
+ khciState->registerBase->ENDPOINT[endpoint].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
+#if defined(FSL_FEATURE_USB_KHCI_HAS_STALL_LOW) && (FSL_FEATURE_USB_KHCI_HAS_STALL_LOW > 0U)
+ if (USB_CONTROL_ENDPOINT != endpoint)
+ {
+ if(USB_IN == direction)
+ {
+ if (endpoint < 8)
+ {
+ khciState->registerBase->STALL_IL_DIS |= (1<<endpoint);
+ }
+#if defined(FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH) && (FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH > 0U)
+ else if ((endpoint >= 8) && (endpoint < 16))
+ {
+ khciState->registerBase->STALL_IH_DIS |= (1<<(endpoint-8));
+ }
+#endif
+ }
+ else
+ {
+ if (endpoint < 8)
+ {
+ khciState->registerBase->STALL_OL_DIS |= (1<<endpoint);
+ }
+#if defined(FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH) && (FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH > 0U)
+ else if ((endpoint >= 8) && (endpoint < 16))
+ {
+ khciState->registerBase->STALL_OH_DIS |= (1<<(endpoint-8));
+ }
+#endif
+ }
+ }
+#endif
+ if ((USB_CONTROL_ENDPOINT != endpoint))
+ {
+ /* Cancel the transfer of the endpoint */
+ USB_DeviceKhciCancel(khciState, ep);
+ }
+
+ /* Prime a transfer to receive next setup packet when the endpoint is a control out endpoint. */
+ if ((USB_CONTROL_ENDPOINT == endpoint) && (USB_OUT == direction))
+ {
+ USB_DeviceKhciPrimeNextSetup(khciState);
+ }
+
+ khciState->registerBase->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
+
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief Handle the token done interrupt.
+ *
+ * The function is used to handle the token done interrupt.
+ *
+ * @param khciState Pointer of the device KHCI state structure.
+ *
+ */
+static void USB_DeviceKhciInterruptTokenDone(usb_device_khci_state_struct_t *khciState)
+{
+ uint32_t control;
+ uint32_t length;
+ uint32_t remainingLength;
+ uint8_t *bdtBuffer;
+ usb_device_callback_message_struct_t message;
+ uint8_t endpoint;
+ uint8_t direction;
+ uint8_t bdtOdd;
+ uint8_t isSetup;
+ uint8_t index;
+ uint8_t stateRegister = khciState->registerBase->STAT;
+
+ /* Get the endpoint number to identify which one triggers the token done interrupt. */
+ endpoint = (stateRegister & USB_STAT_ENDP_MASK) >> USB_STAT_ENDP_SHIFT;
+
+ /* Get the direction of the endpoint number. */
+ direction = (stateRegister & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT;
+
+ /* Get the finished BDT ODD. */
+ bdtOdd = (stateRegister & USB_STAT_ODD_MASK) >> USB_STAT_ODD_SHIFT;
+
+ /* Clear token done interrupt flag. */
+ khciState->registerBase->ISTAT = kUSB_KhciInterruptTokenDone;
+
+ /* Get the Control field of the BDT element according to the endpoint number, the direction and finished BDT ODD. */
+ control = USB_KHCI_BDT_GET_CONTROL((uint32_t)khciState->bdt, endpoint, direction, bdtOdd);
+
+ /* Get the buffer field of the BDT element according to the endpoint number, the direction and finished BDT ODD. */
+ bdtBuffer = (uint8_t *)USB_KHCI_BDT_GET_ADDRESS((uint32_t)khciState->bdt, endpoint, direction, bdtOdd);
+
+ /* Get the transferred length. */
+ length = ((USB_LONG_FROM_LITTLE_ENDIAN(control)) >> 16U) & 0x3FFU;
+
+ /* Get the transferred length. */
+ isSetup = (USB_KHCI_BDT_DEVICE_SETUP_TOKEN == ((uint8_t)(((USB_LONG_FROM_LITTLE_ENDIAN(control)) >> 2U) & 0x0FU))) ?
+ 1U :
+ 0U;
+
+ index = ((uint8_t)((uint32_t)endpoint << 1U)) | (uint8_t)direction;
+
+ if (0U == khciState->endpointState[index].stateUnion.stateBitField.transferring)
+ {
+ return;
+ }
+
+ if (isSetup)
+ {
+ khciState->setupBufferIndex = bdtOdd;
+ }
+
+ /* USB_IN, Send completed */
+ if (direction == USB_IN)
+ {
+ /* The transferred length */
+ khciState->endpointState[index].transferDone += length;
+
+ /* Remaining length */
+ remainingLength = khciState->endpointState[index].transferLength - khciState->endpointState[index].transferDone;
+
+ /* Change the data toggle flag */
+ khciState->endpointState[index].stateUnion.stateBitField.data0 ^= 1U;
+ /* Change the BDT odd toggle flag */
+ khciState->endpointState[index].stateUnion.stateBitField.bdtOdd ^= 1U;
+
+ /* Whether the transfer is completed or not. */
+ /*
+ * The transfer is completed when one of the following conditions meet:
+ * 1. The remaining length is zero.
+ * 2. The length of current transcation is less than the max packet size of the current pipe.
+ */
+ if ((0U == remainingLength) ||
+ (khciState->endpointState[index].stateUnion.stateBitField.maxPacketSize > length))
+ {
+ message.length = khciState->endpointState[index].transferDone;
+ message.buffer = khciState->endpointState[index].transferBuffer;
+ khciState->endpointState[index].stateUnion.stateBitField.transferring = 0U;
+
+ /*
+ * Whether need to send ZLT when the pipe is control in pipe and the transferred length of current
+ * transaction equals to max packet size.
+ */
+ if ((length) && (!(length % khciState->endpointState[index].stateUnion.stateBitField.maxPacketSize)))
+ {
+ if (USB_CONTROL_ENDPOINT == endpoint)
+ {
+ usb_setup_struct_t *setup_packet =
+ (usb_setup_struct_t
+ *)(&khciState->setupPacketBuffer[(USB_SETUP_PACKET_SIZE * khciState->setupBufferIndex)]);
+ /*
+ * Send the ZLT and terminate the token done interrupt service when the tranferred length in data
+ * phase
+ * is less than the host request.
+ */
+ if (USB_SHORT_FROM_LITTLE_ENDIAN(setup_packet->wLength) >
+ khciState->endpointState[index].transferLength)
+ {
+ (void)USB_DeviceKhciEndpointTransfer(khciState, endpoint, USB_IN, (uint8_t *)NULL, 0U);
+ return;
+ }
+ }
+ else if (khciState->endpointState[index].stateUnion.stateBitField.zlt)
+ {
+ (void)USB_DeviceKhciEndpointTransfer(khciState, endpoint, USB_IN, (uint8_t *)NULL, 0U);
+ return;
+ }
+ else
+ {
+ }
+ }
+ }
+ else
+ {
+ /* Send remaining data and terminate the token done interrupt service. */
+ (void)USB_DeviceKhciSend(khciState, endpoint | (USB_IN << 0x07U),
+ khciState->endpointState[index].transferBuffer, remainingLength);
+ return;
+ }
+ }
+ else
+ {
+ if ((USB_CONTROL_ENDPOINT == endpoint) && (0U == length))
+ {
+ message.length = 0U;
+ message.buffer = (uint8_t *)NULL;
+ }
+ else
+ {
+ if (0U == khciState->endpointState[index].stateUnion.stateBitField.dmaAlign)
+ {
+ uint8_t *buffer = (uint8_t *)USB_LONG_FROM_LITTLE_ENDIAN(
+ USB_KHCI_BDT_GET_ADDRESS((uint32_t)khciState->bdt, endpoint, USB_OUT,
+ khciState->endpointState[index].stateUnion.stateBitField.bdtOdd));
+ uint8_t *transferBuffer =
+ khciState->endpointState[index].transferBuffer + khciState->endpointState[index].transferDone;
+ if (buffer != transferBuffer)
+ {
+ for (uint32_t i = 0U; i < length; i++)
+ {
+ transferBuffer[i] = buffer[i];
+ }
+ }
+ khciState->isDmaAlignBufferInusing = 0U;
+ }
+ /* The transferred length */
+ khciState->endpointState[index].transferDone += length;
+ /* Remaining length */
+ remainingLength =
+ khciState->endpointState[index].transferLength - khciState->endpointState[index].transferDone;
+
+ if ((USB_CONTROL_ENDPOINT == endpoint) && isSetup)
+ {
+ khciState->endpointState[(USB_CONTROL_ENDPOINT << 1U) | USB_OUT].stateUnion.stateBitField.data0 = 1U;
+ khciState->endpointState[(USB_CONTROL_ENDPOINT << 1U) | USB_IN].stateUnion.stateBitField.data0 = 1U;
+ }
+ else
+ {
+ khciState->endpointState[index].stateUnion.stateBitField.data0 ^= 1U;
+ }
+ khciState->endpointState[index].stateUnion.stateBitField.bdtOdd ^= 1U;
+ if ((!khciState->endpointState[index].transferLength) || (!remainingLength) ||
+ (khciState->endpointState[index].stateUnion.stateBitField.maxPacketSize > length))
+ {
+ message.length = khciState->endpointState[index].transferDone;
+ if (isSetup)
+ {
+ message.buffer = bdtBuffer;
+ }
+ else
+ {
+ message.buffer = khciState->endpointState[index].transferBuffer;
+ }
+ khciState->endpointState[index].stateUnion.stateBitField.transferring = 0U;
+ }
+ else
+ {
+ /* Receive remaining data and terminate the token done interrupt service. */
+ USB_DeviceKhciRecv(khciState, (endpoint) | (USB_OUT << 0x07U),
+ khciState->endpointState[index].transferBuffer, remainingLength);
+ return;
+ }
+ }
+ }
+
+ message.isSetup = isSetup;
+ message.code = (endpoint) | (uint8_t)(((uint32_t)direction << 0x07U));
+
+ /* Notify the up layer the KHCI status changed. */
+ USB_DeviceNotificationTrigger(khciState->deviceHandle, &message);
+
+ khciState->registerBase->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
+}
+
+/*!
+ * @brief Handle the USB bus reset interrupt.
+ *
+ * The function is used to handle the USB bus reset interrupt.
+ *
+ * @param khciState Pointer of the device KHCI state structure.
+ *
+ */
+static void USB_DeviceKhciInterruptReset(usb_device_khci_state_struct_t *khciState)
+{
+ usb_device_callback_message_struct_t message;
+
+ /* Set KHCI reset flag */
+ khciState->isResetting = 1U;
+
+ /* Clear the reset interrupt */
+ khciState->registerBase->ISTAT = (kUSB_KhciInterruptReset);
+#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+ /* Clear the suspend interrupt */
+ khciState->registerBase->ISTAT = (kUSB_KhciInterruptSleep);
+ khciState->registerBase->USBCTRL &= ~USB_USBCTRL_SUSP_MASK;
+#endif
+
+ message.buffer = (uint8_t *)NULL;
+ message.code = kUSB_DeviceNotifyBusReset;
+ message.length = 0U;
+ message.isSetup = 0U;
+ /* Notify up layer the USB bus reset signal detected. */
+ USB_DeviceNotificationTrigger(khciState->deviceHandle, &message);
+}
+
+/* The USB suspend and resume signals need to be detected and handled when the low power or remote wakeup function
+ * enabled. */
+#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+
+/*!
+ * @brief Handle the suspend interrupt.
+ *
+ * The function is used to handle the suspend interrupt when the suspend signal detected.
+ *
+ * @param khciState Pointer of the device KHCI state structure.
+ *
+ */
+static void USB_DeviceKhciInterruptSleep(usb_device_khci_state_struct_t *khciState)
+{
+ usb_device_callback_message_struct_t message;
+
+ /* Enable the resume interrupt */
+ khciState->registerBase->INTEN |= kUSB_KhciInterruptResume;
+ khciState->registerBase->USBTRC0 |= USB_USBTRC0_USBRESMEN_MASK;
+ khciState->registerBase->USBCTRL |= USB_USBCTRL_SUSP_MASK;
+ /* Disable the suspend interrupt */
+ khciState->registerBase->INTEN &= ~((uint32_t)kUSB_KhciInterruptSleep);
+
+ /* Clear the suspend interrupt */
+ khciState->registerBase->ISTAT = (kUSB_KhciInterruptSleep);
+ /* Clear the resume interrupt */
+ khciState->registerBase->ISTAT = (kUSB_KhciInterruptResume);
+
+ message.buffer = (uint8_t *)NULL;
+ message.code = kUSB_DeviceNotifySuspend;
+ message.length = 0U;
+ message.isSetup = 0U;
+
+ /* Notify up layer the USB suspend signal detected. */
+ USB_DeviceNotificationTrigger(khciState->deviceHandle, &message);
+}
+
+/*!
+ * @brief Handle the resume interrupt.
+ *
+ * The function is used to handle the resume interrupt when the resume signal detected.
+ *
+ * @param khciState Pointer of the device KHCI state structure.
+ *
+ */
+static void USB_DeviceKhciInterruptResume(usb_device_khci_state_struct_t *khciState)
+{
+ usb_device_callback_message_struct_t message;
+
+ khciState->registerBase->USBCTRL &= ~USB_USBCTRL_SUSP_MASK;
+ /* Enable the suspend interrupt */
+ khciState->registerBase->INTEN |= kUSB_KhciInterruptSleep;
+ /* Disable the resume interrupt */
+ khciState->registerBase->INTEN &= ~((uint32_t)kUSB_KhciInterruptResume);
+ khciState->registerBase->USBTRC0 &= ~USB_USBTRC0_USBRESMEN_MASK;
+
+ /* Clear the resume interrupt */
+ khciState->registerBase->ISTAT = (kUSB_KhciInterruptResume);
+ /* Clear the suspend interrupt */
+ khciState->registerBase->ISTAT = (kUSB_KhciInterruptSleep);
+
+ message.buffer = (uint8_t *)NULL;
+ message.code = kUSB_DeviceNotifyResume;
+ message.length = 0U;
+ message.isSetup = 0U;
+
+ /* Notify up layer the USB resume signal detected. */
+ USB_DeviceNotificationTrigger(khciState->deviceHandle, &message);
+}
+#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */
+
+#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U)) && \
+ (defined(FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED) && (FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED > 0U))
+/*!
+ * @brief Handle the VBUS rising interrupt.
+ *
+ * The function is used to handle the VBUS rising interrupt when the VBUS rising signal detected.
+ *
+ * @param khciState Pointer of the device KHCI state structure.
+ *
+ */
+static void USB_DeviceKhciInterruptVbusRising(usb_device_khci_state_struct_t *khciState)
+{
+ usb_device_callback_message_struct_t message;
+
+ /* Disable the VBUS rising interrupt */
+ khciState->registerBase->MISCCTRL &= ~USB_MISCCTRL_VREDG_EN_MASK;
+ /* Enable the VBUS rising interrupt */
+ khciState->registerBase->MISCCTRL |= USB_MISCCTRL_VREDG_EN_MASK;
+
+ message.buffer = (uint8_t *)NULL;
+ message.code = kUSB_DeviceNotifyAttach;
+ message.length = 0U;
+ message.isSetup = 0U;
+
+ /* Notify up layer the USB VBUS rising signal detected. */
+ USB_DeviceNotificationTrigger(khciState->deviceHandle, &message);
+}
+
+/*!
+ * @brief Handle the VBUS falling interrupt.
+ *
+ * The function is used to handle the VBUS falling interrupt when the VBUS falling signal detected.
+ *
+ * @param khciState Pointer of the device KHCI state structure.
+ *
+ */
+static void USB_DeviceKhciInterruptVbusFalling(usb_device_khci_state_struct_t *khciState)
+{
+ usb_device_callback_message_struct_t message;
+
+ /* Disable the VBUS rising interrupt */
+ khciState->registerBase->MISCCTRL &= ~USB_MISCCTRL_VFEDG_EN_MASK;
+ /* Enable the VBUS rising interrupt */
+ khciState->registerBase->MISCCTRL |= USB_MISCCTRL_VFEDG_EN_MASK;
+
+ message.buffer = (uint8_t *)NULL;
+ message.code = kUSB_DeviceNotifyDetach;
+ message.length = 0U;
+ message.isSetup = 0U;
+
+ /* Notify up layer the USB VBUS falling signal detected. */
+ USB_DeviceNotificationTrigger(khciState->deviceHandle, &message);
+}
+#endif /* USB_DEVICE_CONFIG_DETACH_ENABLE || FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED */
+
+#if 0U
+/*!
+ * @brief Handle the sof interrupt.
+ *
+ * The function is used to handle the sof interrupt.
+ *
+ * @param khciState Pointer of the device KHCI state structure.
+ *
+ */
+void USB_DeviceKhciInterruptSof(usb_device_khci_state_struct_t *khciState)
+{
+ khciState->registerBase->ISTAT = (kUSB_KhciInterruptSofToken);
+
+ khciState->registerBase->ISTAT = (kUSB_KhciInterruptResume);
+}
+#endif
+
+/*!
+ * @brief Handle endpoint stalled interrupt.
+ *
+ * The function is used to handle endpoint stalled interrupt.
+ *
+ * @param khciState Pointer of the device KHCI state structure.
+ *
+ */
+static void USB_DeviceKhciInterruptStall(usb_device_khci_state_struct_t *khciState)
+{
+ /* Clear the endpoint stalled interrupt flag */
+ while (khciState->registerBase->ISTAT & (kUSB_KhciInterruptStall))
+ {
+ khciState->registerBase->ISTAT = (kUSB_KhciInterruptStall);
+ }
+
+ /* Un-stall the control in and out pipe when the control in or out pipe stalled. */
+ if ((khciState->endpointState[(USB_CONTROL_ENDPOINT << 1U) | USB_IN].stateUnion.stateBitField.stalled) ||
+ (khciState->endpointState[(USB_CONTROL_ENDPOINT << 1U) | USB_OUT].stateUnion.stateBitField.stalled))
+ {
+ USB_DeviceKhciEndpointUnstall(
+ khciState, (USB_CONTROL_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)));
+ USB_DeviceKhciEndpointUnstall(
+ khciState, (USB_CONTROL_ENDPOINT | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)));
+ }
+}
+
+#if defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U)
+static void USB_DeviceKhciInterruptError(usb_device_khci_state_struct_t *khciState)
+{
+ usb_device_callback_message_struct_t message;
+
+ khciState->registerBase->ISTAT = (kUSB_KhciInterruptError);
+
+ message.buffer = (uint8_t *)NULL;
+ message.code = kUSB_DeviceNotifyError;
+ message.length = 0U;
+ message.isSetup = 0U;
+
+ /* Notify up layer the USB error detected. */
+ USB_DeviceNotificationTrigger(khciState->deviceHandle, &message);
+}
+#endif /* USB_DEVICE_CONFIG_ERROR_HANDLING */
+
+/*!
+ * @brief Initialize the USB device KHCI instance.
+ *
+ * This function initizlizes the USB device KHCI module specified by the controllerId.
+ *
+ * @param controllerId The controller id of the USB IP. Please refer to enumeration type usb_controller_index_t.
+ * @param handle Pointer of the device handle, used to identify the device object is belonged to.
+ * @param khciHandle It is out parameter, is used to return pointer of the device KHCI handle to the caller.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceKhciInit(uint8_t controllerId,
+ usb_device_handle handle,
+ usb_device_controller_handle *khciHandle)
+{
+ usb_device_khci_state_struct_t *khciState;
+ uint32_t khci_base[] = USB_BASE_ADDRS;
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \
+ (defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U))
+ usb_device_dcd_state_struct_t *dcdState;
+ uint32_t dcd_base[] = USBDCD_BASE_ADDRS;
+#endif
+
+ if (((controllerId - kUSB_ControllerKhci0) >= (uint8_t)USB_DEVICE_CONFIG_KHCI) ||
+ ((controllerId - kUSB_ControllerKhci0) >= (sizeof(khci_base) / sizeof(uint32_t))))
+ {
+ return kStatus_USB_ControllerNotFound;
+ }
+ khciState = &s_UsbDeviceKhciState[controllerId - kUSB_ControllerKhci0];
+
+ khciState->controllerId = controllerId;
+
+ khciState->registerBase = (USB_Type *)khci_base[controllerId - kUSB_ControllerKhci0];
+
+ khciState->dmaAlignBuffer = (uint8_t *)&s_UsbDeviceKhciDmaAlignBuffer[controllerId - kUSB_ControllerKhci0][0];
+
+ /* Clear all interrupt flags. */
+ khciState->registerBase->ISTAT = 0xFFU;
+
+#if (defined(USB_DEVICE_CONFIG_OTG) && (USB_DEVICE_CONFIG_OTG))
+ khciState->otgStatus = 0U;
+#else
+ /* Disable the device functionality. */
+ USB_DeviceKhciControl(khciState, kUSB_DeviceControlStop, NULL);
+#endif
+
+ khciState->bdt = s_UsbDeviceKhciBdtBuffer[controllerId - kUSB_ControllerKhci0];
+
+ /* Set BDT buffer address */
+ khciState->registerBase->BDTPAGE1 = (uint8_t)((((uint32_t)khciState->bdt) >> 8U) & 0xFFU);
+ khciState->registerBase->BDTPAGE2 = (uint8_t)((((uint32_t)khciState->bdt) >> 16U) & 0xFFU);
+ khciState->registerBase->BDTPAGE3 = (uint8_t)((((uint32_t)khciState->bdt) >> 24U) & 0xFFU);
+
+#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U)) && \
+ (defined(FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED) && (FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED > 0U))
+ khciState->registerBase->MISCCTRL |= USB_MISCCTRL_VREDG_EN_MASK | USB_MISCCTRL_VFEDG_EN_MASK;
+#endif
+
+#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \
+ defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \
+ defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U)
+ khciState->registerBase->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
+ khciState->registerBase->KEEP_ALIVE_CTRL =
+ USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK | USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK |
+ USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK | FSL_FEATURE_USB_KHCI_KEEP_ALIVE_MODE_CONTROL;
+ /* wake on out and setup transaction */
+ khciState->registerBase->KEEP_ALIVE_WKCTRL = 0x1U;
+#if defined(FSL_FEATURE_SOC_MCGLITE_COUNT) && (FSL_FEATURE_SOC_MCGLITE_COUNT > 0U)
+ MCG->MC |= MCG_MC_HIRCLPEN_MASK;
+#endif
+
+#endif
+#if defined(FSL_FEATURE_USB_KHCI_HAS_STALL_LOW) && (FSL_FEATURE_USB_KHCI_HAS_STALL_LOW > 0U)
+ khciState->registerBase->MISCCTRL |= USB_MISCCTRL_STL_ADJ_EN_MASK;
+#endif
+
+ /* Set KHCI device state to default value. */
+ USB_DeviceKhciSetDefaultState(khciState);
+
+ *khciHandle = khciState;
+ khciState->deviceHandle = (usb_device_struct_t *)handle;
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \
+ (defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U))
+ dcdState = &s_UsbDeviceDcdState[controllerId - kUSB_ControllerKhci0];
+
+ dcdState->controllerId = controllerId;
+
+ dcdState->dcdRegisterBase = (USBDCD_Type *)dcd_base[controllerId - kUSB_ControllerKhci0];
+
+ dcdState->deviceHandle = (usb_device_struct_t *)handle;
+#endif
+
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief De-initialize the USB device KHCI instance.
+ *
+ * This function de-initizlizes the USB device KHCI module.
+ *
+ * @param khciHandle Pointer of the device KHCI handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceKhciDeinit(usb_device_controller_handle khciHandle)
+{
+ usb_device_khci_state_struct_t *khciState = (usb_device_khci_state_struct_t *)khciHandle;
+
+ if (!khciHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+ /* Clear all interrupt flags. */
+ khciState->registerBase->ISTAT = 0xFFU;
+ /* Disable all interrupts. */
+ khciState->registerBase->INTEN &= ~(0xFFU);
+ /* Clear device address. */
+ khciState->registerBase->ADDR = (0U);
+
+ /* Clear USB_CTL register */
+ khciState->registerBase->CTL = 0x00U;
+ khciState->registerBase->USBCTRL |= USB_USBCTRL_PDE_MASK | USB_USBCTRL_SUSP_MASK;
+
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief Send data through a specified endpoint.
+ *
+ * This function sends data through a specified endpoint.
+ *
+ * @param khciHandle Pointer of the device KHCI handle.
+ * @param endpointAddress Endpoint index.
+ * @param buffer The memory address to hold the data need to be sent.
+ * @param length The data length need to be sent.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ *
+ * @note The return value just means if the sending request is successful or not; the transfer done is notified by the
+ * corresponding callback function.
+ * Currently, only one transfer request can be supported for one specific endpoint.
+ * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application
+ * should implement a queue in the application level.
+ * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint
+ * callback).
+ */
+usb_status_t USB_DeviceKhciSend(usb_device_controller_handle khciHandle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ usb_device_khci_state_struct_t *khciState = (usb_device_khci_state_struct_t *)khciHandle;
+ uint32_t index = ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) << 1U) | USB_IN;
+ usb_status_t error = kStatus_USB_Error;
+
+ /* Save the tansfer information */
+ if (0U == khciState->endpointState[index].stateUnion.stateBitField.transferring)
+ {
+ khciState->endpointState[index].transferDone = 0U;
+ khciState->endpointState[index].transferBuffer = buffer;
+ khciState->endpointState[index].transferLength = length;
+ khciState->endpointState[index].stateUnion.stateBitField.dmaAlign = 1U;
+ }
+
+ /* Data length needs to less than max packet size in each call. */
+ if (length > khciState->endpointState[index].stateUnion.stateBitField.maxPacketSize)
+ {
+ length = khciState->endpointState[index].stateUnion.stateBitField.maxPacketSize;
+ }
+
+ /* Send data when the device is not resetting. */
+ if (0U == khciState->isResetting)
+ {
+ error = USB_DeviceKhciEndpointTransfer(khciState, endpointAddress & USB_ENDPOINT_NUMBER_MASK, USB_IN,
+ (uint8_t *)((uint32_t)khciState->endpointState[index].transferBuffer +
+ (uint32_t)khciState->endpointState[index].transferDone),
+ length);
+ }
+
+ /* Prime a transfer to receive next setup packet if the dat length is zero in a control in endpoint. */
+ if ((0U == khciState->endpointState[index].transferDone) && (0U == length) &&
+ (USB_CONTROL_ENDPOINT == (endpointAddress & USB_ENDPOINT_NUMBER_MASK)))
+ {
+ USB_DeviceKhciPrimeNextSetup(khciState);
+ }
+ return error;
+}
+
+/*!
+ * @brief Receive data through a specified endpoint.
+ *
+ * This function Receives data through a specified endpoint.
+ *
+ * @param khciHandle Pointer of the device KHCI handle.
+ * @param endpointAddress Endpoint index.
+ * @param buffer The memory address to save the received data.
+ * @param length The data length want to be received.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ *
+ * @note The return value just means if the receiving request is successful or not; the transfer done is notified by the
+ * corresponding callback function.
+ * Currently, only one transfer request can be supported for one specific endpoint.
+ * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application
+ * should implement a queue in the application level.
+ * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint
+ * callback).
+ */
+usb_status_t USB_DeviceKhciRecv(usb_device_controller_handle khciHandle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ usb_device_khci_state_struct_t *khciState = (usb_device_khci_state_struct_t *)khciHandle;
+ uint32_t index = ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) << 1U) | USB_OUT;
+ usb_status_t error = kStatus_USB_Error;
+
+ if ((0U == length) && (USB_CONTROL_ENDPOINT == (endpointAddress & USB_ENDPOINT_NUMBER_MASK)))
+ {
+ khciState->endpointState[index].stateUnion.stateBitField.transferring = 0U;
+ USB_DeviceKhciPrimeNextSetup(khciState);
+ }
+ else
+ {
+ /* Save the tansfer information */
+ if (0U == khciState->endpointState[index].stateUnion.stateBitField.transferring)
+ {
+ khciState->endpointState[index].transferDone = 0U;
+ khciState->endpointState[index].transferBuffer = buffer;
+ khciState->endpointState[index].transferLength = length;
+ }
+ khciState->endpointState[index].stateUnion.stateBitField.dmaAlign = 1U;
+
+ /* Data length needs to less than max packet size in each call. */
+ if (length > khciState->endpointState[index].stateUnion.stateBitField.maxPacketSize)
+ {
+ length = khciState->endpointState[index].stateUnion.stateBitField.maxPacketSize;
+ }
+
+ buffer = (uint8_t *)((uint32_t)buffer + (uint32_t)khciState->endpointState[index].transferDone);
+
+ if ((khciState->dmaAlignBuffer) && (0U == khciState->isDmaAlignBufferInusing) &&
+ (USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH >= length) &&
+ ((length & 0x03U) || (((uint32_t)buffer) & 0x03U)))
+ {
+ khciState->endpointState[index].stateUnion.stateBitField.dmaAlign = 0U;
+ buffer = khciState->dmaAlignBuffer;
+ khciState->isDmaAlignBufferInusing = 1U;
+ }
+
+ /* Receive data when the device is not resetting. */
+ if (0U == khciState->isResetting)
+ {
+ error = USB_DeviceKhciEndpointTransfer(khciState, endpointAddress & USB_ENDPOINT_NUMBER_MASK, USB_OUT,
+ buffer, length);
+ }
+ }
+ return error;
+}
+
+/*!
+ * @brief Cancel the pending transfer in a specified endpoint.
+ *
+ * The function is used to cancel the pending transfer in a specified endpoint.
+ *
+ * @param khciHandle Pointer of the device KHCI handle.
+ * @param ep Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceKhciCancel(usb_device_controller_handle khciHandle, uint8_t ep)
+{
+ usb_device_khci_state_struct_t *khciState = (usb_device_khci_state_struct_t *)khciHandle;
+ usb_device_callback_message_struct_t message;
+ uint8_t index = ((ep & USB_ENDPOINT_NUMBER_MASK) << 1U) | ((ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >>
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT);
+
+ /* Cancel the transfer and notify the up layer when the endpoint is busy. */
+ if (khciState->endpointState[index].stateUnion.stateBitField.transferring)
+ {
+ message.length = USB_UNINITIALIZED_VAL_32;
+ message.buffer = khciState->endpointState[index].transferBuffer;
+ message.code = ep;
+ message.isSetup = 0U;
+ khciState->endpointState[index].stateUnion.stateBitField.transferring = 0U;
+ USB_DeviceNotificationTrigger(khciState->deviceHandle, &message);
+ }
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief Control the status of the selected item.
+ *
+ * The function is used to control the status of the selected item.
+ *
+ * @param khciHandle Pointer of the device KHCI handle.
+ * @param type The selected item. Please refer to enumeration type usb_device_control_type_t.
+ * @param param The param type is determined by the selected item.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceKhciControl(usb_device_controller_handle khciHandle, usb_device_control_type_t type, void *param)
+{
+ usb_device_khci_state_struct_t *khciState = (usb_device_khci_state_struct_t *)khciHandle;
+ uint16_t *temp16;
+ uint8_t *temp8;
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \
+ (defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U))
+ usb_device_dcd_state_struct_t *dcdState;
+ dcdState = &s_UsbDeviceDcdState[khciState->controllerId - kUSB_ControllerKhci0];
+ usb_device_dcd_charging_time_t *deviceDcdTimingConfig = (usb_device_dcd_charging_time_t *)param;
+#endif
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+ usb_device_struct_t *deviceHandle;
+ uint64_t startTick;
+#endif
+ usb_status_t error = kStatus_USB_Error;
+
+ if (!khciHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+ deviceHandle = (usb_device_struct_t *)khciState->deviceHandle;
+#endif
+
+ switch (type)
+ {
+ case kUSB_DeviceControlRun:
+ khciState->registerBase->USBCTRL = 0U;
+#if defined(FSL_FEATURE_USB_KHCI_OTG_ENABLED) && (FSL_FEATURE_USB_KHCI_OTG_ENABLED > 0U)
+ if (khciState->registerBase->OTGCTL & USB_OTGCTL_OTGEN_MASK)
+ {
+ khciState->registerBase->OTGCTL |= USB_OTGCTL_DPHIGH_MASK;
+ }
+#endif /* FSL_FEATURE_USB_KHCI_OTG_ENABLED */
+ khciState->registerBase->CONTROL |= USB_CONTROL_DPPULLUPNONOTG_MASK;
+ khciState->registerBase->CTL |= USB_CTL_USBENSOFEN_MASK;
+
+ error = kStatus_USB_Success;
+ break;
+ case kUSB_DeviceControlStop:
+#if defined(FSL_FEATURE_USB_KHCI_OTG_ENABLED) && (FSL_FEATURE_USB_KHCI_OTG_ENABLED > 0U)
+ if (khciState->registerBase->OTGCTL & USB_OTGCTL_OTGEN_MASK)
+ {
+ khciState->registerBase->OTGCTL &= ~USB_OTGCTL_DPHIGH_MASK;
+ }
+#endif /* FSL_FEATURE_USB_KHCI_OTG_ENABLED */
+ khciState->registerBase->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;
+ error = kStatus_USB_Success;
+ break;
+ case kUSB_DeviceControlEndpointInit:
+ if (param)
+ {
+ error = USB_DeviceKhciEndpointInit(khciState, (usb_device_endpoint_init_struct_t *)param);
+ }
+ break;
+ case kUSB_DeviceControlEndpointDeinit:
+ if (param)
+ {
+ temp8 = (uint8_t *)param;
+ error = USB_DeviceKhciEndpointDeinit(khciState, *temp8);
+ }
+ break;
+ case kUSB_DeviceControlEndpointStall:
+ if (param)
+ {
+ temp8 = (uint8_t *)param;
+ error = USB_DeviceKhciEndpointStall(khciState, *temp8);
+ }
+ break;
+ case kUSB_DeviceControlEndpointUnstall:
+ if (param)
+ {
+ temp8 = (uint8_t *)param;
+ error = USB_DeviceKhciEndpointUnstall(khciState, *temp8);
+ }
+ break;
+ case kUSB_DeviceControlGetDeviceStatus:
+ if (param)
+ {
+ temp16 = (uint16_t *)param;
+ *temp16 = (USB_DEVICE_CONFIG_SELF_POWER << (USB_REQUEST_STANDARD_GET_STATUS_DEVICE_SELF_POWERED_SHIFT))
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+ | ((uint16_t)(((uint32_t)deviceHandle->remotewakeup)
+ << (USB_REQUEST_STANDARD_GET_STATUS_DEVICE_REMOTE_WARKUP_SHIFT)))
+#endif
+ ;
+ error = kStatus_USB_Success;
+ }
+ break;
+ case kUSB_DeviceControlGetEndpointStatus:
+ if (param)
+ {
+ usb_device_endpoint_status_struct_t *endpointStatus = (usb_device_endpoint_status_struct_t *)param;
+
+ if (((endpointStatus->endpointAddress) & USB_ENDPOINT_NUMBER_MASK) < USB_DEVICE_CONFIG_ENDPOINTS)
+ {
+ endpointStatus->endpointStatus =
+ (uint16_t)(
+ khciState
+ ->endpointState[(((endpointStatus->endpointAddress) & USB_ENDPOINT_NUMBER_MASK) << 1U) |
+ (((endpointStatus->endpointAddress) &
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >>
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)]
+ .stateUnion.stateBitField.stalled == 1U) ?
+ kUSB_DeviceEndpointStateStalled :
+ kUSB_DeviceEndpointStateIdle;
+ error = kStatus_USB_Success;
+ }
+ }
+ break;
+ case kUSB_DeviceControlSetDeviceAddress:
+ if (param)
+ {
+ temp8 = (uint8_t *)param;
+ khciState->registerBase->ADDR = (*temp8);
+ error = kStatus_USB_Success;
+ }
+ break;
+ case kUSB_DeviceControlGetSynchFrame:
+ break;
+#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+#if defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)
+ case kUSB_DeviceControlResume:
+ khciState->registerBase->CTL |= USB_CTL_RESUME_MASK;
+ startTick = deviceHandle->hwTick;
+ while ((deviceHandle->hwTick - startTick) < 10)
+ {
+ __ASM("nop");
+ }
+ khciState->registerBase->CTL &= ~USB_CTL_RESUME_MASK;
+ error = kStatus_USB_Success;
+ break;
+#endif /* USB_DEVICE_CONFIG_REMOTE_WAKEUP */
+ case kUSB_DeviceControlSuspend:
+ error = kStatus_USB_Success;
+ break;
+#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */
+ case kUSB_DeviceControlSetDefaultStatus:
+ for (uint8_t count = 0U; count < USB_DEVICE_CONFIG_ENDPOINTS; count++)
+ {
+ USB_DeviceKhciEndpointDeinit(khciState, (count | (USB_IN << 0x07U)));
+ USB_DeviceKhciEndpointDeinit(khciState, (count | (USB_OUT << 0x07U)));
+ }
+ USB_DeviceKhciSetDefaultState(khciState);
+ error = kStatus_USB_Success;
+ break;
+ case kUSB_DeviceControlGetSpeed:
+ if (param)
+ {
+ temp8 = (uint8_t *)param;
+ *temp8 = USB_SPEED_FULL;
+ error = kStatus_USB_Success;
+ }
+ break;
+#if (defined(USB_DEVICE_CONFIG_OTG) && (USB_DEVICE_CONFIG_OTG))
+ case kUSB_DeviceControlGetOtgStatus:
+ *((uint8_t *)param) = khciState->otgStatus;
+ break;
+ case kUSB_DeviceControlSetOtgStatus:
+ khciState->otgStatus = *((uint8_t *)param);
+ break;
+#endif
+ case kUSB_DeviceControlSetTestMode:
+ break;
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \
+ (defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U))
+ case kUSB_DeviceControlDcdInitModule:
+ dcdState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK;
+ dcdState->dcdRegisterBase->TIMER0 = USBDCD_TIMER0_TSEQ_INIT(deviceDcdTimingConfig->dcdSeqInitTime);
+ dcdState->dcdRegisterBase->TIMER1 = USBDCD_TIMER1_TDCD_DBNC(deviceDcdTimingConfig->dcdDbncTime);
+ dcdState->dcdRegisterBase->TIMER1 |= USBDCD_TIMER1_TVDPSRC_ON(deviceDcdTimingConfig->dcdDpSrcOnTime);
+ dcdState->dcdRegisterBase->TIMER2_BC12 =
+ USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(deviceDcdTimingConfig->dcdTimeWaitAfterPrD);
+ dcdState->dcdRegisterBase->TIMER2_BC12 |=
+ USBDCD_TIMER2_BC12_TVDMSRC_ON(deviceDcdTimingConfig->dcdTimeDMSrcOn);
+ dcdState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_IE_MASK;
+ dcdState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_BC12_MASK;
+ dcdState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_START_MASK;
+ break;
+ case kUSB_DeviceControlDcdDeinitModule:
+ dcdState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK;
+ break;
+#endif
+
+ default:
+ break;
+ }
+
+ return error;
+}
+
+/*!
+ * @brief Handle the KHCI device interrupt.
+ *
+ * The function is used to handle the KHCI device interrupt.
+ *
+ * @param deviceHandle The device handle got from USB_DeviceInit.
+ *
+ */
+void USB_DeviceKhciIsrFunction(void *deviceHandle)
+{
+ usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle;
+ usb_device_khci_state_struct_t *khciState;
+ uint8_t status;
+
+ if (NULL == deviceHandle)
+ {
+ return;
+ }
+
+ khciState = (usb_device_khci_state_struct_t *)(handle->controllerHandle);
+
+ status = khciState->registerBase->ISTAT;
+#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \
+ defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \
+ defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U)
+ /* Clear EEP_ALIVE_CTRL_WAKE_INT interrupt state */
+ if (khciState->registerBase->KEEP_ALIVE_CTRL & USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK)
+ {
+ khciState->registerBase->KEEP_ALIVE_CTRL |= USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK;
+ }
+ /* Clear SOFTOK interrupt state */
+ if (khciState->registerBase->ISTAT & USB_ISTAT_SOFTOK_MASK)
+ {
+ khciState->registerBase->ISTAT = USB_ISTAT_SOFTOK_MASK;
+ }
+#endif
+#if defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U)
+ /* Error interrupt */
+ if (status & kUSB_KhciInterruptError)
+ {
+ USB_DeviceKhciInterruptError(khciState);
+ }
+#endif /* USB_DEVICE_CONFIG_ERROR_HANDLING */
+ /* Token done interrupt */
+ if (status & kUSB_KhciInterruptTokenDone)
+ {
+ USB_DeviceKhciInterruptTokenDone(khciState);
+ }
+
+ /* Reset interrupt */
+ if (status & kUSB_KhciInterruptReset)
+ {
+ USB_DeviceKhciInterruptReset(khciState);
+ }
+
+#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+ /* Suspend interrupt */
+ if (status & kUSB_KhciInterruptSleep)
+ {
+ USB_DeviceKhciInterruptSleep(khciState);
+ }
+
+ /* Resume interrupt */
+ if (status & kUSB_KhciInterruptResume)
+ {
+ USB_DeviceKhciInterruptResume(khciState);
+ }
+
+ if (khciState->registerBase->USBTRC0 & USB_USBTRC0_USB_RESUME_INT_MASK)
+ {
+ USB_DeviceKhciInterruptResume(khciState);
+ }
+#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */
+
+ /* Endpoint stalled interrupt */
+ if (status & kUSB_KhciInterruptStall)
+ {
+ USB_DeviceKhciInterruptStall(khciState);
+ }
+
+#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U)) && \
+ (defined(FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED) && (FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED > 0U))
+ if (khciState->registerBase->USBTRC0 & USB_USBTRC0_VREDG_DET_MASK)
+ {
+ USB_DeviceKhciInterruptVbusRising(khciState);
+ }
+
+ if (khciState->registerBase->USBTRC0 & USB_USBTRC0_VFEDG_DET_MASK)
+ {
+ USB_DeviceKhciInterruptVbusFalling(khciState);
+ }
+#endif /* USB_DEVICE_CONFIG_DETACH_ENABLE && FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED */
+
+#if 0U
+ /* Sof token interrupt */
+ if (status & kUSB_KhciInterruptSofToken)
+ {
+ USB_DeviceKhciInterruptSof(khciState);
+ }
+#endif
+
+#if ((defined FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && \
+ (FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED > 0U))
+ status = khciState->registerBase->CLK_RECOVER_INT_STATUS;
+ if (status)
+ {
+ /* USB RECOVER interrupt is happenned */
+ if (USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK & status)
+ {
+ /* Indicates that the USB clock recovery algorithm has detected that the frequency trim adjustment needed
+ * for the IRC48M output clock is outside the available TRIM_FINE adjustment range for the IRC48M
+ * module.
+ */
+ }
+ khciState->registerBase->CLK_RECOVER_INT_STATUS = status;
+ }
+#endif
+}
+
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \
+ (defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U))
+/*!
+ * @brief Handle the device DCD module interrupt.
+ *
+ * The function is used to handle the device DCD module interrupt.
+ *
+ * @param deviceHandle The device handle got from USB_DeviceInit.
+ *
+ */
+void USB_DeviceDcdIsrFunction(void *deviceHandle)
+{
+ usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle;
+ usb_device_khci_state_struct_t *khciState;
+ usb_device_dcd_state_struct_t *dcdState;
+ uint32_t status;
+ uint32_t chargerType;
+ usb_device_callback_message_struct_t message;
+
+ if (NULL == deviceHandle)
+ {
+ return;
+ }
+
+ khciState = (usb_device_khci_state_struct_t *)(handle->controllerHandle);
+
+ dcdState = &s_UsbDeviceDcdState[khciState->controllerId - kUSB_ControllerKhci0];
+
+ /* Read the STATUS register in the interrupt routine. */
+ status = dcdState->dcdRegisterBase->STATUS;
+
+ /* Clear the interrupt flag bit. */
+ dcdState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_IACK_MASK;
+
+ message.buffer = (uint8_t *)NULL;
+ message.length = 0U;
+ message.isSetup = 0U;
+
+ if (status & USBDCD_STATUS_ERR_MASK)
+ {
+ if (status & USBDCD_STATUS_TO_MASK)
+ {
+ dcdState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK;
+ message.code = kUSB_DeviceNotifyDcdTimeOut;
+ USB_DeviceNotificationTrigger(dcdState->deviceHandle, &message);
+ }
+ else
+ {
+ dcdState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK;
+ message.code = kUSB_DeviceNotifyDcdUnknownPortType;
+ USB_DeviceNotificationTrigger(dcdState->deviceHandle, &message);
+ }
+ }
+ else
+ {
+ switch (status & USBDCD_STATUS_SEQ_STAT_MASK)
+ {
+ case USBDCD_STATUS_SEQ_STAT(kUSB_DcdChargingPortDetectionCompleted):
+ chargerType = status & USBDCD_STATUS_SEQ_RES_MASK;
+ if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionStandardHost))
+ {
+ dcdState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK;
+ message.code = kUSB_DeviceNotifySDPDetected;
+ USB_DeviceNotificationTrigger(dcdState->deviceHandle, &message);
+ }
+ else if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionChargingPort))
+ {
+ message.code = kUSB_DeviceNotifyChargingPortDetected;
+ USB_DeviceNotificationTrigger(dcdState->deviceHandle, &message);
+ }
+ break;
+ case USBDCD_STATUS_SEQ_STAT(kUSB_DcdChargerTypeDetectionCompleted):
+ chargerType = status & USBDCD_STATUS_SEQ_RES_MASK;
+ if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionChargingPort))
+ {
+ dcdState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK;
+ message.code = kUSB_DeviceNotifyChargingHostDetected;
+ USB_DeviceNotificationTrigger(dcdState->deviceHandle, &message);
+ }
+ else if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionDedicatedCharger))
+ {
+ dcdState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK;
+ message.code = kUSB_DeviceNotifyDedicatedChargerDetected;
+ USB_DeviceNotificationTrigger(dcdState->deviceHandle, &message);
+ }
+ break;
+
+ default:
+ break;
+ }
+ }
+}
+#endif
+#endif /* USB_DEVICE_CONFIG_KHCI */
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __USB_DEVICE_KHCI_H__
+#define __USB_DEVICE_KHCI_H__
+
+/*!
+ * @addtogroup usb_device_controller_khci_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief The maximum value of ISO maximum packet size for FS in USB specification 2.0 */
+#define USB_DEVICE_MAX_FS_ISO_MAX_PACKET_SIZE (1023U)
+
+/*! @brief The maximum value of non-ISO maximum packet size for FS in USB specification 2.0 */
+#define USB_DEVICE_MAX_FS_NONE_ISO_MAX_PACKET_SIZE (64U)
+
+/*! @brief Set BDT buffer address */
+#define USB_KHCI_BDT_SET_ADDRESS(bdt_base, ep, direction, odd, address) \
+ *((volatile uint32_t *)((bdt_base & 0xfffffe00U) | (((uint32_t)ep & 0x0fU) << 5U) | \
+ (((uint32_t)direction & 1U) << 4U) | (((uint32_t)odd & 1U) << 3U)) + \
+ 1U) = address
+
+/*! @brief Set BDT control fields*/
+#define USB_KHCI_BDT_SET_CONTROL(bdt_base, ep, direction, odd, control) \
+ *(volatile uint32_t *)((bdt_base & 0xfffffe00U) | (((uint32_t)ep & 0x0fU) << 5U) | \
+ (((uint32_t)direction & 1U) << 4U) | (((uint32_t)odd & 1U) << 3U)) = control
+
+/*! @brief Get BDT buffer address*/
+#define USB_KHCI_BDT_GET_ADDRESS(bdt_base, ep, direction, odd) \
+ (*((volatile uint32_t *)((bdt_base & 0xfffffe00U) | (((uint32_t)ep & 0x0fU) << 5U) | \
+ (((uint32_t)direction & 1U) << 4U) | (((uint32_t)odd & 1U) << 3U)) + \
+ 1U))
+
+/*! @brief Get BDT control fields*/
+#define USB_KHCI_BDT_GET_CONTROL(bdt_base, ep, direction, odd) \
+ (*(volatile uint32_t *)((bdt_base & 0xfffffe00U) | (((uint32_t)ep & 0x0fU) << 5U) | \
+ (((uint32_t)direction & 1U) << 4U) | (((uint32_t)odd & 1U) << 3U)))
+
+/*! @brief Endpoint state structure */
+typedef struct _usb_device_khci_endpoint_state_struct
+{
+ uint8_t *transferBuffer; /*!< Address of buffer containing the data to be transmitted */
+ uint32_t transferLength; /*!< Length of data to transmit. */
+ uint32_t transferDone; /*!< The data length has been transferred*/
+ union
+ {
+ uint32_t state; /*!< The state of the endpoint */
+ struct
+ {
+ uint32_t maxPacketSize : 10U; /*!< The maximum packet size of the endpoint */
+ uint32_t stalled : 1U; /*!< The endpoint is stalled or not */
+ uint32_t data0 : 1U; /*!< The data toggle of the transaction */
+ uint32_t bdtOdd : 1U; /*!< The BDT toggle of the endpoint */
+ uint32_t dmaAlign : 1U; /*!< Whether the transferBuffer is DMA aligned or not */
+ uint32_t transferring : 1U; /*!< The endpoint is transferring */
+ uint32_t zlt : 1U; /*!< zlt flag */
+ } stateBitField;
+ } stateUnion;
+} usb_device_khci_endpoint_state_struct_t;
+
+/*! @brief KHCI state structure */
+typedef struct _usb_device_khci_state_struct
+{
+ usb_device_struct_t *deviceHandle; /*!< Device handle used to identify the device object belongs to */
+ uint8_t *bdt; /*!< BDT buffer address */
+ USB_Type *registerBase; /*!< The base address of the register */
+ uint8_t setupPacketBuffer[USB_SETUP_PACKET_SIZE * 2]; /*!< The setup request buffer */
+ uint8_t *dmaAlignBuffer; /*!< This buffer is used to fix the transferBuffer or transferLength does
+ not align to 4-bytes when the function USB_DeviceKhciRecv is called.
+ The macro USB_DEVICE_CONFIG_KHCI_DMA_ALIGN is used to enable or disable this feature.
+ If the feature is enabled, when the transferBuffer or transferLength does not align to
+ 4-bytes,
+ the transferLength is not more than USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH, and
+ the flag isDmaAlignBufferInusing is zero, the dmaAlignBuffer is used to receive data
+ and the flag isDmaAlignBufferInusing is set to 1.
+ When the transfer is done, the received data, kept in dmaAlignBuffer, is copied
+ to the transferBuffer, and the flag isDmaAlignBufferInusing is cleared.
+ */
+ usb_device_khci_endpoint_state_struct_t
+ endpointState[USB_DEVICE_CONFIG_ENDPOINTS * 2]; /*!< Endpoint state structures */
+ uint8_t isDmaAlignBufferInusing; /*!< The dmaAlignBuffer is used or not */
+ uint8_t isResetting; /*!< Is doing device reset or not */
+ uint8_t controllerId; /*!< Controller ID */
+ uint8_t setupBufferIndex; /*!< A valid setup buffer flag */
+#if (defined(USB_DEVICE_CONFIG_OTG) && (USB_DEVICE_CONFIG_OTG))
+ uint8_t otgStatus;
+#endif
+} usb_device_khci_state_struct_t;
+
+#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \
+ (defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U))
+typedef struct _usb_device_dcd_state_struct
+{
+ usb_device_struct_t *deviceHandle; /*!< Device handle used to identify the device object belongs to */
+ USBDCD_Type *dcdRegisterBase; /*!< The base address of the dcd module */
+ uint8_t controllerId; /*!< Controller ID */
+} usb_device_dcd_state_struct_t;
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name USB device KHCI functions
+ * @{
+ */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Initializes the USB device KHCI instance.
+ *
+ * This function initializes the USB device KHCI module specified by the controllerId.
+ *
+ * @param[in] controllerId The controller ID of the USB IP. See the enumeration type usb_controller_index_t.
+ * @param[in] handle Pointer of the device handle used to identify the device object belongs to.
+ * @param[out] khciHandle An out parameter used to return the pointer of the device KHCI handle to the caller.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceKhciInit(uint8_t controllerId,
+ usb_device_handle handle,
+ usb_device_controller_handle *khciHandle);
+
+/*!
+ * @brief Deinitializes the USB device KHCI instance.
+ *
+ * This function deinitializes the USB device KHCI module.
+ *
+ * @param[in] khciHandle Pointer of the device KHCI handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceKhciDeinit(usb_device_controller_handle khciHandle);
+
+/*!
+ * @brief Sends data through a specified endpoint.
+ *
+ * This function sends data through a specified endpoint.
+ *
+ * @param[in] khciHandle Pointer of the device KHCI handle.
+ * @param[in] endpointAddress Endpoint index.
+ * @param[in] buffer The memory address to hold the data need to be sent.
+ * @param[in] length The data length need to be sent.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ *
+ * @note The return value indicates whether the sending request is successful or not. The transfer completion is
+ * notified by the
+ * corresponding callback function.
+ * Currently, only one transfer request can be supported for a specific endpoint.
+ * If there is a specific requirement to support multiple transfer requests for a specific endpoint, the application
+ * should implement a queue in the application level.
+ * The subsequent transfer can begin only when the previous transfer is done (a notification is obtained through the
+ * endpoint
+ * callback).
+ */
+usb_status_t USB_DeviceKhciSend(usb_device_controller_handle khciHandle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*!
+ * @brief Receives data through a specified endpoint.
+ *
+ * This function receives data through a specified endpoint.
+ *
+ * @param[in] khciHandle Pointer of the device KHCI handle.
+ * @param[in] endpointAddress Endpoint index.
+ * @param[in] buffer The memory address to save the received data.
+ * @param[in] length The data length to be received.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ *
+ * @note The return value indicates whether the receiving request is successful or not. The transfer completion is
+ * notified by the
+ * corresponding callback function.
+ * Currently, only one transfer request can be supported for a specific endpoint.
+ * If there is a specific requirement to support multiple transfer requests for a specific endpoint, the application
+ * should implement a queue in the application level.
+ * The subsequent transfer can begin only when the previous transfer is done (a notification is obtained through the
+ * endpoint
+ * callback).
+ */
+usb_status_t USB_DeviceKhciRecv(usb_device_controller_handle khciHandle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*!
+ * @brief Cancels the pending transfer in a specified endpoint.
+ *
+ * The function is used to cancel the pending transfer in a specified endpoint.
+ *
+ * @param[in] khciHandle Pointer of the device KHCI handle.
+ * @param[in] ep Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceKhciCancel(usb_device_controller_handle khciHandle, uint8_t ep);
+
+/*!
+ * @brief Controls the status of the selected item.
+ *
+ * The function is used to control the status of the selected item.
+ *
+ * @param[in] khciHandle Pointer of the device KHCI handle.
+ * @param[in] type The selected item. See enumeration type usb_device_control_type_t.
+ * @param[in,out] param The parameter type is determined by the selected item.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceKhciControl(usb_device_controller_handle khciHandle,
+ usb_device_control_type_t type,
+ void *param);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* __USB_DEVICE_KHCI_H__ */
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __USB_KHCI_H__
+#define __USB_KHCI_H__
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define USB_KHCI_BDT_DEVICE_OUT_TOKEN (0x01U)
+#define USB_KHCI_BDT_DEVICE_IN_TOKEN (0x09U)
+#define USB_KHCI_BDT_DEVICE_SETUP_TOKEN (0x0DU)
+
+#define USB_KHCI_BDT_OWN (0x80U)
+#define USB_KHCI_BDT_DATA01(x) ((((uint32_t)(x)) & 0x01U) << 0x06U)
+#define USB_KHCI_BDT_BC(x) ((((uint32_t)(x)) & 0x3FFU) << 0x10U)
+#define UBS_KHCI_BDT_KEEP (0x20U)
+#define UBS_KHCI_BDT_NINC (0x10U)
+#define USB_KHCI_BDT_DTS (0x08U)
+#define USB_KHCI_BDT_STALL (0x04U)
+
+typedef enum _usb_khci_interrupt_type
+{
+ kUSB_KhciInterruptReset = 0x01U,
+ kUSB_KhciInterruptError = 0x02U,
+ kUSB_KhciInterruptSofToken = 0x04U,
+ kUSB_KhciInterruptTokenDone = 0x08U,
+ kUSB_KhciInterruptSleep = 0x10U,
+ kUSB_KhciInterruptResume = 0x20U,
+ kUSB_KhciInterruptAttach = 0x40U,
+ kUSB_KhciInterruptStall = 0x80U,
+} usb_khci_interrupt_type_t;
+
+#endif /* __USB_KHCI_H__ */
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __USB_MISC_H__
+#define __USB_MISC_H__
+
+#ifndef ENDIANNESS
+
+#error ENDIANNESS should be defined, and then rebulid the project.
+
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Define USB printf */
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+extern int DbgConsole_Printf(const char *fmt_s, ...);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#if defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE < 1)
+#define usb_echo printf
+#else
+#define usb_echo DbgConsole_Printf
+#endif
+
+#if defined(__ICCARM__)
+
+#ifndef STRUCT_PACKED
+#define STRUCT_PACKED __packed
+#endif
+
+#ifndef STRUCT_UNPACKED
+#define STRUCT_UNPACKED
+#endif
+
+#elif defined(__GNUC__)
+
+#ifndef STRUCT_PACKED
+#define STRUCT_PACKED
+#endif
+
+#ifndef STRUCT_UNPACKED
+#define STRUCT_UNPACKED __attribute__((__packed__))
+#endif
+
+#elif defined(__CC_ARM)
+
+#ifndef STRUCT_PACKED
+#define STRUCT_PACKED _Pragma("pack(1U)")
+#endif
+
+#ifndef STRUCT_UNPACKED
+#define STRUCT_UNPACKED _Pragma("pack()")
+#endif
+
+#endif
+
+#define USB_SHORT_GET_LOW(x) (((uint16_t)x) & 0xFFU)
+#define USB_SHORT_GET_HIGH(x) ((uint8_t)(((uint16_t)x) >> 8U) & 0xFFU)
+
+#define USB_LONG_GET_BYTE0(x) ((uint8_t)(((uint32_t)(x))) & 0xFFU)
+#define USB_LONG_GET_BYTE1(x) ((uint8_t)(((uint32_t)(x)) >> 8U) & 0xFFU)
+#define USB_LONG_GET_BYTE2(x) ((uint8_t)(((uint32_t)(x)) >> 16U) & 0xFFU)
+#define USB_LONG_GET_BYTE3(x) ((uint8_t)(((uint32_t)(x)) >> 24U) & 0xFFU)
+
+#define USB_MEM4_ALIGN_MASK (0x03U)
+
+/* accessory macro */
+#define USB_MEM4_ALIGN(n) ((n + 3U) & (0xFFFFFFFCu))
+#define USB_MEM32_ALIGN(n) ((n + 31U) & (0xFFFFFFE0u))
+#define USB_MEM64_ALIGN(n) ((n + 63U) & (0xFFFFFFC0u))
+
+/* big/little endian */
+#define SWAP2BYTE_CONST(n) ((((n)&0x00FFU) << 8U) | (((n)&0xFF00U) >> 8U))
+#define SWAP4BYTE_CONST(n) \
+ ((((n)&0x000000FFU) << 24U) | (((n)&0x0000FF00U) << 8U) | (((n)&0x00FF0000U) >> 8U) | (((n)&0xFF000000U) >> 24U))
+
+#define USB_ASSIGN_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \
+ { \
+ *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \
+ *((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \
+ *((uint8_t *)&(n) + 2) = *((uint8_t *)&(m) + 2); \
+ *((uint8_t *)&(n) + 3) = *((uint8_t *)&(m) + 3); \
+ }
+
+#define USB_ASSIGN_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \
+ { \
+ *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \
+ *((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \
+ }
+
+#define USB_ASSIGN_MACRO_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \
+ { \
+ *((uint8_t *)&(n)) = (uint8_t)m; \
+ *((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \
+ *((uint8_t *)&(n) + 2) = (uint8_t)(m >> 16); \
+ *((uint8_t *)&(n) + 3) = (uint8_t)(m >> 24); \
+ }
+
+#define USB_ASSIGN_MACRO_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \
+ { \
+ *((uint8_t *)&(n)) = (uint8_t)m; \
+ *((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \
+ }
+
+#if (ENDIANNESS == USB_BIG_ENDIAN)
+
+#define USB_SHORT_TO_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n)
+#define USB_LONG_TO_LITTLE_ENDIAN(n) SWAP4BYTE_CONST(n)
+#define USB_SHORT_FROM_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n)
+#define USB_LONG_FROM_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n)
+
+#define USB_SHORT_TO_BIG_ENDIAN(n) (n)
+#define USB_LONG_TO_BIG_ENDIAN(n) (n)
+#define USB_SHORT_FROM_BIG_ENDIAN(n) (n)
+#define USB_LONG_FROM_BIG_ENDIAN(n) (n)
+
+#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[3] = ((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ m[2] = ((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ m[1] = ((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ m[0] = (((uint32_t)(n)) & 0xFFU); \
+ }
+
+#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \
+ ((uint32_t)((((uint8_t)n[3]) << 24U) | (((uint8_t)n[2]) << 16U) | (((uint8_t)n[1]) << 8U) | \
+ (((uint8_t)n[0]) << 0U)))
+
+#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[0] = ((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ m[1] = ((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ m[2] = ((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ m[3] = (((uint32_t)(n)) & 0xFFU); \
+ }
+
+#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \
+ ((uint32_t)((((uint8_t)n[0]) << 24U) | (((uint8_t)n[1]) << 16U) | (((uint8_t)n[2]) << 8U) | \
+ (((uint8_t)n[3]) << 0U)))
+
+#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[1] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ m[0] = (((uint16_t)(n)) & 0xFFU); \
+ }
+
+#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[1]) << 8U) | (((uint8_t)n[0]) << 0U)))
+
+#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[0] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ m[1] = (((uint16_t)(n)) & 0xFFU); \
+ }
+
+#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[0]) << 8U) | (((uint8_t)n[1]) << 0U)))
+
+#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \
+ { \
+ *((uint8_t *)&(m) + 3) = ((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ *((uint8_t *)&(m) + 2) = ((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ *((uint8_t *)&(m) + 1) = ((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ *((uint8_t *)&(m) + 0) = (((uint32_t)(n)) & 0xFFU); \
+ }
+
+#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \
+ ((uint32_t)(((*((uint8_t *)&(n) + 3)) << 24U) | ((*((uint8_t *)&(n) + 2)) << 16U) | \
+ ((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n))) << 0U)))
+
+#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \
+ { \
+ *((uint8_t *)&(m) + 1) = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ *((uint8_t *)&(m)) = ((((uint16_t)(n))) & 0xFFU); \
+ }
+
+#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) ((uint32_t)(((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n))))))
+
+#else
+
+#define USB_SHORT_TO_LITTLE_ENDIAN(n) (n)
+#define USB_LONG_TO_LITTLE_ENDIAN(n) (n)
+#define USB_SHORT_FROM_LITTLE_ENDIAN(n) (n)
+#define USB_LONG_FROM_LITTLE_ENDIAN(n) (n)
+
+#define USB_SHORT_TO_BIG_ENDIAN(n) SWAP2BYTE_CONST(n)
+#define USB_LONG_TO_BIG_ENDIAN(n) SWAP4BYTE_CONST(n)
+#define USB_SHORT_FROM_BIG_ENDIAN(n) SWAP2BYTE_CONST(n)
+#define USB_LONG_FROM_BIG_ENDIAN(n) SWAP4BYTE_CONST(n)
+
+#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[3] = ((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ m[2] = ((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ m[1] = ((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ m[0] = (((uint32_t)(n)) & 0xFFU); \
+ }
+
+#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \
+ ((uint32_t)((((uint8_t)n[3]) << 24U) | (((uint8_t)n[2]) << 16U) | (((uint8_t)n[1]) << 8U) | \
+ (((uint8_t)n[0]) << 0U)))
+
+#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[0] = ((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ m[1] = ((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ m[2] = ((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ m[3] = (((uint32_t)(n)) & 0xFFU); \
+ }
+
+#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \
+ ((uint32_t)((((uint8_t)n[0]) << 24U) | (((uint8_t)n[1]) << 16U) | (((uint8_t)n[2]) << 8U) | \
+ (((uint8_t)n[3]) << 0U)))
+
+#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[1] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ m[0] = (((uint16_t)(n)) & 0xFFU); \
+ }
+
+#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[1]) << 8U) | (((uint8_t)n[0]) << 0U)))
+
+#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[0] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ m[1] = (((uint16_t)(n)) & 0xFFU); \
+ }
+
+#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[0]) << 8U) | (((uint8_t)n[1]) << 0U)))
+
+#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \
+ { \
+ *((uint8_t *)&(m) + 3) = ((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ *((uint8_t *)&(m) + 2) = ((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ *((uint8_t *)&(m) + 1) = ((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ *((uint8_t *)&(m) + 0) = (((uint32_t)(n)) & 0xFFU); \
+ }
+
+#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \
+ ((uint32_t)(((*((uint8_t *)&(n) + 3)) << 24U) | ((*((uint8_t *)&(n) + 2)) << 16U) | \
+ ((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n))) << 0U)))
+
+#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \
+ { \
+ *((uint8_t *)&(m) + 1) = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ *((uint8_t *)&(m)) = ((((uint16_t)(n))) & 0xFFU); \
+ }
+
+#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) ((uint32_t)(((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n))))))
+
+#endif
+
+/*
+ * The following MACROs (USB_GLOBAL, USB_BDT, USB_RAM_ADDRESS_ALIGNMENT, etc) are only used for USB device stack.
+ * The USB device global variables are put into the section m_usb_global and m_usb_bdt or the section
+ * .bss.m_usb_global and .bss.m_usb_bdt by using the MACRO USB_GLOBAL and USB_BDT. In this way, the USB device
+ * global variables can be linked into USB dedicated RAM by USB_STACK_USE_DEDICATED_RAM.
+ * The MACRO USB_STACK_USE_DEDICATED_RAM is used to decide the USB stack uses dedicated RAM or not. The value of
+ * the marco can be set as 0, USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL, or USB_STACK_DEDICATED_RAM_TYPE_BDT.
+ * The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL means USB device global variables, including USB_BDT and
+ * USB_GLOBAL, are put into the USB dedicated RAM. This feature can only be enabled when the USB dedicated RAM
+ * is not less than 2K Bytes.
+ * The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT means USB device global variables, only including USB_BDT, are put
+ * into the USB dedicated RAM, the USB_GLOBAL will be put into .bss section. This feature is used for some SOCs,
+ * the USB dedicated RAM size is not more than 512 Bytes.
+ */
+#define USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL 1
+#define USB_STACK_DEDICATED_RAM_TYPE_BDT 2
+
+#if defined(__ICCARM__)
+
+#define USB_WEAK_VAR __attribute__((weak))
+#define USB_WEAK_FUN __attribute__((weak))
+/* disable misra 19.13 */
+_Pragma("diag_suppress=Pm120")
+#define USB_ALIGN_PRAGMA(x) _Pragma(#x)
+ _Pragma("diag_default=Pm120")
+
+#define USB_RAM_ADDRESS_ALIGNMENT(n) USB_ALIGN_PRAGMA(data_alignment = n)
+ _Pragma("diag_suppress=Pm120")
+#define USB_LINK_SECTION_PART(str) _Pragma(#str)
+#define USB_LINK_DMA_INIT_DATA(sec) USB_LINK_SECTION_PART(location = #sec)
+#define USB_LINK_USB_GLOBAL _Pragma("location = \"m_usb_global\"")
+#define USB_LINK_USB_BDT _Pragma("location = \"m_usb_bdt\"")
+#define USB_LINK_USB_GLOBAL_BSS _Pragma("location = \".bss.m_usb_global\"")
+#define USB_LINK_USB_BDT_BSS _Pragma("location = \".bss.m_usb_bdt\"")
+ _Pragma("diag_default=Pm120")
+#define USB_LINK_DMA_NONINIT_DATA _Pragma("location = \"m_usb_dma_noninit_data\"")
+#define USB_LINK_NONCACHE_NONINIT_DATA _Pragma("location = \"NonCacheable\"")
+#elif defined(__CC_ARM)
+
+#define USB_WEAK_VAR __attribute__((weak))
+#define USB_WEAK_FUN __weak
+#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n)))
+#define USB_LINK_DMA_INIT_DATA(sec) __attribute__((section(#sec)))
+#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global"))) __attribute__((zero_init))
+#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt"))) __attribute__((zero_init))
+#define USB_LINK_USB_GLOBAL_BSS __attribute__((section(".bss.m_usb_global"))) __attribute__((zero_init))
+#define USB_LINK_USB_BDT_BSS __attribute__((section(".bss.m_usb_bdt"))) __attribute__((zero_init))
+#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data"))) __attribute__((zero_init))
+#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable"))) __attribute__((zero_init))
+
+#elif defined(__GNUC__)
+
+#define USB_WEAK_VAR __attribute__((weak))
+#define USB_WEAK_FUN __attribute__((weak))
+#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n)))
+#define USB_LINK_DMA_INIT_DATA(sec) __attribute__((section(#sec)))
+#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global, \"aw\", %nobits @")))
+#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt, \"aw\", %nobits @")))
+#define USB_LINK_USB_GLOBAL_BSS __attribute__((section(".bss.m_usb_global, \"aw\", %nobits @")))
+#define USB_LINK_USB_BDT_BSS __attribute__((section(".bss.m_usb_bdt, \"aw\", %nobits @")))
+#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data, \"aw\", %nobits @")))
+#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable, \"aw\", %nobits @")))
+
+#else
+#error The tool-chain is not supported.
+#endif
+
+#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \
+ (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE))
+
+#if ((defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)) && (defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
+#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#elif(defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))
+#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, 0)
+#elif(defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))
+#define USB_CACHE_LINESIZE MAX(0, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#else
+#define USB_CACHE_LINESIZE 4
+#endif
+
+#else
+#define USB_CACHE_LINESIZE 4
+#endif
+
+#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \
+ ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)))
+#define USB_DATA_ALIGN 64
+#else
+#define USB_DATA_ALIGN 4
+#endif
+
+#define USB_DATA_ALIGN_SIZE MAX(USB_CACHE_LINESIZE, USB_DATA_ALIGN)
+
+#define USB_DATA_ALIGN_SIZE_MULTIPLE(n) ((n + USB_DATA_ALIGN_SIZE - 1) & (~(USB_DATA_ALIGN_SIZE - 1)))
+
+#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL)
+
+#define USB_GLOBAL USB_LINK_USB_GLOBAL
+#define USB_BDT USB_LINK_USB_BDT
+
+#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \
+ (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE))
+#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA
+#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(m_usb_dma_init_data)
+#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA
+#else
+#define USB_DMA_DATA_NONINIT_SUB
+#define USB_DMA_DATA_INIT_SUB
+#define USB_CONTROLLER_DATA USB_LINK_USB_GLOBAL
+#endif
+
+#elif defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT)
+
+#define USB_BDT USB_LINK_USB_BDT
+
+#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \
+ (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE))
+#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA
+#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA
+#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(m_usb_dma_init_data)
+#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA
+#else
+#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS
+#define USB_DMA_DATA_NONINIT_SUB
+#define USB_DMA_DATA_INIT_SUB
+#define USB_CONTROLLER_DATA
+#endif
+
+#else
+
+#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \
+ (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE))
+
+#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA
+#define USB_BDT USB_LINK_NONCACHE_NONINIT_DATA
+#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA
+#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(m_usb_dma_init_data)
+#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA
+
+#else
+#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS
+#define USB_BDT USB_LINK_USB_BDT_BSS
+#define USB_DMA_DATA_NONINIT_SUB
+#define USB_DMA_DATA_INIT_SUB
+#define USB_CONTROLLER_DATA
+#endif
+
+#endif
+
+#define USB_DMA_NONINIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_NONINIT_SUB
+#define USB_DMA_INIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_INIT_SUB
+
+#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \
+ (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE))
+#define USB_DMA_DATA_NONCACHEABLE USB_LINK_NONCACHE_NONINIT_DATA
+
+#else
+#define USB_DMA_DATA_NONCACHEABLE
+#endif
+
+#define USB_GLOBAL_DEDICATED_RAM USB_LINK_USB_GLOBAL
+
+/* #define USB_RAM_ADDRESS_NONCACHEREG_ALIGNMENT(n, var) AT_NONCACHEABLE_SECTION_ALIGN(var, n) */
+/* #define USB_RAM_ADDRESS_NONCACHEREG(var) AT_NONCACHEABLE_SECTION(var) */
+
+#endif /* __USB_MISC_H__ */
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __USB_OSA_H__
+#define __USB_OSA_H__
+
+/*!
+ * @addtogroup usb_os_abstraction
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Define big endian */
+#define USB_BIG_ENDIAN (0U)
+/*! @brief Define little endian */
+#define USB_LITTLE_ENDIAN (1U)
+
+/*! @brief Define current endian */
+#define ENDIANNESS USB_LITTLE_ENDIAN
+
+/*! @brief Define USB OSA event handle */
+typedef void *usb_osa_event_handle;
+
+/*! @brief Define USB OSA semaphore handle */
+typedef void *usb_osa_sem_handle;
+
+/*! @brief Define USB OSA mutex handle */
+typedef void *usb_osa_mutex_handle;
+
+/*! @brief Define USB OSA message queue handle */
+typedef void *usb_osa_msgq_handle;
+
+/*! @brief USB OSA error code */
+typedef enum _usb_osa_status
+{
+ kStatus_USB_OSA_Success = 0x00U, /*!< Success */
+ kStatus_USB_OSA_Error, /*!< Failed */
+ kStatus_USB_OSA_TimeOut, /*!< Timeout occurs while waiting */
+} usb_osa_status_t;
+
+/*! @brief The event flags are cleared automatically or manually.*/
+typedef enum _usb_osa_event_mode
+{
+ kUSB_OsaEventManualClear = 0U, /*!< The flags of the event is cleared manually. */
+ kUSB_OsaEventAutoClear = 1U, /*!< The flags of the event is cleared automatically. */
+} usb_osa_event_mode_t;
+
+/* Include required header file based on RTOS selection */
+#if defined(USB_STACK_BM)
+
+#include "usb_osa_bm.h"
+
+#elif defined(USB_STACK_FREERTOS)
+
+#include "usb_osa_freertos.h"
+
+#elif defined(USB_STACK_UCOSII)
+
+#include "usb_osa_ucosii.h"
+
+#elif defined(USB_STACK_UCOSIII)
+
+#include "usb_osa_ucosiii.h"
+
+#else
+#if defined(SDK_OS_BAREMETAL)
+
+#define USB_STACK_BM
+#include "usb_osa_bm.h"
+
+#elif defined(SDK_OS_FREE_RTOS)
+
+#define USB_STACK_FREERTOS
+#include "usb_osa_freertos.h"
+
+#elif defined(SDK_OS_UCOSII)
+
+#define USB_STACK_UCOSII
+#include "usb_osa_ucosii.h"
+
+#elif defined(SDK_OS_UCOSIII)
+
+#define USB_STACK_UCOSIII
+#include "usb_osa_ucosiii.h"
+
+#else
+
+#error Not define RTOS in file "usb_osa.h".
+#endif
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name USB OSA Memory Management
+ * @{
+ */
+
+/*!
+ * @brief Reserves the requested amount of memory in bytes.
+ *
+ * The function is used to reserve the requested amount of memory in bytes and initializes it to 0.
+ *
+ * @param length Amount of bytes to reserve.
+ *
+ * @return Pointer to the reserved memory. NULL if memory can't be allocated.
+ */
+void *USB_OsaMemoryAllocate(uint32_t length);
+
+/*!
+ * @brief Frees the memory previously reserved.
+ *
+ * The function is used to free the memory block previously reserved.
+ *
+ * @param p Pointer to the start of the memory block previously reserved.
+ *
+ */
+extern void USB_OsaMemoryFree(void *p);
+
+/* @} */
+
+/*!
+ * @name USB OSA Event
+ * @{
+ */
+
+/*!
+ * @brief Creates an event object with all flags cleared.
+ *
+ * This function creates an event object and sets its clear mode. If the clear mode
+ * is kUSB_OsaEventAutoClear, when a task gets the event flags, these flags are
+ * cleared automatically. If the clear mode is kUSB_OsaEventManualClear, the flags must
+ * be cleared manually.
+ *
+ * @param handle It is an out parameter, which is used to return the pointer of the event object.
+ * @param flag The event is auto-clear or manual-clear. See the enumeration #usb_osa_event_mode_t.
+ *
+ * @return A USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_event_handle eventHandle;
+ usb_osa_status_t usbOsaStatus;
+ usbOsaStatus = USB_OsaEventCreate(&eventHandle, kUSB_OsaEventManualClear);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaEventCreate(usb_osa_event_handle *handle, uint32_t flag);
+
+/*!
+ * @brief Destroys a created event object.
+ *
+ * @param handle Pointer to the event object.
+ *
+ * @return A USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_status_t usbOsaStatus;
+ ...
+ usbOsaStatus = USB_OsaEventDestroy(eventHandle);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaEventDestroy(usb_osa_event_handle handle);
+
+/*!
+ * @brief Sets an event flag.
+ *
+ * Sets specified flags for an event object.
+ *
+ * @param handle Pointer to the event object.
+ * @param bitMask Event flags to be set.
+ *
+ * @return A USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_status_t usbOsaStatus;
+ ...
+ usbOsaStatus = USB_OsaEventSet(eventHandle, 0x01U);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaEventSet(usb_osa_event_handle handle, uint32_t bitMask);
+
+/*!
+ * @brief Waits for an event flag.
+ *
+ * This function waits for a combination of flags to be set in an event object.
+ * An applications can wait for any/all bits to be set. This function can
+ * get the flags that wake up the waiting task.
+ *
+ * @param handle Pointer to the event object.
+ * @param bitMask Event flags to wait.
+ * @param flag Wait all flags or any flag to be set. 0U - wait any flag, others, wait all flags.
+ * @param timeout The maximum number of milliseconds to wait for the event.
+ * If the wait condition is not met, passing 0U
+ * waits indefinitely when the environment is an RTOS and returns the kStatus_OSA_Timeout
+ * immediately. Pass any value for the bare metal.
+ * @param bitSet Flags that wake up the waiting task are obtained by this parameter.
+ *
+ * @return An USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_status_t usbOsaStatus;
+ uint32_t bitSet;
+ ...
+ usbOsaStatus = USB_OsaEventWait(eventHandle, 0x01U, 0U, 0U, &bitSet);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaEventWait(
+ usb_osa_event_handle handle, uint32_t bitMask, uint32_t flag, uint32_t timeout, uint32_t *bitSet);
+
+/*!
+ * @brief Checks an event flag.
+ *
+ * This function checks for a combination of flags to be set in an event object.
+ *
+ * @param handle Pointer to the event object.
+ * @param bitMask Event flags to check.
+ * @param bitSet Flags have been set.
+ *
+ * @return An USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_status_t usbOsaStatus;
+ uint32_t bitSet;
+ ...
+ usbOsaStatus = USB_OsaEventCheck(eventHandle, 0x01U, &bitSet);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaEventCheck(usb_osa_event_handle handle, uint32_t bitMask, uint32_t *bitSet);
+
+/*!
+ * @brief Clears an event flag.
+ *
+ * This function clears flags of an event object.
+ *
+ * @param handle Pointer to the event object
+ * @param bitMask Event flags to be cleared.
+ *
+ * @return An USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_status_t usbOsaStatus;
+ ...
+ usbOsaStatus = USB_OsaEventClear(eventHandle, 0x01U);
+ @endcode
+ */
+extern usb_osa_status_t USB_OsaEventClear(usb_osa_event_handle handle, uint32_t bitMask);
+/* @} */
+
+/*!
+ * @name USB OSA Semaphore
+ * @{
+ */
+
+/*!
+ * @brief Creates a semaphore with a given value.
+ *
+ * This function creates a semaphore and sets the default count.
+ *
+ * @param handle It is an out parameter, which is used to return pointer of the semaphore object.
+ * @param count Initializes a value of the semaphore.
+ *
+ * @return An USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_sem_handle semHandle;
+ usb_osa_status_t usbOsaStatus;
+ usbOsaStatus = USB_OsaSemCreate(&semHandle, 1U);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaSemCreate(usb_osa_sem_handle *handle, uint32_t count);
+
+/*!
+ * @brief Destroys a semaphore object.
+ *
+ * This function destroys a semaphore object.
+ *
+ * @param handle Pointer to the semaphore.
+ *
+ * @return An USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_sem_handle semHandle;
+ usb_osa_status_t usbOsaStatus;
+ ...
+ usbOsaStatus = USB_OsaSemDestroy(semHandle);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaSemDestroy(usb_osa_sem_handle handle);
+
+/*!
+ * @brief Posts a semaphore.
+ *
+ * This function wakes up a task waiting on the semaphore. If a task is not pending, increases the semaphore's
+ value.
+ *
+ * @param handle Pointer to the semaphore.
+ *
+ * @return A USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_sem_handle semHandle;
+ usb_osa_status_t usbOsaStatus;
+ ...
+ usbOsaStatus = USB_OsaSemPost(semHandle);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaSemPost(usb_osa_sem_handle handle);
+
+/*!
+ * @brief Waits on a semaphore.
+ *
+ * This function checks the semaphore's value. If it is positive, it decreases the semaphore's value and return
+ kStatus_OSA_Success.
+ *
+ * @param handle Pointer to the semaphore.
+ * @param timeout The maximum number of milliseconds to wait for the semaphore.
+ * If the wait condition is not met, passing 0U
+ * waits indefinitely when environment is RTOS. And return kStatus_OSA_Timeout
+ * immediately for bare metal no matter what value has been passed.
+ *
+ * @return A USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_sem_handle semHandle;
+ usb_osa_status_t usbOsaStatus;
+ ...
+ usbOsaStatus = USB_OsaSemWait(semHandle, 0U);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaSemWait(usb_osa_sem_handle handle, uint32_t timeout);
+/* @} */
+
+/*!
+ * @name USB OSA Mutex
+ * @{
+ */
+
+/*!
+ * @brief Creates a mutex.
+ *
+ * This function creates a mutex and sets it to an unlocked status.
+ *
+ * @param handle It is out parameter, which is used to return the pointer of the mutex object.
+ *
+ * @return A USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_mutex_handle mutexHandle;
+ usb_osa_status_t usbOsaStatus;
+ usbOsaStatus = USB_OsaMutexCreate(&mutexHandle);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaMutexCreate(usb_osa_mutex_handle *handle);
+
+/*!
+ * @brief Destroys a mutex.
+ *
+ * This function destroys a mutex and sets it to an unlocked status.
+ *
+ * @param handle Pointer to the mutex.
+ *
+ * @return A USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_mutex_handle mutexHandle;
+ usb_osa_status_t usbOsaStatus;
+ ...
+ usbOsaStatus = USB_OsaMutexDestroy(mutexHandle);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaMutexDestroy(usb_osa_mutex_handle handle);
+
+/*!
+ * @brief Waits for a mutex and locks it.
+ *
+ * This function checks the mutex status. If it is unlocked, it locks it and returns the
+ * kStatus_OSA_Success. Otherwise, it waits forever to lock in RTOS and returns the
+ * kStatus_OSA_Success immediately for bare metal.
+ *
+ * @param handle Pointer to the mutex.
+ *
+ * @return A USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_mutex_handle mutexHandle;
+ usb_osa_status_t usbOsaStatus;
+ ...
+ usbOsaStatus = USB_OsaMutexLock(mutexHandle);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaMutexLock(usb_osa_mutex_handle handle);
+
+/*!
+ * @brief Unlocks a mutex.
+ *
+ * This function unlocks a mutex.
+ *
+ * @param handle Pointer to the mutex.
+ *
+ * @return A USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_mutex_handle mutexHandle;
+ usb_osa_status_t usbOsaStatus;
+ ...
+ usbOsaStatus = USB_OsaMutexUnlock(mutexHandle);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaMutexUnlock(usb_osa_mutex_handle handle);
+/* @} */
+
+/*!
+ * @name USB OSA Message Queue
+ * @{
+ */
+
+/*!
+ * @brief Creates a message queue.
+ *
+ * This function creates a message queue.
+ *
+ * @param handle It is an out parameter, which is used to return a pointer of the message queue object.
+ * @param count The count of elements in the queue.
+ * @param size Size of every elements in words.
+ *
+ * @return A USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_msgq_handle msgqHandle;
+ usb_osa_status_t usbOsaStatus;
+ usbOsaStatus = USB_OsaMsgqCreate(msgqHandle, 8U, 4U);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaMsgqCreate(usb_osa_msgq_handle *handle, uint32_t count, uint32_t size);
+
+/*!
+ * @brief Destroys a message queue.
+ *
+ * This function destroys a message queue.
+ *
+ * @param handle Pointer to a message queue.
+ *
+ * @return A USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_msgq_handle msgqHandle;
+ usb_osa_status_t usbOsaStatus;
+ ...
+ usbOsaStatus = USB_OsaMsgqDestroy(msgqHandle);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaMsgqDestroy(usb_osa_msgq_handle handle);
+
+/*!
+ * @brief Sends a message.
+ *
+ * This function sends a message to the tail of the message queue.
+ *
+ * @param handle Pointer to a message queue.
+ * @param msg The pointer to a message to be put into the queue.
+ *
+ * @return A USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_msgq_handle msgqHandle;
+ message_struct_t message;
+ usb_osa_status_t usbOsaStatus;
+ ...
+ usbOsaStatus = USB_OsaMsgqSend(msgqHandle, &message);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaMsgqSend(usb_osa_msgq_handle handle, void *msg);
+
+/*!
+ * @brief Receives a message.
+ *
+ * This function receives a message from the head of the message queue.
+ *
+ * @param handle Pointer to a message queue.
+ * @param msg The pointer to save a received message.
+ * @param timeout The maximum number of milliseconds to wait for a message.
+ * If the wait condition is not met, passing 0U
+ * waits indefinitely when an environment is RTOS and returns the kStatus_OSA_Timeout
+ * immediately for bare metal.
+ *
+ * @return A USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_msgq_handle msgqHandle;
+ message_struct_t message;
+ usb_osa_status_t usbOsaStatus;
+ ...
+ usbOsaStatus = USB_OsaMsgqRecv(msgqHandle, &message, 0U);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaMsgqRecv(usb_osa_msgq_handle handle, void *msg, uint32_t timeout);
+
+/*!
+ * @brief Checks a message queue and receives a message if the queue is not empty.
+ *
+ * This function checks a message queue and receives a message if the queue is not empty.
+ *
+ * @param handle Pointer to a message queue.
+ * @param msg The pointer to save a received message.
+ *
+ * @return A USB OSA error code or kStatus_OSA_Success.
+ *
+ * Example:
+ @code
+ usb_osa_msgq_handle msgqHandle;
+ message_struct_t message;
+ usb_osa_status_t usbOsaStatus;
+ ...
+ usbOsaStatus = USB_OsaMsgqCheck(msgqHandle, &message);
+ @endcode
+ *
+ */
+extern usb_osa_status_t USB_OsaMsgqCheck(usb_osa_msgq_handle handle, void *msg);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* @} */
+
+#endif /* __USB_OSA_H__ */
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "stdint.h"
+#include "usb.h"
+#include "usb_osa.h"
+#include "stdlib.h"
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define USB_OSA_BM_EVENT_COUNT (4U)
+#define USB_OSA_BM_SEM_COUNT (1U)
+#define USB_OSA_BM_MSGQ_COUNT (1U)
+#define USB_OSA_BM_MSG_COUNT (8U)
+#define USB_OSA_BM_MSG_SIZE (4U)
+
+/* BM Event status structure */
+typedef struct _usb_osa_event_struct
+{
+ uint32_t value; /* Event mask */
+ uint32_t flag; /* Event flags, includes auto clear flag */
+ uint8_t isUsed; /* Is used */
+} usb_osa_event_struct_t;
+
+/* BM semaphore status structure */
+typedef struct _usb_osa_sem_struct
+{
+ uint32_t value; /* Semaphore count */
+ uint8_t isUsed; /* Is used */
+} usb_osa_sem_struct_t;
+
+/* BM msg status structure */
+typedef struct _usb_osa_msg_struct
+{
+ uint32_t msg[USB_OSA_BM_MSG_SIZE]; /* Message entity pointer */
+} usb_osa_msg_struct_t;
+
+/* BM msgq status structure */
+typedef struct _usb_osa_msgq_struct
+{
+ usb_osa_msg_struct_t msgs[USB_OSA_BM_MSG_COUNT]; /* Message entity list */
+ uint32_t count; /* Max message entity count */
+ uint32_t msgSize; /* Size of each message */
+ uint32_t msgCount; /* Valid messages */
+ uint32_t index; /* The first empty message entity index */
+ uint32_t current; /* The vaild message index */
+ uint8_t isUsed; /* Is used */
+} usb_osa_msgq_struct_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+USB_GLOBAL USB_RAM_ADDRESS_ALIGNMENT(USB_DATA_ALIGN_SIZE) static usb_osa_sem_struct_t
+ s_UsbBmSemStruct[USB_OSA_BM_SEM_COUNT];
+USB_GLOBAL USB_RAM_ADDRESS_ALIGNMENT(USB_DATA_ALIGN_SIZE) static usb_osa_event_struct_t
+ s_UsbBmEventStruct[USB_OSA_BM_EVENT_COUNT];
+USB_GLOBAL USB_RAM_ADDRESS_ALIGNMENT(USB_DATA_ALIGN_SIZE) static usb_osa_msgq_struct_t
+ s_UsbBmMsgqStruct[USB_OSA_BM_MSGQ_COUNT];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void *USB_OsaMemoryAllocate(uint32_t length)
+{
+ void *p = (void *)malloc(length);
+ uint8_t *temp = (uint8_t *)p;
+ if (p)
+ {
+ for (uint32_t count = 0U; count < length; count++)
+ {
+ temp[count] = 0U;
+ }
+ }
+ return p;
+}
+
+void USB_OsaMemoryFree(void *p)
+{
+ free(p);
+}
+
+void USB_OsaEnterCritical(uint32_t *sr)
+{
+ *sr = DisableGlobalIRQ();
+ __ASM("CPSID I");
+}
+
+void USB_OsaExitCritical(uint32_t sr)
+{
+ EnableGlobalIRQ(sr);
+}
+
+usb_osa_status_t USB_OsaEventCreate(usb_osa_event_handle *handle, uint32_t flag)
+{
+ usb_osa_event_struct_t *event = NULL;
+ USB_OSA_SR_ALLOC();
+
+ if (!handle)
+ {
+ return kStatus_USB_OSA_Error;
+ }
+
+ USB_OSA_ENTER_CRITICAL();
+ for (uint32_t i = 0; i < USB_OSA_BM_EVENT_COUNT; i++)
+ {
+ if (0 == s_UsbBmEventStruct[i].isUsed)
+ {
+ event = &s_UsbBmEventStruct[i];
+ break;
+ }
+ }
+
+ if (NULL == event)
+ {
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_Error;
+ }
+
+ event->value = 0U;
+ event->flag = flag;
+ event->isUsed = 1;
+ *handle = event;
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_Success;
+}
+
+usb_osa_status_t USB_OsaEventDestroy(usb_osa_event_handle handle)
+{
+ usb_osa_event_struct_t *event = (usb_osa_event_struct_t *)handle;
+ USB_OSA_SR_ALLOC();
+
+ if (handle)
+ {
+ USB_OSA_ENTER_CRITICAL();
+ event->isUsed = 0;
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_Success;
+ }
+ return kStatus_USB_OSA_Error;
+}
+
+usb_osa_status_t USB_OsaEventSet(usb_osa_event_handle handle, uint32_t bitMask)
+{
+ usb_osa_event_struct_t *event = (usb_osa_event_struct_t *)handle;
+ USB_OSA_SR_ALLOC();
+
+ if (handle)
+ {
+ USB_OSA_ENTER_CRITICAL();
+ event->value |= bitMask;
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_Success;
+ }
+ return kStatus_USB_OSA_Error;
+}
+
+usb_osa_status_t USB_OsaEventWait(
+ usb_osa_event_handle handle, uint32_t bitMask, uint32_t flag, uint32_t timeout, uint32_t *bitSet)
+{
+ usb_osa_event_struct_t *event = (usb_osa_event_struct_t *)handle;
+ uint32_t bits;
+ USB_OSA_SR_ALLOC();
+
+ if (handle)
+ {
+ USB_OSA_ENTER_CRITICAL();
+ bits = event->value & bitMask;
+ if (flag)
+ {
+ if (bits != bitMask)
+ {
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_TimeOut;
+ }
+ }
+ else
+ {
+ if (!bits)
+ {
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_TimeOut;
+ }
+ }
+ if (bitSet)
+ {
+ *bitSet = bits;
+ }
+ if (event->flag)
+ {
+ event->value &= ~bits;
+ }
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_Success;
+ }
+ return kStatus_USB_OSA_Error;
+}
+
+usb_osa_status_t USB_OsaEventCheck(usb_osa_event_handle handle, uint32_t bitMask, uint32_t *bitSet)
+{
+ usb_osa_event_struct_t *event = (usb_osa_event_struct_t *)handle;
+ uint32_t bits;
+ USB_OSA_SR_ALLOC();
+
+ if (handle)
+ {
+ USB_OSA_ENTER_CRITICAL();
+ bits = event->value & bitMask;
+
+ if (!bits)
+ {
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_Error;
+ }
+
+ if (bitSet)
+ {
+ *bitSet = bits;
+ }
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_Success;
+ }
+ return kStatus_USB_OSA_Error;
+}
+
+usb_osa_status_t USB_OsaEventClear(usb_osa_event_handle handle, uint32_t bitMask)
+{
+ usb_osa_event_struct_t *event = (usb_osa_event_struct_t *)handle;
+ uint32_t bits;
+ USB_OSA_SR_ALLOC();
+
+ if (handle)
+ {
+ USB_OSA_ENTER_CRITICAL();
+ bits = event->value & bitMask;
+ event->value &= ~bits;
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_Success;
+ }
+ return kStatus_USB_OSA_Error;
+}
+
+usb_osa_status_t USB_OsaSemCreate(usb_osa_sem_handle *handle, uint32_t count)
+{
+ usb_osa_sem_struct_t *sem = NULL;
+ USB_OSA_SR_ALLOC();
+
+ if (!handle)
+ {
+ return kStatus_USB_OSA_Error;
+ }
+
+ USB_OSA_ENTER_CRITICAL();
+ for (uint32_t i = 0; i < USB_OSA_BM_SEM_COUNT; i++)
+ {
+ if (0 == s_UsbBmSemStruct[i].isUsed)
+ {
+ sem = &s_UsbBmSemStruct[i];
+ break;
+ }
+ }
+ if (NULL == sem)
+ {
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_Error;
+ }
+
+ sem->value = count;
+ sem->isUsed = 1;
+ *handle = sem;
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_Success;
+}
+
+usb_osa_status_t USB_OsaSemDestroy(usb_osa_sem_handle handle)
+{
+ usb_osa_sem_struct_t *sem = (usb_osa_sem_struct_t *)handle;
+ USB_OSA_SR_ALLOC();
+
+ if (handle)
+ {
+ USB_OSA_ENTER_CRITICAL();
+ sem->isUsed = 0;
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_Success;
+ }
+ return kStatus_USB_OSA_Error;
+}
+
+usb_osa_status_t USB_OsaSemPost(usb_osa_sem_handle handle)
+{
+ usb_osa_sem_struct_t *sem = (usb_osa_sem_struct_t *)handle;
+ USB_OSA_SR_ALLOC();
+
+ if (!handle)
+ {
+ return kStatus_USB_OSA_Error;
+ }
+
+ USB_OSA_ENTER_CRITICAL();
+ sem->value++;
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_Success;
+}
+
+usb_osa_status_t USB_OsaSemWait(usb_osa_sem_handle handle, uint32_t timeout)
+{
+ usb_osa_sem_struct_t *sem = (usb_osa_sem_struct_t *)handle;
+ USB_OSA_SR_ALLOC();
+
+ if (!handle)
+ {
+ return kStatus_USB_OSA_Error;
+ }
+
+ USB_OSA_ENTER_CRITICAL();
+ if (sem->value)
+ {
+ sem->value--;
+ }
+ else
+ {
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_TimeOut;
+ }
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_Success;
+}
+
+usb_osa_status_t USB_OsaMutexCreate(usb_osa_mutex_handle *handle)
+{
+ if (!handle)
+ {
+ return kStatus_USB_OSA_Error;
+ }
+ *handle = (usb_osa_mutex_handle)0xFFFF0000U;
+ return kStatus_USB_OSA_Success;
+}
+
+usb_osa_status_t USB_OsaMutexDestroy(usb_osa_mutex_handle handle)
+{
+ return kStatus_USB_OSA_Success;
+}
+usb_osa_status_t USB_OsaMutexLock(usb_osa_mutex_handle handle)
+{
+ return kStatus_USB_OSA_Success;
+}
+usb_osa_status_t USB_OsaMutexUnlock(usb_osa_mutex_handle handle)
+{
+ return kStatus_USB_OSA_Success;
+}
+
+usb_osa_status_t USB_OsaMsgqCreate(usb_osa_msgq_handle *handle, uint32_t count, uint32_t size)
+{
+ usb_osa_msgq_struct_t *msgq = NULL;
+ USB_OSA_SR_ALLOC();
+
+ if (!handle)
+ {
+ return kStatus_USB_OSA_Error;
+ }
+ USB_OSA_ENTER_CRITICAL();
+
+ for (uint32_t i = 0; i < USB_OSA_BM_MSGQ_COUNT; i++)
+ {
+ if (0 == s_UsbBmMsgqStruct[i].isUsed)
+ {
+ msgq = &s_UsbBmMsgqStruct[i];
+ break;
+ }
+ }
+ if ((NULL == msgq) || (count > USB_OSA_BM_MSG_COUNT) || (size > USB_OSA_BM_MSG_SIZE))
+ {
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_Error;
+ }
+ msgq->count = count;
+ msgq->msgSize = size;
+ msgq->msgCount = 0U;
+ msgq->index = 0U;
+ msgq->current = 0U;
+ msgq->isUsed = 1;
+ *handle = msgq;
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_Success;
+}
+
+usb_osa_status_t USB_OsaMsgqDestroy(usb_osa_msgq_handle handle)
+{
+ usb_osa_msgq_struct_t *msgq = (usb_osa_msgq_struct_t *)handle;
+ USB_OSA_SR_ALLOC();
+
+ if (!handle)
+ {
+ return kStatus_USB_OSA_Error;
+ }
+ USB_OSA_ENTER_CRITICAL();
+ msgq->isUsed = 0;
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_Success;
+}
+
+usb_osa_status_t USB_OsaMsgqSend(usb_osa_msgq_handle handle, void *msg)
+{
+ usb_osa_msgq_struct_t *msgq = (usb_osa_msgq_struct_t *)handle;
+ usb_osa_msg_struct_t *msgEntity;
+ uint32_t *p;
+ uint32_t *q;
+ uint32_t count;
+ USB_OSA_SR_ALLOC();
+
+ if (!handle)
+ {
+ return kStatus_USB_OSA_Error;
+ }
+ USB_OSA_ENTER_CRITICAL();
+ if (msgq->msgCount >= msgq->count)
+ {
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_Error;
+ }
+
+ msgEntity = &msgq->msgs[msgq->index];
+ p = (uint32_t *)&msgEntity->msg[0];
+ q = (uint32_t *)msg;
+
+ for (count = 0U; count < msgq->msgSize; count++)
+ {
+ p[count] = q[count];
+ }
+
+ if (0U == msgq->msgCount)
+ {
+ msgq->current = msgq->index;
+ }
+
+ msgq->msgCount++;
+ msgq->index++;
+ msgq->index = msgq->index % msgq->count;
+
+ USB_OSA_EXIT_CRITICAL();
+
+ return kStatus_USB_OSA_Success;
+}
+
+usb_osa_status_t USB_OsaMsgqRecv(usb_osa_msgq_handle handle, void *msg, uint32_t timeout)
+{
+ usb_osa_msgq_struct_t *msgq = (usb_osa_msgq_struct_t *)handle;
+ usb_osa_msg_struct_t *msgEntity;
+ uint32_t *p;
+ uint32_t *q;
+ uint32_t count;
+ USB_OSA_SR_ALLOC();
+
+ if (!handle)
+ {
+ return kStatus_USB_OSA_Error;
+ }
+ USB_OSA_ENTER_CRITICAL();
+ if (msgq->msgCount < 1U)
+ {
+ USB_OSA_EXIT_CRITICAL();
+ return kStatus_USB_OSA_TimeOut;
+ }
+
+ msgEntity = &msgq->msgs[msgq->current];
+ q = (uint32_t *)&msgEntity->msg[0];
+ p = (uint32_t *)msg;
+
+ for (count = 0U; count < msgq->msgSize; count++)
+ {
+ p[count] = q[count];
+ }
+
+ msgq->msgCount--;
+ msgq->current++;
+ msgq->current = msgq->current % msgq->count;
+
+ USB_OSA_EXIT_CRITICAL();
+
+ return kStatus_USB_OSA_Success;
+}
+
+usb_osa_status_t USB_OsaMsgqCheck(usb_osa_msgq_handle handle, void *msg)
+{
+ usb_osa_msgq_struct_t *msgq = (usb_osa_msgq_struct_t *)handle;
+ uint32_t msgCount;
+ USB_OSA_SR_ALLOC();
+
+ if (!handle)
+ {
+ return kStatus_USB_OSA_Error;
+ }
+
+ USB_OSA_ENTER_CRITICAL();
+ msgCount = msgq->msgCount;
+ USB_OSA_EXIT_CRITICAL();
+
+ if (msgCount)
+ {
+ if (kStatus_USB_OSA_Success == USB_OsaMsgqRecv(msgq, msg, 0U))
+ {
+ return kStatus_USB_OSA_Success;
+ }
+ }
+
+ return kStatus_USB_OSA_Error;
+}
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __USB_OSA_BM_H__
+#define __USB_OSA_BM_H__
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define USB_OSA_SR_ALLOC() uint32_t usbOsaCurrentSr;
+#define USB_OSA_ENTER_CRITICAL() USB_OsaEnterCritical(&usbOsaCurrentSr)
+#define USB_OSA_EXIT_CRITICAL() USB_OsaExitCritical(usbOsaCurrentSr)
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+extern void USB_OsaEnterCritical(uint32_t *sr);
+extern void USB_OsaExitCritical(uint32_t sr);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __USB_OSA_BM_H__ */
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __USB_SPEC_H__
+#define __USB_SPEC_H__
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* USB speed (the value cannot be changed because EHCI QH use the value directly)*/
+#define USB_SPEED_FULL (0x00U)
+#define USB_SPEED_LOW (0x01U)
+#define USB_SPEED_HIGH (0x02U)
+
+/* Set up packet structure */
+typedef struct _usb_setup_struct
+{
+ uint8_t bmRequestType;
+ uint8_t bRequest;
+ uint16_t wValue;
+ uint16_t wIndex;
+ uint16_t wLength;
+} usb_setup_struct_t;
+
+/* USB standard descriptor endpoint type */
+#define USB_ENDPOINT_CONTROL (0x00U)
+#define USB_ENDPOINT_ISOCHRONOUS (0x01U)
+#define USB_ENDPOINT_BULK (0x02U)
+#define USB_ENDPOINT_INTERRUPT (0x03U)
+
+/* USB standard descriptor transfer direction (cannot change the value because iTD use the value directly) */
+#define USB_OUT (0U)
+#define USB_IN (1U)
+
+/* USB standard descriptor length */
+#define USB_DESCRIPTOR_LENGTH_DEVICE (0x12U)
+#define USB_DESCRIPTOR_LENGTH_CONFIGURE (0x09U)
+#define USB_DESCRIPTOR_LENGTH_INTERFACE (0x09U)
+#define USB_DESCRIPTOR_LENGTH_ENDPOINT (0x07U)
+#define USB_DESCRIPTOR_LENGTH_DEVICE_QUALITIER (0x0AU)
+#define USB_DESCRIPTOR_LENGTH_OTG_DESCRIPTOR (5U)
+#define USB_DESCRIPTOR_LENGTH_BOS_DESCRIPTOR (5U)
+
+/* USB Device Capability Type Codes */
+#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_WIRELESS (0x01U)
+#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_USB20_EXTENSION (0x02U)
+#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_SUPERSPEED (0x03U)
+
+/* USB standard descriptor type */
+#define USB_DESCRIPTOR_TYPE_DEVICE (0x01U)
+#define USB_DESCRIPTOR_TYPE_CONFIGURE (0x02U)
+#define USB_DESCRIPTOR_TYPE_STRING (0x03U)
+#define USB_DESCRIPTOR_TYPE_INTERFACE (0x04U)
+#define USB_DESCRIPTOR_TYPE_ENDPOINT (0x05U)
+#define USB_DESCRIPTOR_TYPE_DEVICE_QUALITIER (0x06U)
+#define USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION (0x07U)
+#define USB_DESCRIPTOR_TYPE_INTERFAACE_POWER (0x08U)
+#define USB_DESCRIPTOR_TYPE_OTG (0x09U)
+#define USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION (0x0BU)
+#define USB_DESCRIPTOR_TYPE_BOS (0x0F)
+#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY (0x10)
+
+#define USB_DESCRIPTOR_TYPE_HID (0x21U)
+#define USB_DESCRIPTOR_TYPE_HID_REPORT (0x22U)
+#define USB_DESCRIPTOR_TYPE_HID_PHYSICAL (0x23U)
+
+/* USB standard request type */
+#define USB_REQUEST_TYPE_DIR_MASK (0x80U)
+#define USB_REQUEST_TYPE_DIR_SHIFT (7U)
+#define USB_REQUEST_TYPE_DIR_OUT (0x00U)
+#define USB_REQUEST_TYPE_DIR_IN (0x80U)
+
+#define USB_REQUEST_TYPE_TYPE_MASK (0x60U)
+#define USB_REQUEST_TYPE_TYPE_SHIFT (5U)
+#define USB_REQUEST_TYPE_TYPE_STANDARD (0U)
+#define USB_REQUEST_TYPE_TYPE_CLASS (0x20U)
+#define USB_REQUEST_TYPE_TYPE_VENDOR (0x40U)
+
+#define USB_REQUEST_TYPE_RECIPIENT_MASK (0x1FU)
+#define USB_REQUEST_TYPE_RECIPIENT_SHIFT (0U)
+#define USB_REQUEST_TYPE_RECIPIENT_DEVICE (0x00U)
+#define USB_REQUEST_TYPE_RECIPIENT_INTERFACE (0x01U)
+#define USB_REQUEST_TYPE_RECIPIENT_ENDPOINT (0x02U)
+#define USB_REQUEST_TYPE_RECIPIENT_OTHER (0x03U)
+
+/* USB standard request */
+#define USB_REQUEST_STANDARD_GET_STATUS (0x00U)
+#define USB_REQUEST_STANDARD_CLEAR_FEATURE (0x01U)
+#define USB_REQUEST_STANDARD_SET_FEATURE (0x03U)
+#define USB_REQUEST_STANDARD_SET_ADDRESS (0x05U)
+#define USB_REQUEST_STANDARD_GET_DESCRIPTOR (0x06U)
+#define USB_REQUEST_STANDARD_SET_DESCRIPTOR (0x07U)
+#define USB_REQUEST_STANDARD_GET_CONFIGURATION (0x08U)
+#define USB_REQUEST_STANDARD_SET_CONFIGURATION (0x09U)
+#define USB_REQUEST_STANDARD_GET_INTERFACE (0x0AU)
+#define USB_REQUEST_STANDARD_SET_INTERFACE (0x0BU)
+#define USB_REQUEST_STANDARD_SYNCH_FRAME (0x0CU)
+
+/* USB standard request GET Status */
+#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_SELF_POWERED_SHIFT (0U)
+#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_REMOTE_WARKUP_SHIFT (1U)
+
+#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_MASK (0x01U)
+#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_SHIFT (0U)
+
+#define USB_REQUEST_STANDARD_GET_STATUS_OTG_STATUS_SELECTOR (0xF000U)
+
+/* USB standard request CLEAR/SET feature */
+#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT (0U)
+#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_REMOTE_WAKEUP (1U)
+#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_TEST_MODE (2U)
+#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_B_HNP_ENABLE (3U)
+#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_HNP_SUPPORT (4U)
+#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_ALT_HNP_SUPPORT (5U)
+
+/* USB standard descriptor configure bmAttributes */
+#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_MASK (0x80U)
+#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_SHIFT (7U)
+
+#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_MASK (0x40U)
+#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_SHIFT (6U)
+
+#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_MASK (0x20U)
+#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_SHIFT (5U)
+
+/* USB standard descriptor endpoint bmAttributes */
+#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK (0x80U)
+#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT (7U)
+#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_OUT (0U)
+#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN (0x80U)
+
+#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_MASK (0x0FU)
+#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_SHFIT (0U)
+
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_TYPE_MASK (0x03U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_NUMBER_SHFIT (0U)
+
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_MASK (0x0CU)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SHFIT (2U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_NO_SYNC (0x00U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ASYNC (0x04U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ADAPTIVE (0x08U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SYNC (0x0CU)
+
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_MASK (0x30U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_SHFIT (4U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_DATA_ENDPOINT (0x00U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_FEEDBACK_ENDPOINT (0x10U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_IMPLICIT_FEEDBACK_DATA_ENDPOINT (0x20U)
+
+#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_SIZE_MASK (0x07FFu)
+#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK (0x1800u)
+#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_SHFIT (11U)
+
+/* USB standard descriptor otg bmAttributes */
+#define USB_DESCRIPTOR_OTG_ATTRIBUTES_SRP_MASK (0x01u)
+#define USB_DESCRIPTOR_OTG_ATTRIBUTES_HNP_MASK (0x02u)
+#define USB_DESCRIPTOR_OTG_ATTRIBUTES_ADP_MASK (0x04u)
+
+/* USB standard descriptor device capability usb20 extension bmAttributes */
+#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_MASK (0x02U)
+#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_SHIFT (1U)
+#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_MASK (0x04U)
+#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_SHIFT (2U)
+
+
+/* Language structure */
+typedef struct _usb_language
+{
+ uint8_t **string; /* The Strings descriptor array */
+ uint32_t *length; /* The strings descriptor length array */
+ uint16_t languageId; /* The language id of current language */
+} usb_language_t;
+
+typedef struct _usb_language_list
+{
+ uint8_t *languageString; /* The String 0U pointer */
+ uint32_t stringLength; /* The String 0U Length */
+ usb_language_t *languageList; /* The language list */
+ uint8_t count; /* The language count */
+} usb_language_list_t;
+
+typedef struct _usb_descriptor_common
+{
+ uint8_t bLength; /* Size of this descriptor in bytes */
+ uint8_t bDescriptorType; /* DEVICE Descriptor Type */
+ uint8_t bData[1]; /* Data */
+} usb_descriptor_common_t;
+
+typedef struct _usb_descriptor_device
+{
+ uint8_t bLength; /* Size of this descriptor in bytes */
+ uint8_t bDescriptorType; /* DEVICE Descriptor Type */
+ uint8_t bcdUSB[2]; /* UUSB Specification Release Number in Binary-Coded Decimal, e.g. 0x0200U */
+ uint8_t bDeviceClass; /* Class code */
+ uint8_t bDeviceSubClass; /* Sub-Class code */
+ uint8_t bDeviceProtocol; /* Protocol code */
+ uint8_t bMaxPacketSize0; /* Maximum packet size for endpoint zero */
+ uint8_t idVendor[2]; /* Vendor ID (assigned by the USB-IF) */
+ uint8_t idProduct[2]; /* Product ID (assigned by the manufacturer) */
+ uint8_t bcdDevice[2]; /* Device release number in binary-coded decimal */
+ uint8_t iManufacturer; /* Index of string descriptor describing manufacturer */
+ uint8_t iProduct; /* Index of string descriptor describing product */
+ uint8_t iSerialNumber; /* Index of string descriptor describing the device serial number */
+ uint8_t bNumConfigurations; /* Number of possible configurations */
+} usb_descriptor_device_t;
+
+typedef struct _usb_descriptor_configuration
+{
+ uint8_t bLength; /* Descriptor size in bytes = 9U */
+ uint8_t bDescriptorType; /* CONFIGURATION type = 2U or 7U */
+ uint8_t wTotalLength[2]; /* Length of concatenated descriptors */
+ uint8_t bNumInterfaces; /* Number of interfaces, this configuration. */
+ uint8_t bConfigurationValue; /* Value to set this configuration. */
+ uint8_t iConfiguration; /* Index to configuration string */
+ uint8_t bmAttributes; /* Configuration characteristics */
+ uint8_t bMaxPower; /* Maximum power from bus, 2 mA units */
+} usb_descriptor_configuration_t;
+
+typedef struct _usb_descriptor_interface
+{
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bInterfaceNumber;
+ uint8_t bAlternateSetting;
+ uint8_t bNumEndpoints;
+ uint8_t bInterfaceClass;
+ uint8_t bInterfaceSubClass;
+ uint8_t bInterfaceProtocol;
+ uint8_t iInterface;
+} usb_descriptor_interface_t;
+
+typedef struct _usb_descriptor_endpoint
+{
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bEndpointAddress;
+ uint8_t bmAttributes;
+ uint8_t wMaxPacketSize[2];
+ uint8_t bInterval;
+} usb_descriptor_endpoint_t;
+
+typedef struct _usb_descriptor_binary_device_object_store
+{
+ uint8_t bLength; /* Descriptor size in bytes = 5U */
+ uint8_t bDescriptorType; /* BOS Descriptor type = 0FU*/
+ uint8_t wTotalLength[2]; /*Length of this descriptor and all of its sub descriptors*/
+ uint8_t bNumDeviceCaps; /*The number of separate device capability descriptors in the BOS*/
+} usb_descriptor_bos_t;
+
+typedef struct _usb_descriptor_usb20_extension
+{
+ uint8_t bLength; /* Descriptor size in bytes = 7U */
+ uint8_t bDescriptorType; /* DEVICE CAPABILITY Descriptor type = 0x10U*/
+ uint8_t bDevCapabilityType; /*Length of this descriptor and all of its sub descriptors*/
+ uint8_t bmAttributes[4]; /*Bitmap encoding of supported device level features.*/
+} usb_descriptor_usb20_extension_t;
+
+typedef union _usb_descriptor_union
+{
+ usb_descriptor_common_t common; /* Common descriptor */
+ usb_descriptor_device_t device; /* Device descriptor */
+ usb_descriptor_configuration_t configuration; /* Configuration descriptor */
+ usb_descriptor_interface_t interface; /* Interface descriptor */
+ usb_descriptor_endpoint_t endpoint; /* Endpoint descriptor */
+} usb_descriptor_union_t;
+
+#endif /* __USB_SPEC_H__ */
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_device_registers.h"
+#include "clock_config.h"
+#include "board.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "usb_device_config.h"
+#include "usb.h"
+#include "usb_device.h"
+
+#include "usb_device_cdc_acm.h"
+#include "usb_device_ch9.h"
+
+#include "usb_device_descriptor.h"
+#include "virtual_com.h"
+#if (defined(FSL_FEATURE_SOC_SYSMPU_COUNT) && (FSL_FEATURE_SOC_SYSMPU_COUNT > 0U))
+#include "fsl_sysmpu.h"
+#endif /* FSL_FEATURE_SOC_SYSMPU_COUNT */
+#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0)
+#include "usb_phy.h"
+#endif
+
+/* Provided by users. */
+extern void USB_DeviceClockInit(void);
+extern void USB_DeviceIsrEnable(void);
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+
+/*******************************************************************************
+* Variables
+******************************************************************************/
+/* Data structure of virtual com device */
+usb_cdc_vcom_struct_t s_cdcVcom;
+
+/* Line codinig of cdc device */
+static uint8_t s_lineCoding[LINE_CODING_SIZE] = {
+ /* E.g. 0x00,0xC2,0x01,0x00 : 0x0001C200 is 115200 bits per second */
+ (LINE_CODING_DTERATE >> 0U) & 0x000000FFU,
+ (LINE_CODING_DTERATE >> 8U) & 0x000000FFU,
+ (LINE_CODING_DTERATE >> 16U) & 0x000000FFU,
+ (LINE_CODING_DTERATE >> 24U) & 0x000000FFU,
+ LINE_CODING_CHARFORMAT,
+ LINE_CODING_PARITYTYPE,
+ LINE_CODING_DATABITS};
+
+/* Abstract state of cdc device */
+static uint8_t s_abstractState[COMM_FEATURE_DATA_SIZE] = {(STATUS_ABSTRACT_STATE >> 0U) & 0x00FFU,
+ (STATUS_ABSTRACT_STATE >> 8U) & 0x00FFU};
+
+/* Country code of cdc device */
+static uint8_t s_countryCode[COMM_FEATURE_DATA_SIZE] = {(COUNTRY_SETTING >> 0U) & 0x00FFU,
+ (COUNTRY_SETTING >> 8U) & 0x00FFU};
+
+/* CDC ACM information */
+static usb_cdc_acm_info_t s_usbCdcAcmInfo = {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 0, 0, 0, 0};
+
+/* Data buffer for receiving and sending*/
+static uint8_t s_currRecvBuf[DATA_BUFF_SIZE];
+volatile static uint32_t s_recvSize = 0;
+volatile static uint32_t s_sendSize = 0;
+volatile static uint8_t s_sendComplete = 0;
+volatile static uint8_t s_currRecvIndex = 0;
+static uint32_t s_usbBulkMaxPacketSize = FS_CDC_VCOM_BULK_OUT_PACKET_SIZE;
+/*******************************************************************************
+* Prototypes
+******************************************************************************/
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+/*!
+ * @brief Interrupt in pipe callback function.
+ *
+ * This function serves as the callback function for interrupt in pipe.
+ *
+ * @param handle The USB device handle.
+ * @param message The endpoint callback message
+ * @param callbackParam The parameter of the callback.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceCdcAcmInterruptIn(usb_device_handle handle,
+ usb_device_endpoint_callback_message_struct_t *message,
+ void *callbackParam)
+{
+ usb_status_t error = kStatus_USB_Error;
+
+ return error;
+}
+
+/*!
+ * @brief Bulk in pipe callback function.
+ *
+ * This function serves as the callback function for bulk in pipe.
+ *
+ * @param handle The USB device handle.
+ * @param message The endpoint callback message
+ * @param callbackParam The parameter of the callback.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceCdcAcmBulkIn(usb_device_handle handle,
+ usb_device_endpoint_callback_message_struct_t *message,
+ void *callbackParam)
+{
+ usb_status_t error = kStatus_USB_Error;
+
+ if ((message->length != 0) && (!(message->length % s_usbBulkMaxPacketSize)))
+ {
+ /* If the last packet is the size of endpoint, then send also zero-ended packet,
+ ** meaning that we want to inform the host that we do not have any additional
+ ** data, so it can flush the output.
+ */
+ USB_DeviceSendRequest(handle, USB_CDC_VCOM_BULK_IN_ENDPOINT, NULL, 0);
+ }
+ else if ((1 == s_cdcVcom.attach) && (1 == s_cdcVcom.startTransactions))
+ {
+ if ((message->buffer != NULL) || ((message->buffer == NULL) && (message->length == 0)))
+ {
+ /* User: add your own code for send complete event */
+ s_sendComplete = 1;
+#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \
+ defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \
+ defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U)
+ USB0->INTEN &= ~USB_INTEN_SOFTOKEN_MASK;
+#endif
+ }
+ }
+ else if ((0 == s_sendComplete) && (1 == s_cdcVcom.attach) && (0 == s_cdcVcom.startTransactions))
+ {
+ s_sendComplete = 1;
+ }
+ else
+ {
+ }
+ return error;
+}
+
+/*!
+ * @brief Bulk out pipe callback function.
+ *
+ * This function serves as the callback function for bulk out pipe.
+ *
+ * @param handle The USB device handle.
+ * @param message The endpoint callback message
+ * @param callbackParam The parameter of the callback.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceCdcAcmBulkOut(usb_device_handle handle,
+ usb_device_endpoint_callback_message_struct_t *message,
+ void *callbackParam)
+{
+ usb_status_t error = kStatus_USB_Error;
+ if (USB_UNINITIALIZED_VAL_32 == message->length)
+ {
+ s_recvSize = 0xFFFFFFFFU;
+ }
+ else if ((1 == s_cdcVcom.attach) && (1 == s_cdcVcom.startTransactions))
+ {
+ s_recvSize = message->length;
+#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \
+ defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \
+ defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U)
+ USB0->INTEN |= USB_INTEN_SOFTOKEN_MASK;
+#endif
+ if (!s_recvSize)
+ {
+#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \
+ defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \
+ defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U)
+ USB0->INTEN &= ~USB_INTEN_SOFTOKEN_MASK;
+#endif
+ }
+ }
+ else
+ {
+ }
+ return error;
+}
+
+/*!
+ * @brief Get the setup packet buffer.
+ *
+ * This function provides the buffer for setup packet.
+ *
+ * @param handle The USB device handle.
+ * @param setupBuffer The pointer to the address of setup packet buffer.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceGetSetupBuffer(usb_device_handle handle, usb_setup_struct_t **setupBuffer)
+{
+ static uint32_t cdcVcomSetup[2];
+ if (NULL == setupBuffer)
+ {
+ return kStatus_USB_InvalidParameter;
+ }
+ *setupBuffer = (usb_setup_struct_t *)&cdcVcomSetup;
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief Get the setup packet data buffer.
+ *
+ * This function gets the data buffer for setup packet.
+ *
+ * @param handle The USB device handle.
+ * @param setup The pointer to the setup packet.
+ * @param length The pointer to the length of the data buffer.
+ * @param buffer The pointer to the address of setup packet data buffer.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceGetClassReceiveBuffer(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint32_t *length,
+ uint8_t **buffer)
+{
+ static uint8_t setupOut[8];
+ if ((NULL == buffer) || ((*length) > sizeof(setupOut)))
+ {
+ return kStatus_USB_InvalidRequest;
+ }
+ *buffer = setupOut;
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief Configure remote wakeup feature.
+ *
+ * This function configures the remote wakeup feature.
+ *
+ * @param handle The USB device handle.
+ * @param enable 1: enable, 0: disable.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceConfigureRemoteWakeup(usb_device_handle handle, uint8_t enable)
+{
+ return kStatus_USB_InvalidRequest;
+}
+
+/*!
+ * @brief CDC class specific callback function.
+ *
+ * This function handles the CDC class specific requests.
+ *
+ * @param handle The USB device handle.
+ * @param setup The pointer to the setup packet.
+ * @param length The pointer to the length of the data buffer.
+ * @param buffer The pointer to the address of setup packet data buffer.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceProcessClassRequest(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ uint32_t *length,
+ uint8_t **buffer)
+{
+ usb_status_t error = kStatus_USB_InvalidRequest;
+
+ usb_cdc_acm_info_t *acmInfo = &s_usbCdcAcmInfo;
+ uint32_t len;
+ uint16_t *uartBitmap;
+ if (setup->wIndex != USB_CDC_VCOM_COMM_INTERFACE_INDEX)
+ {
+ return error;
+ }
+
+ switch (setup->bRequest)
+ {
+ case USB_DEVICE_CDC_REQUEST_SEND_ENCAPSULATED_COMMAND:
+ break;
+ case USB_DEVICE_CDC_REQUEST_GET_ENCAPSULATED_RESPONSE:
+ break;
+ case USB_DEVICE_CDC_REQUEST_SET_COMM_FEATURE:
+ if (USB_DEVICE_CDC_FEATURE_ABSTRACT_STATE == setup->wValue)
+ {
+ *buffer = s_abstractState;
+ }
+ else if (USB_DEVICE_CDC_FEATURE_COUNTRY_SETTING == setup->wValue)
+ {
+ *buffer = s_countryCode;
+ }
+ else
+ {
+ }
+ error = kStatus_USB_Success;
+ break;
+ case USB_DEVICE_CDC_REQUEST_GET_COMM_FEATURE:
+ if (USB_DEVICE_CDC_FEATURE_ABSTRACT_STATE == setup->wValue)
+ {
+ *buffer = s_abstractState;
+ *length = COMM_FEATURE_DATA_SIZE;
+ }
+ else if (USB_DEVICE_CDC_FEATURE_COUNTRY_SETTING == setup->wValue)
+ {
+ *buffer = s_countryCode;
+ *length = COMM_FEATURE_DATA_SIZE;
+ }
+ else
+ {
+ }
+ error = kStatus_USB_Success;
+ break;
+ case USB_DEVICE_CDC_REQUEST_CLEAR_COMM_FEATURE:
+ break;
+ case USB_DEVICE_CDC_REQUEST_GET_LINE_CODING:
+ *buffer = s_lineCoding;
+ *length = LINE_CODING_SIZE;
+ error = kStatus_USB_Success;
+ break;
+ case USB_DEVICE_CDC_REQUEST_SET_LINE_CODING:
+ *buffer = s_lineCoding;
+ error = kStatus_USB_Success;
+ break;
+ case USB_DEVICE_CDC_REQUEST_SET_CONTROL_LINE_STATE:
+ {
+ acmInfo->dteStatus = setup->wValue;
+ /* activate/deactivate Tx carrier */
+ if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_CARRIER_ACTIVATION)
+ {
+ acmInfo->uartState |= USB_DEVICE_CDC_UART_STATE_TX_CARRIER;
+ }
+ else
+ {
+ acmInfo->uartState &= (uint16_t)~USB_DEVICE_CDC_UART_STATE_TX_CARRIER;
+ }
+
+ /* activate carrier and DTE */
+ if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE)
+ {
+ acmInfo->uartState |= USB_DEVICE_CDC_UART_STATE_RX_CARRIER;
+ }
+ else
+ {
+ acmInfo->uartState &= (uint16_t)~USB_DEVICE_CDC_UART_STATE_RX_CARRIER;
+ }
+
+ /* Indicates to DCE if DTE is present or not */
+ acmInfo->dtePresent = (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE) ? true : false;
+
+ /* Initialize the serial state buffer */
+ acmInfo->serialStateBuf[0] = NOTIF_REQUEST_TYPE; /* bmRequestType */
+ acmInfo->serialStateBuf[1] = USB_DEVICE_CDC_REQUEST_SERIAL_STATE_NOTIF; /* bNotification */
+ acmInfo->serialStateBuf[2] = 0x00; /* wValue */
+ acmInfo->serialStateBuf[3] = 0x00;
+ acmInfo->serialStateBuf[4] = 0x00; /* wIndex */
+ acmInfo->serialStateBuf[5] = 0x00;
+ acmInfo->serialStateBuf[6] = UART_BITMAP_SIZE; /* wLength */
+ acmInfo->serialStateBuf[7] = 0x00;
+ /* Notifiy to host the line state */
+ acmInfo->serialStateBuf[4] = setup->wIndex;
+ /* Lower byte of UART BITMAP */
+ uartBitmap = (uint16_t *)&acmInfo->serialStateBuf[NOTIF_PACKET_SIZE + UART_BITMAP_SIZE - 2];
+ *uartBitmap = acmInfo->uartState;
+ len = (uint32_t)(NOTIF_PACKET_SIZE + UART_BITMAP_SIZE);
+ error = USB_DeviceSendRequest(handle, USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT, acmInfo->serialStateBuf, len);
+
+ /* Update status */
+ if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_CARRIER_ACTIVATION)
+ {
+ /* To do: CARRIER_ACTIVATED */
+ }
+ else
+ {
+ /* To do: CARRIER_DEACTIVATED */
+ }
+ if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE)
+ {
+ /* DTE_ACTIVATED */
+ if (1 == s_cdcVcom.attach)
+ {
+ s_cdcVcom.startTransactions = 1;
+#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \
+ defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \
+ defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U)
+ USB0->INTEN &= ~USB_INTEN_SOFTOKEN_MASK;
+#endif
+ }
+ }
+ else
+ {
+ /* DTE_DEACTIVATED */
+ if (1 == s_cdcVcom.attach)
+ {
+ s_cdcVcom.startTransactions = 0;
+ }
+ }
+ }
+ break;
+ case USB_DEVICE_CDC_REQUEST_SEND_BREAK:
+ break;
+ default:
+ break;
+ }
+
+ return error;
+}
+
+/*!
+ * @brief USB device callback function.
+ *
+ * This function handles the usb device specific requests.
+ *
+ * @param handle The USB device handle.
+ * @param event The USB device event type.
+ * @param param The parameter of the device specific request.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceCallback(usb_device_handle handle, uint32_t event, void *param)
+{
+ usb_status_t error = kStatus_USB_Error;
+ uint8_t *temp8 = (uint8_t *)param;
+
+ switch (event)
+ {
+ case kUSB_DeviceEventBusReset:
+ {
+ USB_DeviceControlPipeInit(s_cdcVcom.deviceHandle);
+ s_cdcVcom.attach = 0;
+#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0)) || \
+ (defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+ if (kStatus_USB_Success ==
+ USB_DeviceGetStatus(s_cdcVcom.deviceHandle, kUSB_DeviceStatusSpeed, &s_cdcVcom.speed))
+ {
+ USB_DeviceSetSpeed(handle, s_cdcVcom.speed);
+ }
+#endif
+ }
+ break;
+ case kUSB_DeviceEventSetConfiguration:
+ if (param)
+ {
+ s_cdcVcom.attach = 1;
+ s_cdcVcom.currentConfiguration = *temp8;
+ if (USB_CDC_VCOM_CONFIGURE_INDEX == (*temp8))
+ {
+ usb_device_endpoint_init_struct_t epInitStruct;
+ usb_device_endpoint_callback_struct_t endpointCallback;
+
+ /* Initiailize endpoint for interrupt pipe */
+ endpointCallback.callbackFn = USB_DeviceCdcAcmInterruptIn;
+ endpointCallback.callbackParam = handle;
+
+ epInitStruct.zlt = 0;
+ epInitStruct.transferType = USB_ENDPOINT_INTERRUPT;
+ epInitStruct.endpointAddress = USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT |
+ (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT);
+ if (USB_SPEED_HIGH == s_cdcVcom.speed)
+ {
+ epInitStruct.maxPacketSize = HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE;
+ }
+ else
+ {
+ epInitStruct.maxPacketSize = FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE;
+ }
+
+ USB_DeviceInitEndpoint(s_cdcVcom.deviceHandle, &epInitStruct, &endpointCallback);
+
+ /* Initiailize endpoints for bulk pipe */
+ endpointCallback.callbackFn = USB_DeviceCdcAcmBulkIn;
+ endpointCallback.callbackParam = handle;
+
+ epInitStruct.zlt = 0;
+ epInitStruct.transferType = USB_ENDPOINT_BULK;
+ epInitStruct.endpointAddress =
+ USB_CDC_VCOM_BULK_IN_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT);
+ if (USB_SPEED_HIGH == s_cdcVcom.speed)
+ {
+ epInitStruct.maxPacketSize = HS_CDC_VCOM_BULK_IN_PACKET_SIZE;
+ }
+ else
+ {
+ epInitStruct.maxPacketSize = FS_CDC_VCOM_BULK_IN_PACKET_SIZE;
+ }
+
+ USB_DeviceInitEndpoint(s_cdcVcom.deviceHandle, &epInitStruct, &endpointCallback);
+
+ endpointCallback.callbackFn = USB_DeviceCdcAcmBulkOut;
+ endpointCallback.callbackParam = handle;
+
+ epInitStruct.zlt = 0;
+ epInitStruct.transferType = USB_ENDPOINT_BULK;
+ epInitStruct.endpointAddress =
+ USB_CDC_VCOM_BULK_OUT_ENDPOINT | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT);
+ if (USB_SPEED_HIGH == s_cdcVcom.speed)
+ {
+ epInitStruct.maxPacketSize = HS_CDC_VCOM_BULK_OUT_PACKET_SIZE;
+ }
+ else
+ {
+ epInitStruct.maxPacketSize = FS_CDC_VCOM_BULK_OUT_PACKET_SIZE;
+ }
+
+ USB_DeviceInitEndpoint(s_cdcVcom.deviceHandle, &epInitStruct, &endpointCallback);
+
+ if (USB_SPEED_HIGH == s_cdcVcom.speed)
+ {
+ s_usbBulkMaxPacketSize = HS_CDC_VCOM_BULK_OUT_PACKET_SIZE;
+ }
+ else
+ {
+ s_usbBulkMaxPacketSize = FS_CDC_VCOM_BULK_OUT_PACKET_SIZE;
+ }
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ return error;
+}
+
+/*!
+ * @brief USB configure endpoint function.
+ *
+ * This function configure endpoint status.
+ *
+ * @param handle The USB device handle.
+ * @param ep Endpoint address.
+ * @param status A flag to indicate whether to stall the endpoint. 1: stall, 0: unstall.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceConfigureEndpointStatus(usb_device_handle handle, uint8_t ep, uint8_t status)
+{
+ if (status)
+ {
+ return USB_DeviceStallEndpoint(handle, ep);
+ }
+ else
+ {
+ return USB_DeviceUnstallEndpoint(handle, ep);
+ }
+}
+
+/* See virtual_com.h for documentation of this function. */
+void USB_VcomWriteBlocking(usb_device_handle baseAddr, const uint8_t *buf, size_t count)
+{
+ while ((s_cdcVcom.attach != 1) || (s_cdcVcom.startTransactions != 1))
+ {
+ __NOP();
+ };
+ USB_DeviceSendRequest((usb_device_handle)baseAddr, USB_CDC_VCOM_BULK_IN_ENDPOINT, (uint8_t *)buf, count);
+ while (!s_sendComplete)
+ {
+ __NOP();
+ };
+ s_sendComplete = 0;
+}
+
+/* See virtual_com.h for documentation of this function. */
+status_t USB_VcomReadBlocking(usb_device_handle baseAddr, uint8_t *buf, size_t count)
+{
+ status_t error = kStatus_Success;
+ size_t bufIndex = 0U, bytesToReceive = 0U;
+ assert(count != 0U);
+
+ /* Waiting for the USB ready. */
+ while ((s_cdcVcom.attach != 1) || (s_cdcVcom.startTransactions != 1))
+ {
+ __NOP();
+ };
+
+ do
+ {
+ /* If no receive request. */
+ if (s_recvSize <= 0)
+ {
+ if (kStatus_USB_Success !=
+ USB_DeviceRecvRequest(baseAddr, USB_CDC_VCOM_BULK_OUT_ENDPOINT, s_currRecvBuf, s_usbBulkMaxPacketSize))
+ {
+ return kStatus_Fail;
+ }
+ s_currRecvIndex = 0;
+ }
+ /* Waiting for data received by virtual com. */
+ while (s_recvSize <= 0)
+ {
+ __NOP();
+ };
+
+ /* When receive request is error. */
+ if (0xFFFFFFFFU == s_recvSize)
+ {
+ /* Waiting for the USB ready and transfer started. */
+ while ((s_cdcVcom.attach != 1) || (s_cdcVcom.startTransactions != 1))
+ {
+ __NOP();
+ };
+ s_recvSize = 0;
+ }
+ else
+ {
+ bytesToReceive = MIN(count, s_recvSize);
+ memcpy((void *)&buf[bufIndex], s_currRecvBuf + s_currRecvIndex, bytesToReceive);
+ count -= bytesToReceive;
+ s_recvSize -= bytesToReceive;
+ bufIndex += bytesToReceive;
+ s_currRecvIndex += bytesToReceive;
+ }
+ } while (0U != count);
+ return error;
+}
+
+/* See virtual_com.h for documentation of this function. */
+usb_device_handle USB_VcomInit(void)
+{
+ usb_device_handle deviceHandle = NULL;
+
+ USB_DeviceClockInit();
+
+#if (defined(FSL_FEATURE_SOC_SYSMPU_COUNT) && (FSL_FEATURE_SOC_SYSMPU_COUNT > 0U))
+ SYSMPU_Enable(SYSMPU, 0);
+#endif /* FSL_FEATURE_SOC_SYSMPU_COUNT */
+
+ s_cdcVcom.speed = USB_SPEED_FULL;
+ s_cdcVcom.attach = 0;
+ s_cdcVcom.deviceHandle = NULL;
+
+ if (kStatus_USB_Success != USB_DeviceInit(CONTROLLER_ID, USB_DeviceCallback, &s_cdcVcom.deviceHandle))
+ {
+ deviceHandle = NULL;
+ }
+ else
+ {
+ deviceHandle = s_cdcVcom.deviceHandle;
+ USB_DeviceIsrEnable();
+ USB_DeviceRun(s_cdcVcom.deviceHandle);
+ }
+ return deviceHandle;
+}
+
+/* See virtual_com.h for documentation of this function. */
+void USB_VcomDeinit(usb_device_handle deviceHandle)
+{
+ USB_DeviceStop(deviceHandle);
+ USB_DeviceDeinit(deviceHandle);
+ s_cdcVcom.deviceHandle = NULL;
+#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0)
+ USB_EhciPhyDeinit(CONTROLLER_ID);
+#endif
+#if defined(USB_DEVICE_CONFIG_KHCI) && (USB_DEVICE_CONFIG_KHCI > 0)
+ CLOCK_DisableUsbfs0Clock();
+#endif
+#if defined(USB_DEVICE_CONFIG_LPCIP3511FS) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)
+ /* enable USB IP clock, user code. */
+ CLOCK_DisableClock(kCLOCK_Usbd0);
+#endif /* USB_DEVICE_CONFIG_LPCIP3511FS */
+
+#if defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)
+/* enable USB IP clock,user code. */
+#endif /* USB_DEVICE_CONFIG_LPCIP3511HS */
+}
--- /dev/null
+/*
+ * The Clear BSD License
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _USB_CDC_VCOM_H_
+#define _USB_CDC_VCOM_H_ 1
+
+#include "usb_device_descriptor.h"
+#include "fsl_common.h"
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0)
+#define CONTROLLER_ID kUSB_ControllerEhci0
+#define DATA_BUFF_SIZE HS_CDC_VCOM_BULK_OUT_PACKET_SIZE
+#endif /* USB_DEVICE_CONFIG_EHCI */
+
+#if defined(USB_DEVICE_CONFIG_KHCI) && (USB_DEVICE_CONFIG_KHCI > 0)
+#define CONTROLLER_ID kUSB_ControllerKhci0
+#define DATA_BUFF_SIZE FS_CDC_VCOM_BULK_OUT_PACKET_SIZE
+#endif /* USB_DEVICE_CONFIG_KHCI */
+
+#if defined(USB_DEVICE_CONFIG_LPCIP3511FS) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)
+#define CONTROLLER_ID kUSB_ControllerLpcIp3511Fs0
+#define DATA_BUFF_SIZE FS_CDC_VCOM_BULK_OUT_PACKET_SIZE
+#endif /* USB_DEVICE_CONFIG_LPCIP3511FS */
+
+#if defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)
+#define CONTROLLER_ID kUSB_ControllerLpcIp3511Hs0
+#define DATA_BUFF_SIZE HS_CDC_VCOM_BULK_OUT_PACKET_SIZE
+#endif /* USB_DEVICE_CONFIG_LPCIP3511HS */
+
+#if defined(USB_DEVICE_CONFIG_LPCIP3511FS) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)
+#define CONTROLLER_ID kUSB_ControllerLpcIp3511Fs0
+#define DATA_BUFF_SIZE FS_CDC_VCOM_BULK_OUT_PACKET_SIZE
+
+#endif
+
+#if defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)
+#define CONTROLLER_ID kUSB_ControllerLpcIp3511Hs0
+#define DATA_BUFF_SIZE HS_CDC_VCOM_BULK_OUT_PACKET_SIZE
+#endif
+
+#define USB_DEVICE_INTERRUPT_PRIORITY (3U)
+
+/* Currently configured line coding */
+#define LINE_CODING_SIZE (0x07)
+#define LINE_CODING_DTERATE (115200)
+#define LINE_CODING_CHARFORMAT (0x00)
+#define LINE_CODING_PARITYTYPE (0x00)
+#define LINE_CODING_DATABITS (0x08)
+
+/* Communications feature */
+#define COMM_FEATURE_DATA_SIZE (0x02)
+#define STATUS_ABSTRACT_STATE (0x0000)
+#define COUNTRY_SETTING (0x0000)
+
+/* Notification of serial state */
+#define NOTIF_PACKET_SIZE (0x08)
+#define UART_BITMAP_SIZE (0x02)
+#define NOTIF_REQUEST_TYPE (0xA1)
+
+/* Define the types for application */
+typedef struct _usb_cdc_vcom_struct
+{
+ usb_device_handle deviceHandle; /* USB device handle. */
+ volatile uint8_t attach; /* A flag to indicate whether a usb device is attached. 1: attached, 0: not attached */
+ uint8_t speed; /* Speed of USB device. USB_SPEED_FULL/USB_SPEED_LOW/USB_SPEED_HIGH. */
+ volatile uint8_t
+ startTransactions; /* A flag to indicate whether a CDC device is ready to transmit and receive data. */
+ uint8_t currentConfiguration; /* Current configuration value. */
+ uint8_t currentInterfaceAlternateSetting
+ [USB_CDC_VCOM_INTERFACE_COUNT]; /* Current alternate setting value for each interface. */
+} usb_cdc_vcom_struct_t;
+
+/* Define the infomation relates to abstract control model */
+typedef struct _usb_cdc_acm_info
+{
+ uint8_t serialStateBuf[NOTIF_PACKET_SIZE + UART_BITMAP_SIZE]; /* Serial state buffer of the CDC device to notify the
+ serial state to host. */
+ bool dtePresent; /* A flag to indicate whether DTE is present. */
+ uint16_t breakDuration; /* Length of time in milliseconds of the break signal */
+ uint8_t dteStatus; /* Status of data terminal equipment */
+ uint8_t currentInterface; /* Current interface index. */
+ uint16_t uartState; /* UART state of the CDC device. */
+} usb_cdc_acm_info_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Application initialization function.
+ *
+ * This function initializes the application.
+ *
+ * @return pointer to USB device handle.
+ */
+usb_device_handle USB_VcomInit(void);
+
+/*!
+ * @brief Application initialization function.
+ *
+ * This function initializes the application.
+ *
+ * @return pointer to USB device handle.
+ */
+void USB_VcomDeinit(usb_device_handle deviceHandle);
+
+/*!
+ * @brief USB recive data from host using a blocking method.
+ *
+ * This function recives data from host by usb cdc protocol
+ * @param baseAddr pointer to USB device handle.
+ * @param buf pointer to the data.
+ * @param count size of the transfer.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+status_t USB_VcomReadBlocking(usb_device_handle baseAddr, uint8_t *buf, size_t count);
+
+/*!
+ * @brief USB recive 'count' number of data from host using a blocking method.
+ *
+ * This function recives data from host by usb cdc protocol
+ * @param baseAddr pointer to USB device handle.
+ * @param buf pointer to the data.
+ * @param count size of the transfer.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+status_t USB_VcomReadPolling(usb_device_handle baseAddr, uint8_t *buf, size_t count);
+
+/*!
+ * @brief USB send data to host using a blocking method.
+ *
+ * This function sends data to host by usb cdc protocol
+ * @param baseAddr pointer to USB device handle.
+ * @param buf pointer to the data.
+ * @param count size of the transfer.
+ *
+ * @return None.
+ */
+void USB_VcomWriteBlocking(usb_device_handle baseAddr, const uint8_t *buf, size_t count);
+
+#endif /* _USB_CDC_VCOM_H_ */
projects / gps-watch.git / commitdiff