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4 * Copyright 2016-2017 NXP
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35 #ifndef _FSL_COMMON_H_
36 #define _FSL_COMMON_H_
44 #if defined(__ICCARM__)
48 #include "fsl_device_registers.h"
51 * @addtogroup ksdk_common
55 /*******************************************************************************
57 ******************************************************************************/
59 /*! @brief Construct a status code value from a group and code number. */
60 #define MAKE_STATUS(group, code) ((((group)*100) + (code)))
62 /*! @brief Construct the version number for drivers. */
63 #define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
65 /*! @name Driver version */
67 /*! @brief common driver version 2.0.0. */
68 #define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
71 /* Debug console type definition. */
72 #define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
73 #define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */
74 #define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */
75 #define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */
76 #define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */
77 #define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
78 #define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */
79 #define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */
80 #define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console base on LPC_USART. */
81 #define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console base on SWO. */
83 /*! @brief Status group numbers. */
86 kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
87 kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
88 kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
89 kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
90 kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
91 kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
92 kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
93 kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
94 kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
95 kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
96 kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
97 kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
98 kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
99 kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
100 kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
101 kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
102 kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
103 kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
104 kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
105 kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
106 kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
107 kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
108 kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
109 kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
110 kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
111 kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
112 kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
113 kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
114 kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */
115 kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
116 kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
117 kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
118 kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
119 kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
120 kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
121 kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
122 kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
123 kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
124 kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
125 kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
126 kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
127 kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
128 kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
129 kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
130 kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
131 kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
132 kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
133 kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
134 kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
135 kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
136 kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
137 kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
138 kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
139 kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
140 kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/
141 kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/
142 kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
143 kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
144 kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
145 kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */
146 kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
147 kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
148 kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
149 kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
150 kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
151 kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
152 kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
153 kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
156 /*! @brief Generic status return codes. */
159 kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
160 kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
161 kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
162 kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
163 kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
164 kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
165 kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
168 /*! @brief Type used for all status and error return values. */
169 typedef int32_t status_t;
172 * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
174 #if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
175 (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
176 #include "fsl_reset.h"
180 * Macro guard for whether to use default weak IRQ implementation in drivers
182 #ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
183 #define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
186 /*! @name Min/max macros */
189 #define MIN(a, b) ((a) < (b) ? (a) : (b))
193 #define MAX(a, b) ((a) > (b) ? (a) : (b))
197 /*! @brief Computes the number of elements in an array. */
198 #if !defined(ARRAY_SIZE)
199 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
202 /*! @name UINT16_MAX/UINT32_MAX value */
204 #if !defined(UINT16_MAX)
205 #define UINT16_MAX ((uint16_t)-1)
208 #if !defined(UINT32_MAX)
209 #define UINT32_MAX ((uint32_t)-1)
213 /*! @name Timer utilities */
215 /*! Macro to convert a microsecond period to raw count value */
216 #define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
217 /*! Macro to convert a raw count value to microsecond */
218 #define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
220 /*! Macro to convert a millisecond period to raw count value */
221 #define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
222 /*! Macro to convert a raw count value to millisecond */
223 #define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
226 /*! @name Alignment variable definition macros */
228 #if (defined(__ICCARM__))
230 * Workaround to disable MISRA C message suppress warnings for IAR compiler.
231 * http://supp.iar.com/Support/?note=24725
233 _Pragma("diag_suppress=Pm120")
234 #define SDK_PRAGMA(x) _Pragma(#x)
235 _Pragma("diag_error=Pm120")
236 /*! Macro to define a variable with alignbytes alignment */
237 #define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
238 /*! Macro to define a variable with L1 d-cache line size alignment */
239 #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
240 #define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
242 /*! Macro to define a variable with L2 cache line size alignment */
243 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
244 #define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
246 #elif defined(__ARMCC_VERSION)
247 /*! Macro to define a variable with alignbytes alignment */
248 #define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
249 /*! Macro to define a variable with L1 d-cache line size alignment */
250 #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
251 #define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
253 /*! Macro to define a variable with L2 cache line size alignment */
254 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
255 #define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
257 #elif defined(__GNUC__)
258 /*! Macro to define a variable with alignbytes alignment */
259 #define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
260 /*! Macro to define a variable with L1 d-cache line size alignment */
261 #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
262 #define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
264 /*! Macro to define a variable with L2 cache line size alignment */
265 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
266 #define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
269 #error Toolchain not supported
270 #define SDK_ALIGN(var, alignbytes) var
271 #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
272 #define SDK_L1DCACHE_ALIGN(var) var
274 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
275 #define SDK_L2CACHE_ALIGN(var) var
279 /*! Macro to change a value to a given size aligned value */
280 #define SDK_SIZEALIGN(var, alignbytes) \
281 ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
284 /*! @name Non-cacheable region definition macros */
285 /* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
286 * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
287 * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
288 * will be initialized to zero in system startup.
291 #if (defined(__ICCARM__))
292 #if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
293 #define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
294 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
295 #define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
296 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
298 #define AT_NONCACHEABLE_SECTION(var) var
299 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
300 #define AT_NONCACHEABLE_SECTION_INIT(var) var
301 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
303 #elif(defined(__ARMCC_VERSION))
304 #if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
305 #define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
306 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
307 __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
308 #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
309 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
310 __attribute__((section("NonCacheable.init"))) __align(alignbytes) var
312 #define AT_NONCACHEABLE_SECTION(var) var
313 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
314 #define AT_NONCACHEABLE_SECTION_INIT(var) var
315 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var
317 #elif(defined(__GNUC__))
318 /* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
319 * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
321 #if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
322 #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
323 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
324 __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
325 #define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
326 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
327 __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
329 #define AT_NONCACHEABLE_SECTION(var) var
330 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
331 #define AT_NONCACHEABLE_SECTION_INIT(var) var
332 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))
335 #error Toolchain not supported.
336 #define AT_NONCACHEABLE_SECTION(var) var
337 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
338 #define AT_NONCACHEABLE_SECTION_INIT(var) var
339 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
343 /*! @name Time sensitive region */
345 #if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
346 #if (defined(__ICCARM__))
347 #define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
348 #define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
349 #elif(defined(__ARMCC_VERSION))
350 #define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
351 #define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
352 #elif(defined(__GNUC__))
353 #define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
354 #define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
356 #error Toolchain not supported.
357 #endif /* defined(__ICCARM__) */
359 #if (defined(__ICCARM__))
360 #define AT_QUICKACCESS_SECTION_CODE(func) func
361 #define AT_QUICKACCESS_SECTION_DATA(func) func
362 #elif(defined(__ARMCC_VERSION))
363 #define AT_QUICKACCESS_SECTION_CODE(func) func
364 #define AT_QUICKACCESS_SECTION_DATA(func) func
365 #elif(defined(__GNUC__))
366 #define AT_QUICKACCESS_SECTION_CODE(func) func
367 #define AT_QUICKACCESS_SECTION_DATA(func) func
369 #error Toolchain not supported.
371 #endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
374 /*******************************************************************************
376 ******************************************************************************/
378 #if defined(__cplusplus)
383 static inline void __disable_irq(void)
385 asm volatile("cpsid i" ::: "memory");
389 * @brief Disable the global IRQ
391 * Disable the global interrupt and return the current primask register. User is required to provided the primask
392 * register for the EnableGlobalIRQ().
394 * @return Current primask value.
396 static inline uint32_t DisableGlobalIRQ(void)
398 #if defined(CPSR_I_Msk)
399 uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
405 uint32_t regPrimask = __get_PRIMASK();
414 * @brief Enaable the global IRQ
416 * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
417 * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
418 * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
420 * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
421 * DisableGlobalIRQ().
423 static inline void EnableGlobalIRQ(uint32_t primask)
425 #if defined(CPSR_I_Msk)
426 __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
428 __set_PRIMASK(primask);
432 #if defined(ENABLE_RAM_VECTOR_TABLE)
434 * @brief install IRQ handler
436 * @param irq IRQ number
437 * @param irqHandler IRQ handler address
438 * @return The old IRQ handler address
440 uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
441 #endif /* ENABLE_RAM_VECTOR_TABLE. */
443 #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
445 * @brief Enable specific interrupt for wake-up from deep-sleep mode.
447 * Enable the interrupt for wake-up from deep sleep mode.
448 * Some interrupts are typically used in sleep mode only and will not occur during
449 * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
450 * those clocks (significantly increasing power consumption in the reduced power mode),
451 * making these wake-ups possible.
453 * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
455 * @param interrupt The IRQ number.
457 void EnableDeepSleepIRQ(IRQn_Type interrupt);
460 * @brief Disable specific interrupt for wake-up from deep-sleep mode.
462 * Disable the interrupt for wake-up from deep sleep mode.
463 * Some interrupts are typically used in sleep mode only and will not occur during
464 * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
465 * those clocks (significantly increasing power consumption in the reduced power mode),
466 * making these wake-ups possible.
468 * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
470 * @param interrupt The IRQ number.
472 void DisableDeepSleepIRQ(IRQn_Type interrupt);
473 #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
476 * @brief Allocate memory with given alignment and aligned size.
478 * This is provided to support the dynamically allocated memory
479 * used in cache-able region.
480 * @param size The length required to malloc.
481 * @param alignbytes The alignment size.
482 * @retval The allocated memory.
484 void *SDK_Malloc(size_t size, size_t alignbytes);
487 * @brief Free memory.
489 * @param ptr The memory to be release.
491 void SDK_Free(void *ptr);
493 #if defined(__cplusplus)
499 #endif /* _FSL_COMMON_H_ */