2 * Copyright (c) 2019 Tilman Sauerbeck (tilman at code-monkey de)
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sublicense, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
19 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
20 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
21 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 type Reg8 = register::Register<u8>;
27 type Reg32 = register::Register<u32>;
29 const SIM_BASE: u32 = 0x40047000;
31 const SIM_SOPT1: u32 = SIM_BASE + 0x0000;
32 const SIM_SOPT2: u32 = SIM_BASE + 0x1004;
34 const SIM_SCGC4: u32 = SIM_BASE + 0x1034;
35 const SIM_CLKDIV1: u32 = SIM_BASE + 0x1044;
37 const SIM_SOPT1_USBREGEN: u32 = 1 << 31;
39 const SIM_SOPT2_PLLFLLSEL: u32 = 1 << 16;
40 const SIM_SOPT2_USBSRC: u32 = 1 << 18;
42 const SIM_SCGC4_USBOTG: u32 = 1 << 18;
44 const SIM_CLKDIV1_OUTDIV4_SHIFT: u32 = 16;
45 const SIM_CLKDIV1_OUTDIV1_SHIFT: u32 = 28;
47 const MCG_BASE: u32 = 0x40064000;
49 const MCG_C1: u32 = MCG_BASE + 0;
50 const MCG_C2: u32 = MCG_BASE + 1;
51 const MCG_C4: u32 = MCG_BASE + 3;
52 const MCG_C5: u32 = MCG_BASE + 4;
53 const MCG_C6: u32 = MCG_BASE + 5;
54 const MCG_S : u32 = MCG_BASE + 6;
56 const MCG_C1_FRDIV_SHIFT: u32 = 3;
57 const MCG_C1_CLKS_SHIFT: u32 = 6;
59 const MCG_C2_IRCS: u8 = 1 << 0;
60 const MCG_C2_EREFS0: u8 = 1 << 2;
61 const MCG_C2_RANGE0_SHIFT: u32 = 4;
63 const MCG_C4_DMX32: u8 = 1 << 7;
64 const MCG_C4_DRST_DRS_MASK: u8 = 3 << 5;
66 const MCG_C5_PLLSTEN0: u8 = 1 << 5;
67 const MCG_C5_PRDIV0_SHIFT: u32 = 0;
69 const MCG_C6_VDIV0_SHIFT: u32 = 0;
70 const MCG_C6_CME0: u8 = 1 << 5;
71 const MCG_C6_PLLS: u8 = 1 << 6;
73 const MCG_S_CLKST_SHIFT: u32 = 2;
74 const MCG_S_CLKST_MASK: u8 = 3 << MCG_S_CLKST_SHIFT;
75 const MCG_S_IREFST: u8 = 1 << 4;
76 const MCG_S_LOCK0: u8 = 1 << 6;
78 const OSC0_CR: u32 = 0x40065000;
80 const OSC_CR_ERCLKEN: u8 = 1 << 7;
82 fn configure_clkdiv() {
83 let mut clkdiv1 = Reg32::new(SIM_CLKDIV1);
85 clkdiv1.write((1 << SIM_CLKDIV1_OUTDIV4_SHIFT)
86 | (1 << SIM_CLKDIV1_OUTDIV1_SHIFT));
90 let mut c2 = Reg8::new(MCG_C2);
91 c2.write((2 << MCG_C2_RANGE0_SHIFT) | MCG_C2_EREFS0 | MCG_C2_IRCS);
93 let mut c1 = Reg8::new(MCG_C1);
94 c1.write((2 << MCG_C1_CLKS_SHIFT) | (3 << MCG_C1_FRDIV_SHIFT));
96 let mut c4 = Reg8::new(MCG_C4);
97 c4.modify(|v| v & !MCG_C4_DMX32 & !MCG_C4_DRST_DRS_MASK);
99 let mut c5 = Reg8::new(MCG_C5);
100 c5.write(MCG_C5_PLLSTEN0 | (11 << MCG_C5_PRDIV0_SHIFT));
102 let mut c6 = Reg8::new(MCG_C6);
103 c6.write(24 << MCG_C6_VDIV0_SHIFT);
105 let s = Reg8::new(MCG_S);
107 while (s.read() & MCG_S_IREFST) != 0 {
110 while (s.read() & MCG_S_CLKST_MASK) != (2 << MCG_S_CLKST_SHIFT) {
115 let mut c1 = Reg8::new(MCG_C1);
116 c1.write((2 << MCG_C1_CLKS_SHIFT) | (3 << MCG_C1_FRDIV_SHIFT));
118 let mut c2 = Reg8::new(MCG_C2);
119 c2.write((2 << MCG_C2_RANGE0_SHIFT) | MCG_C2_EREFS0 | MCG_C2_IRCS);
121 let mut c5 = Reg8::new(MCG_C5);
122 c5.write(MCG_C5_PLLSTEN0 | (11 << MCG_C5_PRDIV0_SHIFT));
124 let mut c6 = Reg8::new(MCG_C6);
125 c6.write(MCG_C6_PLLS | 24 << MCG_C6_VDIV0_SHIFT);
127 let s = Reg8::new(MCG_S);
129 while (s.read() & MCG_S_CLKST_MASK) != (2 << MCG_S_CLKST_SHIFT) {
132 while (s.read() & MCG_S_LOCK0) == 0 {
137 let mut c1 = Reg8::new(MCG_C1);
138 c1.write(3 << MCG_C1_FRDIV_SHIFT);
140 let mut c2 = Reg8::new(MCG_C2);
141 c2.write((2 << MCG_C2_RANGE0_SHIFT) | MCG_C2_EREFS0 | MCG_C2_IRCS);
143 let mut c5 = Reg8::new(MCG_C5);
144 c5.write(MCG_C5_PLLSTEN0 | (11 << MCG_C5_PRDIV0_SHIFT));
146 let mut c6 = Reg8::new(MCG_C6);
147 c6.write(MCG_C6_PLLS | 24 << MCG_C6_VDIV0_SHIFT);
149 let s = Reg8::new(MCG_S);
151 while (s.read() & MCG_S_CLKST_MASK) != (3 << MCG_S_CLKST_SHIFT) {
154 c6.modify(|v| v | MCG_C6_CME0);
157 pub unsafe fn configure() {
164 let mut sopt2 = Reg32::new(SIM_SOPT2);
167 v | SIM_SOPT2_PLLFLLSEL
171 pub unsafe fn reset() {
176 pub unsafe fn enable_osc0() {
177 Reg8::new(OSC0_CR).write(OSC_CR_ERCLKEN);
180 pub unsafe fn configure_usb() {
181 let mut scgc4 = Reg32::new(SIM_SCGC4);
182 scgc4.modify(|v| v & !SIM_SCGC4_USBOTG);
184 let mut sopt1 = Reg32::new(SIM_SOPT1);
185 sopt1.modify(|v| v | SIM_SOPT1_USBREGEN);
187 let mut sopt2 = Reg32::new(SIM_SOPT2);
188 sopt2.modify(|v| v | SIM_SOPT2_USBSRC);
190 scgc4.modify(|v| v | SIM_SCGC4_USBOTG);