2 ** ###################################################################
3 ** Version: rev. 1.11, 2015-05-27
7 ** Chip specific module features.
9 ** The Clear BSD License
10 ** Copyright 2016 Freescale Semiconductor, Inc.
11 ** Copyright 2016-2018 NXP
12 ** All rights reserved.
14 ** Redistribution and use in source and binary forms, with or without
15 ** modification, are permitted (subject to the limitations in the
16 ** disclaimer below) provided that the following conditions are met:
18 ** * Redistributions of source code must retain the above copyright
19 ** notice, this list of conditions and the following disclaimer.
21 ** * Redistributions in binary form must reproduce the above copyright
22 ** notice, this list of conditions and the following disclaimer in the
23 ** documentation and/or other materials provided with the distribution.
25 ** * Neither the name of the copyright holder nor the names of its
26 ** contributors may be used to endorse or promote products derived from
27 ** this software without specific prior written permission.
29 ** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
30 ** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
31 ** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
32 ** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
33 ** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
35 ** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
36 ** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
37 ** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
38 ** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
39 ** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
40 ** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
41 ** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 ** mail: support@nxp.com
47 ** - rev. 1.0 (2012-12-12)
49 ** - rev. 1.1 (2013-04-12)
50 ** SystemInit function fixed for clock configuration 1.
51 ** Name of the interrupt num. 31 updated to reflect proper function.
52 ** - rev. 1.2 (2014-01-30)
53 ** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum.
54 ** - rev. 1.3 (2014-05-27)
55 ** Updated to Kinetis SDK support standard.
56 ** MCG OSC clock select supported (MCG_C7[OSCSEL]).
57 ** - rev. 1.4 (2014-07-25)
58 ** System initialization updated:
59 ** - Prefix added to the system initialization parameterization constants to avoid name conflicts..
60 ** - VLLSx wake-up recovery added.
61 ** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes.
62 ** - rev. 1.5 (2014-08-28)
63 ** Update of system files - default clock configuration changed, fix of OSC initialization.
64 ** Update of startup files - possibility to override DefaultISR added.
65 ** - rev. 1.6 (2014-10-14)
66 ** Renamed interrupt vector LPTimer to LPTMR0
67 ** - rev. 1.7 (2015-01-21)
68 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
69 ** - rev. 1.8 (2015-02-18)
70 ** Renamed interrupt vector LLW to LLWU
71 ** - rev. 1.9 (2015-05-19)
72 ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
73 ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
74 ** Added features for PORT.
75 ** - rev. 1.10 (2015-05-25)
76 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
77 ** - rev. 1.11 (2015-05-27)
78 ** Several USB features added.
80 ** ###################################################################
83 #ifndef _MKL26Z4_FEATURES_H_
84 #define _MKL26Z4_FEATURES_H_
86 /* SOC module features */
88 /* @brief ADC16 availability on the SoC. */
89 #define FSL_FEATURE_SOC_ADC16_COUNT (1)
90 /* @brief CMP availability on the SoC. */
91 #define FSL_FEATURE_SOC_CMP_COUNT (1)
92 /* @brief DAC availability on the SoC. */
93 #define FSL_FEATURE_SOC_DAC_COUNT (1)
94 /* @brief DMA availability on the SoC. */
95 #define FSL_FEATURE_SOC_DMA_COUNT (1)
96 /* @brief DMAMUX availability on the SoC. */
97 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
98 /* @brief FGPIO availability on the SoC. */
99 #define FSL_FEATURE_SOC_FGPIO_COUNT (5)
100 /* @brief FTFA availability on the SoC. */
101 #define FSL_FEATURE_SOC_FTFA_COUNT (1)
102 /* @brief GPIO availability on the SoC. */
103 #define FSL_FEATURE_SOC_GPIO_COUNT (5)
104 /* @brief I2C availability on the SoC. */
105 #define FSL_FEATURE_SOC_I2C_COUNT (2)
106 /* @brief I2S availability on the SoC. */
107 #define FSL_FEATURE_SOC_I2S_COUNT (1)
108 /* @brief LLWU availability on the SoC. */
109 #define FSL_FEATURE_SOC_LLWU_COUNT (1)
110 /* @brief LPSCI availability on the SoC. */
111 #define FSL_FEATURE_SOC_LPSCI_COUNT (1)
112 /* @brief LPTMR availability on the SoC. */
113 #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
114 /* @brief MCG availability on the SoC. */
115 #define FSL_FEATURE_SOC_MCG_COUNT (1)
116 /* @brief MCM availability on the SoC. */
117 #define FSL_FEATURE_SOC_MCM_COUNT (1)
118 /* @brief MTB availability on the SoC. */
119 #define FSL_FEATURE_SOC_MTB_COUNT (1)
120 /* @brief MTBDWT availability on the SoC. */
121 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1)
122 /* @brief OSC availability on the SoC. */
123 #define FSL_FEATURE_SOC_OSC_COUNT (1)
124 /* @brief PIT availability on the SoC. */
125 #define FSL_FEATURE_SOC_PIT_COUNT (1)
126 /* @brief PMC availability on the SoC. */
127 #define FSL_FEATURE_SOC_PMC_COUNT (1)
128 /* @brief PORT availability on the SoC. */
129 #define FSL_FEATURE_SOC_PORT_COUNT (5)
130 /* @brief RCM availability on the SoC. */
131 #define FSL_FEATURE_SOC_RCM_COUNT (1)
132 /* @brief ROM availability on the SoC. */
133 #define FSL_FEATURE_SOC_ROM_COUNT (1)
134 /* @brief RTC availability on the SoC. */
135 #define FSL_FEATURE_SOC_RTC_COUNT (1)
136 /* @brief SIM availability on the SoC. */
137 #define FSL_FEATURE_SOC_SIM_COUNT (1)
138 /* @brief SMC availability on the SoC. */
139 #define FSL_FEATURE_SOC_SMC_COUNT (1)
140 /* @brief SPI availability on the SoC. */
141 #define FSL_FEATURE_SOC_SPI_COUNT (2)
142 /* @brief TPM availability on the SoC. */
143 #define FSL_FEATURE_SOC_TPM_COUNT (3)
144 /* @brief TSI availability on the SoC. */
145 #define FSL_FEATURE_SOC_TSI_COUNT (1)
146 /* @brief UART availability on the SoC. */
147 #define FSL_FEATURE_SOC_UART_COUNT (2)
148 /* @brief USB availability on the SoC. */
149 #define FSL_FEATURE_SOC_USB_COUNT (1)
151 /* ADC16 module features */
153 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
154 #define FSL_FEATURE_ADC16_HAS_PGA (0)
155 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
156 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
157 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
158 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
159 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
160 #define FSL_FEATURE_ADC16_HAS_DMA (1)
161 /* @brief Has differential mode (bitfield SC1x[DIFF]). */
162 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
163 /* @brief Has FIFO (bit SC4[AFDEP]). */
164 #define FSL_FEATURE_ADC16_HAS_FIFO (0)
165 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */
166 #define FSL_FEATURE_ADC16_FIFO_SIZE (0)
167 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
168 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
169 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
170 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
171 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
172 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
173 /* @brief Has HW averaging (bit SC3[AVGE]). */
174 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
175 /* @brief Has offset correction (register OFS). */
176 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
177 /* @brief Maximum ADC resolution. */
178 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
179 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
180 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
182 /* CMP module features */
184 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
185 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
186 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */
187 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
188 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
189 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
190 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
191 #define FSL_FEATURE_CMP_HAS_DMA (1)
192 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
193 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1)
194 /* @brief Has DAC Test function in CMP (register DACTEST). */
195 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
197 /* COP module features */
199 /* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */
200 #define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (0)
201 /* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */
202 #define FSL_FEATURE_COP_HAS_STOP_ENABLE (0)
203 /* @brief Has more clock sources like MCGIRC */
204 #define FSL_FEATURE_COP_HAS_MORE_CLKSRC (0)
205 /* @brief Has the timeout long and short mode bit (COPC[COPCLKSEL] and COPC[COPCLKS]) */
206 #define FSL_FEATURE_COP_HAS_LONGTIME_MODE (0)
208 /* DAC module features */
210 /* @brief Define the size of hardware buffer */
211 #define FSL_FEATURE_DAC_BUFFER_SIZE (2)
212 /* @brief Define whether the buffer supports watermark event detection or not. */
213 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (0)
214 /* @brief Define whether the buffer supports watermark selection detection or not. */
215 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (0)
216 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
217 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (0)
218 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
219 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (0)
220 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
221 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (0)
222 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
223 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (0)
224 /* @brief Define whether FIFO buffer mode is available or not. */
225 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
226 /* @brief Define whether swing buffer mode is available or not.. */
227 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0)
229 /* DMA module features */
231 /* @brief Number of DMA channels. */
232 #define FSL_FEATURE_DMA_MODULE_CHANNEL (4)
233 /* @brief Total number of DMA channels on all modules. */
234 #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMA_COUNT * 4)
236 /* DMAMUX module features */
238 /* @brief Number of DMA channels (related to number of register CHCFGn). */
239 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4)
240 /* @brief Total number of DMA channels on all modules. */
241 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4)
242 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
243 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
245 /* FLASH module features */
247 #if defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z128VLH4)
248 /* @brief Is of type FTFA. */
249 #define FSL_FEATURE_FLASH_IS_FTFA (1)
250 /* @brief Is of type FTFE. */
251 #define FSL_FEATURE_FLASH_IS_FTFE (0)
252 /* @brief Is of type FTFL. */
253 #define FSL_FEATURE_FLASH_IS_FTFL (0)
254 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
255 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
256 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
257 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
258 /* @brief Has EEPROM region protection (register FEPROT). */
259 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
260 /* @brief Has data flash region protection (register FDPROT). */
261 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
262 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
263 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
264 /* @brief Has flash cache control in FMC module. */
265 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
266 /* @brief Has flash cache control in MCM module. */
267 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
268 /* @brief Has flash cache control in MSCM module. */
269 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
270 /* @brief Has prefetch speculation control in flash, such as kv5x. */
271 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
272 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
273 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
274 /* @brief P-Flash start address. */
275 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
276 /* @brief P-Flash block count. */
277 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
278 /* @brief P-Flash block size. */
279 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072)
280 /* @brief P-Flash sector size. */
281 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
282 /* @brief P-Flash write unit size. */
283 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
284 /* @brief P-Flash data path width. */
285 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
286 /* @brief P-Flash block swap feature. */
287 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
288 /* @brief P-Flash protection region count. */
289 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
290 /* @brief Has FlexNVM memory. */
291 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
292 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
293 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
294 /* @brief FlexNVM block count. */
295 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
296 /* @brief FlexNVM block size. */
297 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
298 /* @brief FlexNVM sector size. */
299 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
300 /* @brief FlexNVM write unit size. */
301 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
302 /* @brief FlexNVM data path width. */
303 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
304 /* @brief Has FlexRAM memory. */
305 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
306 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
307 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
308 /* @brief FlexRAM size. */
309 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
310 /* @brief Has 0x00 Read 1s Block command. */
311 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
312 /* @brief Has 0x01 Read 1s Section command. */
313 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
314 /* @brief Has 0x02 Program Check command. */
315 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
316 /* @brief Has 0x03 Read Resource command. */
317 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
318 /* @brief Has 0x06 Program Longword command. */
319 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
320 /* @brief Has 0x07 Program Phrase command. */
321 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
322 /* @brief Has 0x08 Erase Flash Block command. */
323 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
324 /* @brief Has 0x09 Erase Flash Sector command. */
325 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
326 /* @brief Has 0x0B Program Section command. */
327 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
328 /* @brief Has 0x40 Read 1s All Blocks command. */
329 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
330 /* @brief Has 0x41 Read Once command. */
331 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
332 /* @brief Has 0x43 Program Once command. */
333 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
334 /* @brief Has 0x44 Erase All Blocks command. */
335 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
336 /* @brief Has 0x45 Verify Backdoor Access Key command. */
337 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
338 /* @brief Has 0x46 Swap Control command. */
339 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
340 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
341 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
342 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
343 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
344 /* @brief Has 0x4B Erase All Execute-only Segments command. */
345 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
346 /* @brief Has 0x80 Program Partition command. */
347 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
348 /* @brief Has 0x81 Set FlexRAM Function command. */
349 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
350 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
351 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
352 /* @brief P-Flash Erase sector command address alignment. */
353 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
354 /* @brief P-Flash Rrogram/Verify section command address alignment. */
355 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
356 /* @brief P-Flash Read resource command address alignment. */
357 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
358 /* @brief P-Flash Program check command address alignment. */
359 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
360 /* @brief P-Flash Program check command address alignment. */
361 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
362 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
363 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
364 /* @brief FlexNVM Erase sector command address alignment. */
365 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
366 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
367 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
368 /* @brief FlexNVM Read resource command address alignment. */
369 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
370 /* @brief FlexNVM Program check command address alignment. */
371 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
372 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
373 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
374 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
375 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
376 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
377 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
378 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
379 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
380 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
381 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
382 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
383 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
384 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
385 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
386 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
387 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
388 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
389 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
390 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
391 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
392 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
393 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
394 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
395 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
396 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
397 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
398 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
399 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
400 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
401 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
402 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
403 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
404 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
405 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
406 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
407 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
408 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
409 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
410 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
411 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
412 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
413 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
414 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
415 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
416 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
417 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
418 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
419 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
420 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
421 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
422 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
423 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
424 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
425 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
426 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
427 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
428 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
429 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
430 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
431 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
432 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
433 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
434 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
435 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
436 #elif defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z128VMC4)
437 /* @brief Is of type FTFA. */
438 #define FSL_FEATURE_FLASH_IS_FTFA (1)
439 /* @brief Is of type FTFE. */
440 #define FSL_FEATURE_FLASH_IS_FTFE (0)
441 /* @brief Is of type FTFL. */
442 #define FSL_FEATURE_FLASH_IS_FTFL (0)
443 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
444 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
445 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
446 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
447 /* @brief Has EEPROM region protection (register FEPROT). */
448 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
449 /* @brief Has data flash region protection (register FDPROT). */
450 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
451 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
452 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
453 /* @brief Has flash cache control in FMC module. */
454 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
455 /* @brief Has flash cache control in MCM module. */
456 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
457 /* @brief Has flash cache control in MSCM module. */
458 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
459 /* @brief Has prefetch speculation control in flash, such as kv5x. */
460 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
461 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
462 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
463 /* @brief P-Flash start address. */
464 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
465 /* @brief P-Flash block count. */
466 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
467 /* @brief P-Flash block size. */
468 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536)
469 /* @brief P-Flash sector size. */
470 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
471 /* @brief P-Flash write unit size. */
472 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
473 /* @brief P-Flash data path width. */
474 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
475 /* @brief P-Flash block swap feature. */
476 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
477 /* @brief P-Flash protection region count. */
478 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
479 /* @brief Has FlexNVM memory. */
480 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
481 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
482 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
483 /* @brief FlexNVM block count. */
484 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
485 /* @brief FlexNVM block size. */
486 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
487 /* @brief FlexNVM sector size. */
488 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
489 /* @brief FlexNVM write unit size. */
490 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
491 /* @brief FlexNVM data path width. */
492 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
493 /* @brief Has FlexRAM memory. */
494 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
495 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
496 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
497 /* @brief FlexRAM size. */
498 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
499 /* @brief Has 0x00 Read 1s Block command. */
500 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
501 /* @brief Has 0x01 Read 1s Section command. */
502 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
503 /* @brief Has 0x02 Program Check command. */
504 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
505 /* @brief Has 0x03 Read Resource command. */
506 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
507 /* @brief Has 0x06 Program Longword command. */
508 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
509 /* @brief Has 0x07 Program Phrase command. */
510 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
511 /* @brief Has 0x08 Erase Flash Block command. */
512 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
513 /* @brief Has 0x09 Erase Flash Sector command. */
514 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
515 /* @brief Has 0x0B Program Section command. */
516 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
517 /* @brief Has 0x40 Read 1s All Blocks command. */
518 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
519 /* @brief Has 0x41 Read Once command. */
520 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
521 /* @brief Has 0x43 Program Once command. */
522 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
523 /* @brief Has 0x44 Erase All Blocks command. */
524 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
525 /* @brief Has 0x45 Verify Backdoor Access Key command. */
526 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
527 /* @brief Has 0x46 Swap Control command. */
528 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
529 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
530 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
531 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
532 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
533 /* @brief Has 0x4B Erase All Execute-only Segments command. */
534 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
535 /* @brief Has 0x80 Program Partition command. */
536 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
537 /* @brief Has 0x81 Set FlexRAM Function command. */
538 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
539 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
540 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
541 /* @brief P-Flash Erase sector command address alignment. */
542 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
543 /* @brief P-Flash Rrogram/Verify section command address alignment. */
544 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
545 /* @brief P-Flash Read resource command address alignment. */
546 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
547 /* @brief P-Flash Program check command address alignment. */
548 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
549 /* @brief P-Flash Program check command address alignment. */
550 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
551 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
552 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
553 /* @brief FlexNVM Erase sector command address alignment. */
554 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
555 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
556 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
557 /* @brief FlexNVM Read resource command address alignment. */
558 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
559 /* @brief FlexNVM Program check command address alignment. */
560 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
561 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
562 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
563 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
564 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
565 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
566 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
567 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
568 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
569 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
570 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
571 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
572 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
573 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
574 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
575 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
576 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
577 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
578 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
579 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
580 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
581 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
582 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
583 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
584 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
585 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
586 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
587 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
588 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
589 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
590 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
591 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
592 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
593 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
594 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
595 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
596 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
597 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
598 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
599 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
600 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
601 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
602 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
603 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
604 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
605 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
606 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
607 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
608 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
609 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
610 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
611 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
612 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
613 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
614 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
615 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
616 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
617 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
618 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
619 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
620 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
621 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
622 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
623 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
624 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
625 #elif defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL26Z256VMP4)
626 /* @brief Is of type FTFA. */
627 #define FSL_FEATURE_FLASH_IS_FTFA (1)
628 /* @brief Is of type FTFE. */
629 #define FSL_FEATURE_FLASH_IS_FTFE (0)
630 /* @brief Is of type FTFL. */
631 #define FSL_FEATURE_FLASH_IS_FTFL (0)
632 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
633 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
634 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
635 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
636 /* @brief Has EEPROM region protection (register FEPROT). */
637 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
638 /* @brief Has data flash region protection (register FDPROT). */
639 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
640 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
641 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
642 /* @brief Has flash cache control in FMC module. */
643 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
644 /* @brief Has flash cache control in MCM module. */
645 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
646 /* @brief Has flash cache control in MSCM module. */
647 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
648 /* @brief Has prefetch speculation control in flash, such as kv5x. */
649 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
650 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
651 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
652 /* @brief P-Flash start address. */
653 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
654 /* @brief P-Flash block count. */
655 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
656 /* @brief P-Flash block size. */
657 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072)
658 /* @brief P-Flash sector size. */
659 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
660 /* @brief P-Flash write unit size. */
661 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
662 /* @brief P-Flash data path width. */
663 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
664 /* @brief P-Flash block swap feature. */
665 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
666 /* @brief P-Flash protection region count. */
667 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
668 /* @brief Has FlexNVM memory. */
669 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
670 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
671 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
672 /* @brief FlexNVM block count. */
673 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
674 /* @brief FlexNVM block size. */
675 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
676 /* @brief FlexNVM sector size. */
677 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
678 /* @brief FlexNVM write unit size. */
679 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
680 /* @brief FlexNVM data path width. */
681 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
682 /* @brief Has FlexRAM memory. */
683 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
684 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
685 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
686 /* @brief FlexRAM size. */
687 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
688 /* @brief Has 0x00 Read 1s Block command. */
689 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
690 /* @brief Has 0x01 Read 1s Section command. */
691 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
692 /* @brief Has 0x02 Program Check command. */
693 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
694 /* @brief Has 0x03 Read Resource command. */
695 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
696 /* @brief Has 0x06 Program Longword command. */
697 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
698 /* @brief Has 0x07 Program Phrase command. */
699 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
700 /* @brief Has 0x08 Erase Flash Block command. */
701 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
702 /* @brief Has 0x09 Erase Flash Sector command. */
703 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
704 /* @brief Has 0x0B Program Section command. */
705 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
706 /* @brief Has 0x40 Read 1s All Blocks command. */
707 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
708 /* @brief Has 0x41 Read Once command. */
709 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
710 /* @brief Has 0x43 Program Once command. */
711 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
712 /* @brief Has 0x44 Erase All Blocks command. */
713 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
714 /* @brief Has 0x45 Verify Backdoor Access Key command. */
715 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
716 /* @brief Has 0x46 Swap Control command. */
717 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
718 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
719 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
720 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
721 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
722 /* @brief Has 0x4B Erase All Execute-only Segments command. */
723 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
724 /* @brief Has 0x80 Program Partition command. */
725 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
726 /* @brief Has 0x81 Set FlexRAM Function command. */
727 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
728 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
729 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
730 /* @brief P-Flash Erase sector command address alignment. */
731 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
732 /* @brief P-Flash Rrogram/Verify section command address alignment. */
733 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
734 /* @brief P-Flash Read resource command address alignment. */
735 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
736 /* @brief P-Flash Program check command address alignment. */
737 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
738 /* @brief P-Flash Program check command address alignment. */
739 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
740 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
741 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
742 /* @brief FlexNVM Erase sector command address alignment. */
743 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
744 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
745 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
746 /* @brief FlexNVM Read resource command address alignment. */
747 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
748 /* @brief FlexNVM Program check command address alignment. */
749 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
750 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
751 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
752 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
753 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
754 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
755 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
756 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
757 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
758 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
759 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
760 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
761 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
762 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
763 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
764 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
765 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
766 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
767 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
768 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
769 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
770 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
771 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
772 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
773 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
774 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
775 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
776 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
777 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
778 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
779 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
780 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
781 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
782 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
783 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
784 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
785 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
786 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
787 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
788 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
789 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
790 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
791 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
792 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
793 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
794 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
795 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
796 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
797 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
798 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
799 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
800 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
801 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
802 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
803 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
804 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
805 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
806 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
807 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
808 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
809 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
810 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
811 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
812 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
813 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
814 #elif defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z32VLH4)
815 /* @brief Is of type FTFA. */
816 #define FSL_FEATURE_FLASH_IS_FTFA (1)
817 /* @brief Is of type FTFE. */
818 #define FSL_FEATURE_FLASH_IS_FTFE (0)
819 /* @brief Is of type FTFL. */
820 #define FSL_FEATURE_FLASH_IS_FTFL (0)
821 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
822 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
823 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
824 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
825 /* @brief Has EEPROM region protection (register FEPROT). */
826 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
827 /* @brief Has data flash region protection (register FDPROT). */
828 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
829 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
830 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
831 /* @brief Has flash cache control in FMC module. */
832 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
833 /* @brief Has flash cache control in MCM module. */
834 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
835 /* @brief Has flash cache control in MSCM module. */
836 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
837 /* @brief Has prefetch speculation control in flash, such as kv5x. */
838 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
839 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
840 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
841 /* @brief P-Flash start address. */
842 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
843 /* @brief P-Flash block count. */
844 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
845 /* @brief P-Flash block size. */
846 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (32768)
847 /* @brief P-Flash sector size. */
848 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
849 /* @brief P-Flash write unit size. */
850 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
851 /* @brief P-Flash data path width. */
852 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
853 /* @brief P-Flash block swap feature. */
854 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
855 /* @brief P-Flash protection region count. */
856 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
857 /* @brief Has FlexNVM memory. */
858 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
859 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
860 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
861 /* @brief FlexNVM block count. */
862 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
863 /* @brief FlexNVM block size. */
864 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
865 /* @brief FlexNVM sector size. */
866 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
867 /* @brief FlexNVM write unit size. */
868 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
869 /* @brief FlexNVM data path width. */
870 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
871 /* @brief Has FlexRAM memory. */
872 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
873 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
874 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
875 /* @brief FlexRAM size. */
876 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
877 /* @brief Has 0x00 Read 1s Block command. */
878 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
879 /* @brief Has 0x01 Read 1s Section command. */
880 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
881 /* @brief Has 0x02 Program Check command. */
882 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
883 /* @brief Has 0x03 Read Resource command. */
884 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
885 /* @brief Has 0x06 Program Longword command. */
886 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
887 /* @brief Has 0x07 Program Phrase command. */
888 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
889 /* @brief Has 0x08 Erase Flash Block command. */
890 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
891 /* @brief Has 0x09 Erase Flash Sector command. */
892 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
893 /* @brief Has 0x0B Program Section command. */
894 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
895 /* @brief Has 0x40 Read 1s All Blocks command. */
896 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
897 /* @brief Has 0x41 Read Once command. */
898 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
899 /* @brief Has 0x43 Program Once command. */
900 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
901 /* @brief Has 0x44 Erase All Blocks command. */
902 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
903 /* @brief Has 0x45 Verify Backdoor Access Key command. */
904 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
905 /* @brief Has 0x46 Swap Control command. */
906 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
907 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
908 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
909 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
910 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
911 /* @brief Has 0x4B Erase All Execute-only Segments command. */
912 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
913 /* @brief Has 0x80 Program Partition command. */
914 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
915 /* @brief Has 0x81 Set FlexRAM Function command. */
916 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
917 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
918 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
919 /* @brief P-Flash Erase sector command address alignment. */
920 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
921 /* @brief P-Flash Rrogram/Verify section command address alignment. */
922 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
923 /* @brief P-Flash Read resource command address alignment. */
924 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
925 /* @brief P-Flash Program check command address alignment. */
926 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
927 /* @brief P-Flash Program check command address alignment. */
928 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
929 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
930 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
931 /* @brief FlexNVM Erase sector command address alignment. */
932 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
933 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
934 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
935 /* @brief FlexNVM Read resource command address alignment. */
936 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
937 /* @brief FlexNVM Program check command address alignment. */
938 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
939 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
940 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
941 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
942 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
943 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
944 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
945 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
946 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
947 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
948 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
949 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
950 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
951 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
952 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
953 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
954 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
955 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
956 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
957 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
958 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
959 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
960 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
961 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
962 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
963 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
964 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
965 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
966 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
967 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
968 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
969 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
970 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
971 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
972 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
973 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
974 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
975 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
976 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
977 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
978 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
979 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
980 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
981 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
982 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
983 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
984 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
985 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
986 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
987 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
988 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
989 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
990 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
991 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
992 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
993 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
994 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
995 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
996 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
997 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
998 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
999 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1000 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
1001 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1002 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
1003 #elif defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z64VLH4)
1004 /* @brief Is of type FTFA. */
1005 #define FSL_FEATURE_FLASH_IS_FTFA (1)
1006 /* @brief Is of type FTFE. */
1007 #define FSL_FEATURE_FLASH_IS_FTFE (0)
1008 /* @brief Is of type FTFL. */
1009 #define FSL_FEATURE_FLASH_IS_FTFL (0)
1010 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
1011 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
1012 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
1013 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
1014 /* @brief Has EEPROM region protection (register FEPROT). */
1015 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
1016 /* @brief Has data flash region protection (register FDPROT). */
1017 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
1018 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
1019 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
1020 /* @brief Has flash cache control in FMC module. */
1021 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
1022 /* @brief Has flash cache control in MCM module. */
1023 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
1024 /* @brief Has flash cache control in MSCM module. */
1025 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
1026 /* @brief Has prefetch speculation control in flash, such as kv5x. */
1027 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
1028 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
1029 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
1030 /* @brief P-Flash start address. */
1031 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
1032 /* @brief P-Flash block count. */
1033 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
1034 /* @brief P-Flash block size. */
1035 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536)
1036 /* @brief P-Flash sector size. */
1037 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
1038 /* @brief P-Flash write unit size. */
1039 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
1040 /* @brief P-Flash data path width. */
1041 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
1042 /* @brief P-Flash block swap feature. */
1043 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
1044 /* @brief P-Flash protection region count. */
1045 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
1046 /* @brief Has FlexNVM memory. */
1047 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
1048 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
1049 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
1050 /* @brief FlexNVM block count. */
1051 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
1052 /* @brief FlexNVM block size. */
1053 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
1054 /* @brief FlexNVM sector size. */
1055 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
1056 /* @brief FlexNVM write unit size. */
1057 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
1058 /* @brief FlexNVM data path width. */
1059 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
1060 /* @brief Has FlexRAM memory. */
1061 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
1062 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
1063 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
1064 /* @brief FlexRAM size. */
1065 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
1066 /* @brief Has 0x00 Read 1s Block command. */
1067 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
1068 /* @brief Has 0x01 Read 1s Section command. */
1069 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
1070 /* @brief Has 0x02 Program Check command. */
1071 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
1072 /* @brief Has 0x03 Read Resource command. */
1073 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
1074 /* @brief Has 0x06 Program Longword command. */
1075 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
1076 /* @brief Has 0x07 Program Phrase command. */
1077 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
1078 /* @brief Has 0x08 Erase Flash Block command. */
1079 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
1080 /* @brief Has 0x09 Erase Flash Sector command. */
1081 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
1082 /* @brief Has 0x0B Program Section command. */
1083 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
1084 /* @brief Has 0x40 Read 1s All Blocks command. */
1085 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
1086 /* @brief Has 0x41 Read Once command. */
1087 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
1088 /* @brief Has 0x43 Program Once command. */
1089 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
1090 /* @brief Has 0x44 Erase All Blocks command. */
1091 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
1092 /* @brief Has 0x45 Verify Backdoor Access Key command. */
1093 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
1094 /* @brief Has 0x46 Swap Control command. */
1095 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
1096 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
1097 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
1098 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
1099 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
1100 /* @brief Has 0x4B Erase All Execute-only Segments command. */
1101 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
1102 /* @brief Has 0x80 Program Partition command. */
1103 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
1104 /* @brief Has 0x81 Set FlexRAM Function command. */
1105 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
1106 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
1107 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
1108 /* @brief P-Flash Erase sector command address alignment. */
1109 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
1110 /* @brief P-Flash Rrogram/Verify section command address alignment. */
1111 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
1112 /* @brief P-Flash Read resource command address alignment. */
1113 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
1114 /* @brief P-Flash Program check command address alignment. */
1115 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
1116 /* @brief P-Flash Program check command address alignment. */
1117 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
1118 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
1119 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
1120 /* @brief FlexNVM Erase sector command address alignment. */
1121 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
1122 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
1123 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
1124 /* @brief FlexNVM Read resource command address alignment. */
1125 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
1126 /* @brief FlexNVM Program check command address alignment. */
1127 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
1128 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1129 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
1130 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1131 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
1132 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1133 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
1134 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1135 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
1136 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1137 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
1138 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1139 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
1140 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1141 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
1142 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1143 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
1144 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1145 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
1146 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1147 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
1148 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1149 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
1150 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1151 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
1152 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1153 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
1154 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1155 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
1156 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1157 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
1158 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1159 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
1160 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1161 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
1162 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1163 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
1164 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1165 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
1166 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1167 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
1168 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1169 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
1170 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1171 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
1172 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1173 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
1174 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1175 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
1176 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1177 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
1178 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1179 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
1180 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1181 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
1182 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1183 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
1184 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1185 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
1186 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1187 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
1188 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1189 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
1190 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1191 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
1192 #endif /* defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z128VLH4) */
1194 /* GPIO module features */
1196 /* @brief Has fast (single cycle) access capability via a dedicated memory region. */
1197 #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1)
1198 /* @brief Has port input disable register (PIDR). */
1199 #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
1200 /* @brief Has dedicated interrupt vector. */
1201 #define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
1203 /* I2C module features */
1205 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
1206 #define FSL_FEATURE_I2C_HAS_SMBUS (1)
1207 /* @brief Maximum supported baud rate in kilobit per second. */
1208 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (100)
1209 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
1210 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (1)
1211 /* @brief Has DMA support (register bit C1[DMAEN]). */
1212 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
1213 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
1214 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
1215 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
1216 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
1217 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
1218 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
1219 /* @brief Maximum width of the glitch filter in number of bus clocks. */
1220 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
1221 /* @brief Has control of the drive capability of the I2C pins. */
1222 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
1223 /* @brief Has double buffering support (register S2). */
1224 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
1225 /* @brief Has double buffer enable. */
1226 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0)
1228 /* SAI module features */
1230 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
1231 #define FSL_FEATURE_SAI_FIFO_COUNT (1)
1232 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
1233 #define FSL_FEATURE_SAI_CHANNEL_COUNT (1)
1234 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
1235 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (2)
1236 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
1237 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0)
1238 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
1239 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0)
1240 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
1241 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0)
1242 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
1243 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0)
1244 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
1245 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
1246 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
1247 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
1248 /* @brief Ihe interrupt source number */
1249 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (1)
1250 /* @brief Has register of MCR. */
1251 #define FSL_FEATURE_SAI_HAS_MCR (1)
1252 /* @brief Has register of MDR */
1253 #define FSL_FEATURE_SAI_HAS_MDR (1)
1255 /* LLWU module features */
1257 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
1258 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
1259 /* @brief Has pins 8-15 connected to LLWU device. */
1260 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
1261 /* @brief Maximum number of internal modules connected to LLWU device. */
1262 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
1263 /* @brief Number of digital filters. */
1264 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
1265 /* @brief Has MF register. */
1266 #define FSL_FEATURE_LLWU_HAS_MF (0)
1267 /* @brief Has PF register. */
1268 #define FSL_FEATURE_LLWU_HAS_PF (0)
1269 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
1270 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
1271 /* @brief Has no internal module wakeup flag register. */
1272 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
1273 /* @brief Has external pin 0 connected to LLWU device. */
1274 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0)
1275 /* @brief Index of port of external pin. */
1276 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0)
1277 /* @brief Number of external pin port on specified port. */
1278 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0)
1279 /* @brief Has external pin 1 connected to LLWU device. */
1280 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0)
1281 /* @brief Index of port of external pin. */
1282 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0)
1283 /* @brief Number of external pin port on specified port. */
1284 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0)
1285 /* @brief Has external pin 2 connected to LLWU device. */
1286 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0)
1287 /* @brief Index of port of external pin. */
1288 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0)
1289 /* @brief Number of external pin port on specified port. */
1290 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0)
1291 /* @brief Has external pin 3 connected to LLWU device. */
1292 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (0)
1293 /* @brief Index of port of external pin. */
1294 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (0)
1295 /* @brief Number of external pin port on specified port. */
1296 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (0)
1297 /* @brief Has external pin 4 connected to LLWU device. */
1298 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0)
1299 /* @brief Index of port of external pin. */
1300 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0)
1301 /* @brief Number of external pin port on specified port. */
1302 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0)
1303 /* @brief Has external pin 5 connected to LLWU device. */
1304 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
1305 /* @brief Index of port of external pin. */
1306 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
1307 /* @brief Number of external pin port on specified port. */
1308 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
1309 /* @brief Has external pin 6 connected to LLWU device. */
1310 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
1311 /* @brief Index of port of external pin. */
1312 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
1313 /* @brief Number of external pin port on specified port. */
1314 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
1315 /* @brief Has external pin 7 connected to LLWU device. */
1316 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
1317 /* @brief Index of port of external pin. */
1318 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
1319 /* @brief Number of external pin port on specified port. */
1320 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
1321 /* @brief Has external pin 8 connected to LLWU device. */
1322 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
1323 /* @brief Index of port of external pin. */
1324 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
1325 /* @brief Number of external pin port on specified port. */
1326 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
1327 /* @brief Has external pin 9 connected to LLWU device. */
1328 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
1329 /* @brief Index of port of external pin. */
1330 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
1331 /* @brief Number of external pin port on specified port. */
1332 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
1333 /* @brief Has external pin 10 connected to LLWU device. */
1334 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
1335 /* @brief Index of port of external pin. */
1336 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
1337 /* @brief Number of external pin port on specified port. */
1338 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
1339 /* @brief Has external pin 11 connected to LLWU device. */
1340 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0)
1341 /* @brief Index of port of external pin. */
1342 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0)
1343 /* @brief Number of external pin port on specified port. */
1344 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0)
1345 /* @brief Has external pin 12 connected to LLWU device. */
1346 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0)
1347 /* @brief Index of port of external pin. */
1348 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0)
1349 /* @brief Number of external pin port on specified port. */
1350 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
1351 /* @brief Has external pin 13 connected to LLWU device. */
1352 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0)
1353 /* @brief Index of port of external pin. */
1354 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0)
1355 /* @brief Number of external pin port on specified port. */
1356 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0)
1357 /* @brief Has external pin 14 connected to LLWU device. */
1358 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
1359 /* @brief Index of port of external pin. */
1360 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
1361 /* @brief Number of external pin port on specified port. */
1362 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
1363 /* @brief Has external pin 15 connected to LLWU device. */
1364 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
1365 /* @brief Index of port of external pin. */
1366 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
1367 /* @brief Number of external pin port on specified port. */
1368 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
1369 /* @brief Has external pin 16 connected to LLWU device. */
1370 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
1371 /* @brief Index of port of external pin. */
1372 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
1373 /* @brief Number of external pin port on specified port. */
1374 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
1375 /* @brief Has external pin 17 connected to LLWU device. */
1376 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
1377 /* @brief Index of port of external pin. */
1378 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
1379 /* @brief Number of external pin port on specified port. */
1380 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
1381 /* @brief Has external pin 18 connected to LLWU device. */
1382 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
1383 /* @brief Index of port of external pin. */
1384 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
1385 /* @brief Number of external pin port on specified port. */
1386 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
1387 /* @brief Has external pin 19 connected to LLWU device. */
1388 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
1389 /* @brief Index of port of external pin. */
1390 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
1391 /* @brief Number of external pin port on specified port. */
1392 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
1393 /* @brief Has external pin 20 connected to LLWU device. */
1394 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
1395 /* @brief Index of port of external pin. */
1396 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
1397 /* @brief Number of external pin port on specified port. */
1398 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
1399 /* @brief Has external pin 21 connected to LLWU device. */
1400 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
1401 /* @brief Index of port of external pin. */
1402 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
1403 /* @brief Number of external pin port on specified port. */
1404 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
1405 /* @brief Has external pin 22 connected to LLWU device. */
1406 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
1407 /* @brief Index of port of external pin. */
1408 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
1409 /* @brief Number of external pin port on specified port. */
1410 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
1411 /* @brief Has external pin 23 connected to LLWU device. */
1412 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
1413 /* @brief Index of port of external pin. */
1414 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
1415 /* @brief Number of external pin port on specified port. */
1416 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
1417 /* @brief Has external pin 24 connected to LLWU device. */
1418 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
1419 /* @brief Index of port of external pin. */
1420 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
1421 /* @brief Number of external pin port on specified port. */
1422 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
1423 /* @brief Has external pin 25 connected to LLWU device. */
1424 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
1425 /* @brief Index of port of external pin. */
1426 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
1427 /* @brief Number of external pin port on specified port. */
1428 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
1429 /* @brief Has external pin 26 connected to LLWU device. */
1430 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
1431 /* @brief Index of port of external pin. */
1432 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
1433 /* @brief Number of external pin port on specified port. */
1434 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
1435 /* @brief Has external pin 27 connected to LLWU device. */
1436 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
1437 /* @brief Index of port of external pin. */
1438 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
1439 /* @brief Number of external pin port on specified port. */
1440 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
1441 /* @brief Has external pin 28 connected to LLWU device. */
1442 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
1443 /* @brief Index of port of external pin. */
1444 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
1445 /* @brief Number of external pin port on specified port. */
1446 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
1447 /* @brief Has external pin 29 connected to LLWU device. */
1448 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
1449 /* @brief Index of port of external pin. */
1450 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
1451 /* @brief Number of external pin port on specified port. */
1452 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
1453 /* @brief Has external pin 30 connected to LLWU device. */
1454 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
1455 /* @brief Index of port of external pin. */
1456 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
1457 /* @brief Number of external pin port on specified port. */
1458 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
1459 /* @brief Has external pin 31 connected to LLWU device. */
1460 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
1461 /* @brief Index of port of external pin. */
1462 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
1463 /* @brief Number of external pin port on specified port. */
1464 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
1465 /* @brief Has internal module 0 connected to LLWU device. */
1466 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
1467 /* @brief Has internal module 1 connected to LLWU device. */
1468 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
1469 /* @brief Has internal module 2 connected to LLWU device. */
1470 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0)
1471 /* @brief Has internal module 3 connected to LLWU device. */
1472 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
1473 /* @brief Has internal module 4 connected to LLWU device. */
1474 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
1475 /* @brief Has internal module 5 connected to LLWU device. */
1476 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
1477 /* @brief Has internal module 6 connected to LLWU device. */
1478 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
1479 /* @brief Has internal module 7 connected to LLWU device. */
1480 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
1481 /* @brief Has Version ID Register (LLWU_VERID). */
1482 #define FSL_FEATURE_LLWU_HAS_VERID (0)
1483 /* @brief Has Parameter Register (LLWU_PARAM). */
1484 #define FSL_FEATURE_LLWU_HAS_PARAM (0)
1485 /* @brief Width of registers of the LLWU. */
1486 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
1487 /* @brief Has DMA Enable register (LLWU_DE). */
1488 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
1490 /* LPTMR module features */
1492 /* @brief Has shared interrupt handler with another LPTMR module. */
1493 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
1494 /* @brief Whether LPTMR counter is 32 bits width. */
1495 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
1496 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
1497 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0)
1499 /* MCG module features */
1501 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
1502 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
1503 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
1504 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24)
1505 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
1506 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
1507 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */
1508 #define FSL_FEATURE_MCG_PLL_REF_MIN (2000000)
1509 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */
1510 #define FSL_FEATURE_MCG_PLL_REF_MAX (4000000)
1511 /* @brief The PLL clock is divided by 2 before VCO divider. */
1512 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
1513 /* @brief FRDIV supports 1280. */
1514 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
1515 /* @brief FRDIV supports 1536. */
1516 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
1517 /* @brief MCGFFCLK divider. */
1518 #define FSL_FEATURE_MCG_FFCLK_DIV (1)
1519 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
1520 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
1521 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
1522 #define FSL_FEATURE_MCG_HAS_RTC_32K (0)
1523 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
1524 #define FSL_FEATURE_MCG_HAS_PLL1 (0)
1525 /* @brief Has 48MHz internal oscillator. */
1526 #define FSL_FEATURE_MCG_HAS_IRC_48M (0)
1527 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
1528 #define FSL_FEATURE_MCG_HAS_OSC1 (0)
1529 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
1530 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
1531 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
1532 #define FSL_FEATURE_MCG_HAS_LOLRE (1)
1533 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
1534 #define FSL_FEATURE_MCG_USE_OSCSEL (1)
1535 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
1536 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
1538 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
1539 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */
1540 #define FSL_FEATURE_MCG_HAS_PLL (1)
1541 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
1542 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
1543 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
1544 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
1545 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
1546 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1)
1547 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
1548 #define FSL_FEATURE_MCG_HAS_FLL (1)
1549 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
1550 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
1551 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
1552 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
1553 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
1554 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
1555 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
1556 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
1557 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
1558 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
1559 /* @brief Has external clock monitor (register bit C6[CME]). */
1560 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
1561 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
1562 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
1563 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
1564 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
1565 /* @brief Has PEI mode or PBI mode. */
1566 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
1567 /* @brief Reset clock mode is BLPI. */
1568 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
1570 /* interrupt module features */
1572 /* @brief Lowest interrupt request number. */
1573 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
1574 /* @brief Highest interrupt request number. */
1575 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
1577 /* OSC module features */
1579 /* @brief Has OSC1 external oscillator. */
1580 #define FSL_FEATURE_OSC_HAS_OSC1 (0)
1581 /* @brief Has OSC0 external oscillator. */
1582 #define FSL_FEATURE_OSC_HAS_OSC0 (1)
1583 /* @brief Has OSC external oscillator (without index). */
1584 #define FSL_FEATURE_OSC_HAS_OSC (0)
1585 /* @brief Number of OSC external oscillators. */
1586 #define FSL_FEATURE_OSC_OSC_COUNT (1)
1587 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
1588 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
1590 /* PIT module features */
1592 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
1593 #define FSL_FEATURE_PIT_TIMER_COUNT (2)
1594 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
1595 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
1596 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
1597 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
1598 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
1599 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
1600 /* @brief Has timer enable control. */
1601 #define FSL_FEATURE_PIT_HAS_MDIS (1)
1603 /* PMC module features */
1605 /* @brief Has Bandgap Enable In VLPx Operation support. */
1606 #define FSL_FEATURE_PMC_HAS_BGEN (1)
1607 /* @brief Has Bandgap Buffer Enable. */
1608 #define FSL_FEATURE_PMC_HAS_BGBE (1)
1609 /* @brief Has Bandgap Buffer Drive Select. */
1610 #define FSL_FEATURE_PMC_HAS_BGBDS (0)
1611 /* @brief Has Low-Voltage Detect Voltage Select support. */
1612 #define FSL_FEATURE_PMC_HAS_LVDV (1)
1613 /* @brief Has Low-Voltage Warning Voltage Select support. */
1614 #define FSL_FEATURE_PMC_HAS_LVWV (1)
1615 /* @brief Has LPO. */
1616 #define FSL_FEATURE_PMC_HAS_LPO (0)
1617 /* @brief Has VLPx option PMC_REGSC[VLPO]. */
1618 #define FSL_FEATURE_PMC_HAS_VLPO (0)
1619 /* @brief Has acknowledge isolation support. */
1620 #define FSL_FEATURE_PMC_HAS_ACKISO (1)
1621 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
1622 #define FSL_FEATURE_PMC_HAS_REGFPM (0)
1623 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
1624 #define FSL_FEATURE_PMC_HAS_REGONS (1)
1625 /* @brief Has PMC_HVDSC1. */
1626 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
1627 /* @brief Has PMC_PARAM. */
1628 #define FSL_FEATURE_PMC_HAS_PARAM (0)
1629 /* @brief Has PMC_VERID. */
1630 #define FSL_FEATURE_PMC_HAS_VERID (0)
1632 /* PORT module features */
1634 /* @brief Has control lock (register bit PCR[LK]). */
1635 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
1636 /* @brief Has open drain control (register bit PCR[ODE]). */
1637 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
1638 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
1639 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
1640 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
1641 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
1642 /* @brief Has pull resistor selection available. */
1643 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
1644 /* @brief Has pull resistor enable (register bit PCR[PE]). */
1645 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
1646 /* @brief Has slew rate control (register bit PCR[SRE]). */
1647 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
1648 /* @brief Has passive filter (register bit field PCR[PFE]). */
1649 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
1650 /* @brief Has drive strength control (register bit PCR[DSE]). */
1651 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
1652 /* @brief Has separate drive strength register (HDRVE). */
1653 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
1654 /* @brief Has glitch filter (register IOFLT). */
1655 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
1656 /* @brief Defines width of PCR[MUX] field. */
1657 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
1658 /* @brief Has dedicated interrupt vector. */
1659 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
1660 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
1661 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
1662 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */
1663 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
1664 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
1665 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
1667 /* RCM module features */
1669 /* @brief Has Loss-of-Lock Reset support. */
1670 #define FSL_FEATURE_RCM_HAS_LOL (1)
1671 /* @brief Has Loss-of-Clock Reset support. */
1672 #define FSL_FEATURE_RCM_HAS_LOC (1)
1673 /* @brief Has JTAG generated Reset support. */
1674 #define FSL_FEATURE_RCM_HAS_JTAG (0)
1675 /* @brief Has EzPort generated Reset support. */
1676 #define FSL_FEATURE_RCM_HAS_EZPORT (0)
1677 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
1678 #define FSL_FEATURE_RCM_HAS_EZPMS (0)
1679 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
1680 #define FSL_FEATURE_RCM_HAS_BOOTROM (0)
1681 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
1682 #define FSL_FEATURE_RCM_HAS_SSRS (0)
1683 /* @brief Has Version ID Register (RCM_VERID). */
1684 #define FSL_FEATURE_RCM_HAS_VERID (0)
1685 /* @brief Has Parameter Register (RCM_PARAM). */
1686 #define FSL_FEATURE_RCM_HAS_PARAM (0)
1687 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
1688 #define FSL_FEATURE_RCM_HAS_SRIE (0)
1689 /* @brief Width of registers of the RCM. */
1690 #define FSL_FEATURE_RCM_REG_WIDTH (8)
1691 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
1692 #define FSL_FEATURE_RCM_HAS_CORE1 (0)
1693 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
1694 #define FSL_FEATURE_RCM_HAS_MDM_AP (1)
1695 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
1696 #define FSL_FEATURE_RCM_HAS_WAKEUP (1)
1698 /* RTC module features */
1700 #if defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z128VLH4) || \
1701 defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VFM4) || \
1702 defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z64VLH4)
1703 /* @brief Has wakeup pin. */
1704 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0)
1705 /* @brief Has wakeup pin selection (bit field CR[WPS]). */
1706 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
1707 /* @brief Has low power features (registers MER, MCLR and MCHR). */
1708 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
1709 /* @brief Has read/write access control (registers WAR and RAR). */
1710 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0)
1711 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
1712 #define FSL_FEATURE_RTC_HAS_SECURITY (0)
1713 /* @brief Has RTC_CLKIN available. */
1714 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1)
1715 /* @brief Has prescaler adjust for LPO. */
1716 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
1717 /* @brief Has Clock Pin Enable field. */
1718 #define FSL_FEATURE_RTC_HAS_CPE (0)
1719 /* @brief Has Timer Seconds Interrupt Configuration field. */
1720 #define FSL_FEATURE_RTC_HAS_TSIC (0)
1721 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
1722 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
1723 /* @brief Has Tamper Interrupt Register (register TIR). */
1724 #define FSL_FEATURE_RTC_HAS_TIR (0)
1725 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
1726 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0)
1727 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
1728 #define FSL_FEATURE_RTC_HAS_TIR_SIE (0)
1729 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
1730 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0)
1731 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
1732 #define FSL_FEATURE_RTC_HAS_SR_TIDF (0)
1733 /* @brief Has Tamper Detect Register (register TDR). */
1734 #define FSL_FEATURE_RTC_HAS_TDR (0)
1735 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
1736 #define FSL_FEATURE_RTC_HAS_TDR_TPF (0)
1737 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
1738 #define FSL_FEATURE_RTC_HAS_TDR_STF (0)
1739 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
1740 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0)
1741 /* @brief Has Tamper Time Seconds Register (register TTSR). */
1742 #define FSL_FEATURE_RTC_HAS_TTSR (0)
1743 /* @brief Has Pin Configuration Register (register PCR). */
1744 #define FSL_FEATURE_RTC_HAS_PCR (0)
1745 #elif defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLL4) || \
1746 defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL26Z256VMP4)
1747 /* @brief Has wakeup pin. */
1748 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
1749 /* @brief Has wakeup pin selection (bit field CR[WPS]). */
1750 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
1751 /* @brief Has low power features (registers MER, MCLR and MCHR). */
1752 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
1753 /* @brief Has read/write access control (registers WAR and RAR). */
1754 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0)
1755 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
1756 #define FSL_FEATURE_RTC_HAS_SECURITY (0)
1757 /* @brief Has RTC_CLKIN available. */
1758 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1)
1759 /* @brief Has prescaler adjust for LPO. */
1760 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
1761 /* @brief Has Clock Pin Enable field. */
1762 #define FSL_FEATURE_RTC_HAS_CPE (0)
1763 /* @brief Has Timer Seconds Interrupt Configuration field. */
1764 #define FSL_FEATURE_RTC_HAS_TSIC (0)
1765 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
1766 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
1767 /* @brief Has Tamper Interrupt Register (register TIR). */
1768 #define FSL_FEATURE_RTC_HAS_TIR (0)
1769 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
1770 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0)
1771 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
1772 #define FSL_FEATURE_RTC_HAS_TIR_SIE (0)
1773 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
1774 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0)
1775 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
1776 #define FSL_FEATURE_RTC_HAS_SR_TIDF (0)
1777 /* @brief Has Tamper Detect Register (register TDR). */
1778 #define FSL_FEATURE_RTC_HAS_TDR (0)
1779 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
1780 #define FSL_FEATURE_RTC_HAS_TDR_TPF (0)
1781 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
1782 #define FSL_FEATURE_RTC_HAS_TDR_STF (0)
1783 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
1784 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0)
1785 /* @brief Has Tamper Time Seconds Register (register TTSR). */
1786 #define FSL_FEATURE_RTC_HAS_TTSR (0)
1787 /* @brief Has Pin Configuration Register (register PCR). */
1788 #define FSL_FEATURE_RTC_HAS_PCR (0)
1789 #endif /* defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z128VLH4) || \
1790 defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VFM4) || \
1791 defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z64VLH4) */
1793 /* SIM module features */
1795 /* @brief Has USB FS divider. */
1796 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
1797 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
1798 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (1)
1799 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
1800 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
1801 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
1802 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
1803 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
1804 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
1805 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
1806 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
1807 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
1808 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
1809 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
1810 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
1811 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
1812 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
1813 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
1814 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
1815 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
1816 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
1817 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
1818 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
1819 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
1820 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
1821 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
1822 #define FSL_FEATURE_SIM_OPT_HAS_ODE (1)
1823 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
1824 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
1825 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
1826 #define FSL_FEATURE_SIM_OPT_UART_COUNT (3)
1827 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
1828 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (1)
1829 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
1830 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (1)
1831 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
1832 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (1)
1833 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
1834 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
1835 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
1836 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
1837 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
1838 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
1839 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
1840 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
1841 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
1842 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
1843 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
1844 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
1845 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1846 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
1847 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1848 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
1849 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1850 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
1851 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1852 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
1853 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1854 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1)
1855 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1856 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
1857 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1858 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
1859 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1860 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (1)
1861 /* @brief Has FTM module(s) configuration. */
1862 #define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
1863 /* @brief Number of FTM modules. */
1864 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
1865 /* @brief Number of FTM triggers with selectable source. */
1866 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
1867 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1868 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
1869 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1870 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
1871 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1872 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
1873 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1874 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
1875 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1876 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1877 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1878 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
1879 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1880 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
1881 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1882 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
1883 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
1884 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
1885 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
1886 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
1887 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
1888 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
1889 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
1890 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
1891 /* @brief Has TPM module(s) configuration. */
1892 #define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
1893 /* @brief The highest TPM module index. */
1894 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
1895 /* @brief Has TPM module with index 0. */
1896 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
1897 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
1898 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1)
1899 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
1900 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1)
1901 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1902 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
1903 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
1904 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1)
1905 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1906 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2)
1907 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
1908 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1)
1909 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
1910 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1)
1911 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
1912 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
1913 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
1914 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
1915 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
1916 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
1917 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
1918 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
1919 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
1920 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
1921 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
1922 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
1923 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
1924 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
1925 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
1926 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
1927 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1928 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
1929 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1930 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
1931 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1932 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
1933 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1934 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
1935 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1936 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
1937 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1938 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
1939 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1940 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
1941 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1942 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1)
1943 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
1944 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
1945 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
1946 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
1947 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
1948 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
1949 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
1950 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1)
1951 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
1952 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0)
1953 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
1954 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
1955 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
1956 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
1957 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
1958 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
1959 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
1960 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
1961 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
1962 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
1963 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
1964 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
1965 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
1966 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
1967 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
1968 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
1969 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
1970 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
1971 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
1972 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
1973 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
1974 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
1975 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
1976 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3)
1977 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
1978 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
1979 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
1980 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
1981 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
1982 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
1983 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
1984 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
1985 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
1986 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
1987 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
1988 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
1989 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
1990 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
1991 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
1992 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
1993 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
1994 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
1995 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
1996 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
1997 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
1998 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
1999 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
2000 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
2001 /* @brief Has device die ID (register bit field SDID[DIEID]). */
2002 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
2003 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
2004 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1)
2005 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
2006 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
2007 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
2008 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
2009 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
2010 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
2011 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
2012 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
2013 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
2014 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
2015 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
2016 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
2017 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
2018 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
2019 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
2020 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
2021 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
2022 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
2023 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
2024 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
2025 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
2026 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
2027 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
2028 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
2029 /* @brief Has miscellanious control register (register MCR). */
2030 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
2031 /* @brief Has COP watchdog (registers COPC and SRVCOP). */
2032 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1)
2033 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
2034 #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
2035 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
2036 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
2038 /* SMC module features */
2040 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
2041 #define FSL_FEATURE_SMC_HAS_PSTOPO (1)
2042 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
2043 #define FSL_FEATURE_SMC_HAS_LPOPO (0)
2044 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
2045 #define FSL_FEATURE_SMC_HAS_PORPO (1)
2046 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
2047 #define FSL_FEATURE_SMC_HAS_LPWUI (0)
2048 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
2049 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
2050 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
2051 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
2052 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
2053 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1)
2054 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
2055 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
2056 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
2057 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
2058 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
2059 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
2060 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
2061 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
2062 /* @brief Has stop submode. */
2063 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
2064 /* @brief Has stop submode 0(VLLS0). */
2065 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
2066 /* @brief Has stop submode 1(VLLS1). */
2067 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1)
2068 /* @brief Has stop submode 2(VLLS2). */
2069 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0)
2070 /* @brief Has SMC_PARAM. */
2071 #define FSL_FEATURE_SMC_HAS_PARAM (0)
2072 /* @brief Has SMC_VERID. */
2073 #define FSL_FEATURE_SMC_HAS_VERID (0)
2074 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
2075 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
2076 /* @brief Has tamper reset (register bit SRS[TAMPER]). */
2077 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
2078 /* @brief Has security violation reset (register bit SRS[SECVIO]). */
2079 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
2081 /* SPI module features */
2083 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
2084 #define FSL_FEATURE_SPI_HAS_FIFO (1)
2085 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). */
2086 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
2087 /* @brief Has separate DMA RX and TX requests. */
2088 #define FSL_FEATURE_SPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0)
2089 /* @brief Receive/transmit FIFO size in number of 16-bit communication items. */
2090 #define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
2091 ((x) == SPI0 ? (0) : \
2092 ((x) == SPI1 ? (4) : (-1)))
2093 /* @brief Maximum transfer data width in bits. */
2094 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
2095 /* @brief The data register name has postfix (L as low and H as high). */
2096 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1)
2097 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
2098 #define FSL_FEATURE_SPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
2099 /* @brief Has 16-bit data transfer support. */
2100 #define FSL_FEATURE_SPI_16BIT_TRANSFERS (1)
2102 /* SysTick module features */
2104 /* @brief Systick has external reference clock. */
2105 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1)
2106 /* @brief Systick external reference clock is core clock divided by this value. */
2107 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16)
2109 /* TPM module features */
2111 /* @brief Bus clock is the source clock for the module. */
2112 #define FSL_FEATURE_TPM_BUS_CLOCK (0)
2113 /* @brief Number of channels. */
2114 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
2115 ((x) == TPM0 ? (6) : \
2116 ((x) == TPM1 ? (2) : \
2117 ((x) == TPM2 ? (2) : (-1))))
2118 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
2119 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
2120 /* @brief Has TPM_PARAM. */
2121 #define FSL_FEATURE_TPM_HAS_PARAM (0)
2122 /* @brief Has TPM_VERID. */
2123 #define FSL_FEATURE_TPM_HAS_VERID (0)
2124 /* @brief Has TPM_GLOBAL. */
2125 #define FSL_FEATURE_TPM_HAS_GLOBAL (0)
2126 /* @brief Has TPM_TRIG. */
2127 #define FSL_FEATURE_TPM_HAS_TRIG (0)
2128 /* @brief Has counter pause on trigger. */
2129 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (0)
2130 /* @brief Has external trigger selection. */
2131 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (0)
2132 /* @brief Has TPM_COMBINE register. */
2133 #define FSL_FEATURE_TPM_HAS_COMBINE (0)
2134 /* @brief Whether COMBINE register has effect. */
2135 #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (0)
2136 /* @brief Has TPM_POL. */
2137 #define FSL_FEATURE_TPM_HAS_POL (0)
2138 /* @brief Has TPM_FILTER register. */
2139 #define FSL_FEATURE_TPM_HAS_FILTER (0)
2140 /* @brief Whether FILTER register has effect. */
2141 #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (0)
2142 /* @brief Has TPM_QDCTRL register. */
2143 #define FSL_FEATURE_TPM_HAS_QDCTRL (0)
2144 /* @brief Whether QDCTRL register has effect. */
2145 #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (0)
2147 /* TSI module features */
2149 /* @brief TSI module version. */
2150 #define FSL_FEATURE_TSI_VERSION (4)
2151 /* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */
2152 #define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0)
2153 /* @brief Number of TSI channels. */
2154 #define FSL_FEATURE_TSI_CHANNEL_COUNT (16)
2156 /* LPSCI module features */
2158 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
2159 #define FSL_FEATURE_LPSCI_HAS_IRQ_EXTENDED_FUNCTIONS (1)
2160 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
2161 #define FSL_FEATURE_LPSCI_HAS_LOW_POWER_UART_SUPPORT (1)
2162 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
2163 #define FSL_FEATURE_LPSCI_HAS_EXTENDED_DATA_REGISTER_FLAGS (0)
2164 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
2165 #define FSL_FEATURE_LPSCI_HAS_FIFO (0)
2166 /* @brief Hardware flow control (RTS, CTS) is supported. */
2167 #define FSL_FEATURE_LPSCI_HAS_MODEM_SUPPORT (0)
2168 /* @brief Infrared (modulation) is supported. */
2169 #define FSL_FEATURE_LPSCI_HAS_IR_SUPPORT (0)
2170 /* @brief 2 bits long stop bit is available. */
2171 #define FSL_FEATURE_LPSCI_HAS_STOP_BIT_CONFIG_SUPPORT (1)
2172 /* @brief If 10-bit mode is supported. */
2173 #define FSL_FEATURE_LPSCI_HAS_10BIT_DATA_SUPPORT (1)
2174 /* @brief Baud rate fine adjustment is available. */
2175 #define FSL_FEATURE_LPSCI_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
2176 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
2177 #define FSL_FEATURE_LPSCI_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
2178 /* @brief Baud rate oversampling is available. */
2179 #define FSL_FEATURE_LPSCI_HAS_RX_RESYNC_SUPPORT (1)
2180 /* @brief Baud rate oversampling is available. */
2181 #define FSL_FEATURE_LPSCI_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
2182 /* @brief Peripheral type. */
2183 #define FSL_FEATURE_LPSCI_IS_SCI (1)
2184 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
2185 #define FSL_FEATURE_LPSCI_FIFO_SIZE (0)
2186 /* @brief Maximal data width without parity bit. */
2187 #define FSL_FEATURE_LPSCI_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
2188 /* @brief Maximal data width with parity bit. */
2189 #define FSL_FEATURE_LPSCI_MAX_DATA_WIDTH_WITH_PARITY (9)
2190 /* @brief Supports two match addresses to filter incoming frames. */
2191 #define FSL_FEATURE_LPSCI_HAS_ADDRESS_MATCHING (1)
2192 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
2193 #define FSL_FEATURE_LPSCI_HAS_DMA_ENABLE (1)
2194 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
2195 #define FSL_FEATURE_LPSCI_HAS_DMA_SELECT (0)
2196 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
2197 #define FSL_FEATURE_LPSCI_HAS_BIT_ORDER_SELECT (1)
2198 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
2199 #define FSL_FEATURE_LPSCI_HAS_SMART_CARD_SUPPORT (0)
2200 /* @brief Has improved smart card (ISO7816 protocol) support. */
2201 #define FSL_FEATURE_LPSCI_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
2202 /* @brief Has local operation network (CEA709.1-B protocol) support. */
2203 #define FSL_FEATURE_LPSCI_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
2204 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
2205 #define FSL_FEATURE_LPSCI_HAS_32BIT_REGISTERS (0)
2206 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */
2207 #define FSL_FEATURE_LPSCI_HAS_LIN_BREAK_DETECT (1)
2208 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
2209 #define FSL_FEATURE_LPSCI_HAS_WAIT_MODE_OPERATION (0)
2210 /* @brief Has separate DMA RX and TX requests. */
2211 #define FSL_FEATURE_LPSCI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
2213 /* UART module features */
2215 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
2216 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
2217 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
2218 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
2219 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
2220 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0)
2221 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
2222 #define FSL_FEATURE_UART_HAS_FIFO (0)
2223 /* @brief Hardware flow control (RTS, CTS) is supported. */
2224 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0)
2225 /* @brief Infrared (modulation) is supported. */
2226 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0)
2227 /* @brief 2 bits long stop bit is available. */
2228 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
2229 /* @brief If 10-bit mode is supported. */
2230 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
2231 /* @brief Baud rate fine adjustment is available. */
2232 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
2233 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
2234 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
2235 /* @brief Baud rate oversampling is available. */
2236 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (1)
2237 /* @brief Baud rate oversampling is available. */
2238 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
2239 /* @brief Peripheral type. */
2240 #define FSL_FEATURE_UART_IS_SCI (1)
2241 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
2242 #define FSL_FEATURE_UART_FIFO_SIZE (0)
2243 /* @brief Maximal data width without parity bit. */
2244 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
2245 /* @brief Maximal data width with parity bit. */
2246 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (8)
2247 /* @brief Supports two match addresses to filter incoming frames. */
2248 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (0)
2249 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
2250 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
2251 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
2252 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
2253 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
2254 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (0)
2255 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
2256 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0)
2257 /* @brief Has improved smart card (ISO7816 protocol) support. */
2258 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
2259 /* @brief Has local operation network (CEA709.1-B protocol) support. */
2260 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
2261 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
2262 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
2263 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */
2264 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
2265 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
2266 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
2267 /* @brief Has separate DMA RX and TX requests. */
2268 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
2270 /* USB module features */
2272 /* @brief KHCI module instance count */
2273 #define FSL_FEATURE_USB_KHCI_COUNT (1)
2274 /* @brief HOST mode enabled */
2275 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
2276 /* @brief OTG mode enabled */
2277 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
2278 /* @brief Size of the USB dedicated RAM */
2279 #define FSL_FEATURE_USB_KHCI_USB_RAM (0)
2280 /* @brief Has KEEP_ALIVE_CTRL register */
2281 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
2282 /* @brief Has the Dynamic SOF threshold compare support */
2283 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
2284 /* @brief Has the VBUS detect support */
2285 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
2286 /* @brief Has the IRC48M module clock support */
2287 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (0)
2288 /* @brief Number of endpoints supported */
2289 #define FSL_FEATURE_USB_ENDPT_COUNT (16)
2290 /* @brief Has STALL_IL/OL_DIS registers */
2291 #define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (0)
2292 /* @brief Has STALL_IH/OH_DIS registers */
2293 #define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (0)
2295 #endif /* _MKL26Z4_FEATURES_H_ */