2 ** ###################################################################
3 ** Processors: MKL26Z128CAL4
20 ** Compilers: Keil ARM C/C++ Compiler
21 ** Freescale C/C++ for Embedded ARM
23 ** IAR ANSI C/C++ Compiler for ARM
24 ** MCUXpresso Compiler
26 ** Reference manuals: KL26P121M48SF4RM Rev. 3.2, October 2013
27 ** KL26P121M48SF4RM, Rev.2, Dec 2012
29 ** Version: rev. 1.8, 2015-07-29
33 ** CMSIS Peripheral Access Layer for MKL26Z4
35 ** The Clear BSD License
36 ** Copyright 1997-2016 Freescale Semiconductor, Inc.
37 ** Copyright 2016-2017 NXP
38 ** All rights reserved.
40 ** Redistribution and use in source and binary forms, with or without
41 ** modification, are permitted (subject to the limitations in the
42 ** disclaimer below) provided that the following conditions are met:
44 ** * Redistributions of source code must retain the above copyright
45 ** notice, this list of conditions and the following disclaimer.
47 ** * Redistributions in binary form must reproduce the above copyright
48 ** notice, this list of conditions and the following disclaimer in the
49 ** documentation and/or other materials provided with the distribution.
51 ** * Neither the name of the copyright holder nor the names of its
52 ** contributors may be used to endorse or promote products derived from
53 ** this software without specific prior written permission.
55 ** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
56 ** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
57 ** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
58 ** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
59 ** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
60 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
61 ** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
62 ** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
63 ** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
64 ** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
65 ** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
66 ** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
67 ** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
70 ** mail: support@nxp.com
73 ** - rev. 1.0 (2012-12-12)
75 ** - rev. 1.1 (2013-04-05)
76 ** Changed start of doxygen comment.
77 ** - rev. 1.2 (2013-04-12)
78 ** SystemInit function fixed for clock configuration 1.
79 ** Name of the interrupt num. 31 updated to reflect proper function.
80 ** - rev. 1.3 (2014-05-27)
81 ** Updated to Kinetis SDK support standard.
82 ** MCG OSC clock select supported (MCG_C7[OSCSEL]).
83 ** - rev. 1.4 (2014-07-25)
84 ** System initialization updated:
85 ** - Prefix added to the system initialization parameterization constants to avoid name conflicts..
86 ** - VLLSx wake-up recovery added.
87 ** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes.
88 ** - rev. 1.5 (2014-08-28)
89 ** Update of system files - default clock configuration changed, fix of OSC initialization.
90 ** Update of startup files - possibility to override DefaultISR added.
91 ** - rev. 1.6 (2014-10-14)
92 ** Renamed interrupt vector LPTimer to LPTMR0
93 ** - rev. 1.7 (2015-02-18)
94 ** Renamed interrupt vector LLW to LLWU
95 ** - rev. 1.8 (2015-07-29)
96 ** Correction of backward compatibility.
98 ** ###################################################################
105 * @brief CMSIS Peripheral Access Layer for MKL26Z4
107 * CMSIS Peripheral Access Layer for MKL26Z4
111 #define _MKL26Z4_H_ /**< Symbol preventing repeated inclusion */
115 /** Memory map major version (memory maps with equal major version number are
117 #define MCU_MEM_MAP_VERSION 0x0100U
118 /** Memory map minor version */
119 #define MCU_MEM_MAP_VERSION_MINOR 0x0008U
122 /* ----------------------------------------------------------------------------
123 -- Interrupt vector numbers
124 ---------------------------------------------------------------------------- */
127 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
131 /** Interrupt Number Definitions */
132 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
135 /* Auxiliary constants */
136 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
138 /* Core interrupts */
139 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
140 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
141 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
142 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
143 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
145 /* Device specific interrupts */
146 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete and error interrupt */
147 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete and error interrupt */
148 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete and error interrupt */
149 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete and error interrupt */
150 Reserved20_IRQn = 4, /**< Reserved interrupt */
151 FTFA_IRQn = 5, /**< FTFA command complete and read collision */
152 LVD_LVW_IRQn = 6, /**< Low-voltage detect, low-voltage warning */
153 LLWU_IRQn = 7, /**< Low Leakage Wakeup */
154 I2C0_IRQn = 8, /**< I2C0 interrupt */
155 I2C1_IRQn = 9, /**< I2C1 interrupt */
156 SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
157 SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */
158 UART0_IRQn = 12, /**< UART0 status and error */
159 UART1_IRQn = 13, /**< UART1 status and error */
160 UART2_IRQn = 14, /**< UART2 status and error */
161 ADC0_IRQn = 15, /**< ADC0 interrupt */
162 CMP0_IRQn = 16, /**< CMP0 interrupt */
163 TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
164 TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
165 TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
166 RTC_IRQn = 20, /**< RTC alarm interrupt */
167 RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
168 PIT_IRQn = 22, /**< PIT single interrupt vector for all channels */
169 I2S0_IRQn = 23, /**< I2S0 Single interrupt vector for all sources */
170 USB0_IRQn = 24, /**< USB0 OTG */
171 DAC0_IRQn = 25, /**< DAC0 interrupt */
172 TSI0_IRQn = 26, /**< TSI0 interrupt */
173 MCG_IRQn = 27, /**< MCG interrupt */
174 LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */
175 Reserved45_IRQn = 29, /**< Reserved interrupt */
176 PORTA_IRQn = 30, /**< PORTA pin detect */
177 PORTC_PORTD_IRQn = 31 /**< Single interrupt vector for PORTC and PORTD pin detect */
182 */ /* end of group Interrupt_vector_numbers */
185 /* ----------------------------------------------------------------------------
186 -- Cortex M0 Core Configuration
187 ---------------------------------------------------------------------------- */
190 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
194 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
195 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
196 #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */
197 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
198 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
201 uint32_t __get_PRIMASK (void)
205 asm volatile ("MRS %0, primask" : "=r" (result) :: "memory");
210 void __set_PRIMASK (uint32_t priMask)
212 asm volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
217 */ /* end of group Cortex_Core_Configuration */
220 /* ----------------------------------------------------------------------------
221 -- Mapping Information
222 ---------------------------------------------------------------------------- */
225 * @addtogroup Mapping_Information Mapping Information
229 /** Mapping Information */
231 * @addtogroup edma_request
235 /*******************************************************************************
237 ******************************************************************************/
240 * @brief Structure for the DMA hardware request
242 * Defines the structure for the DMA hardware request collections. The user can configure the
243 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
244 * of the hardware request varies according to the to SoC.
246 typedef enum _dma_request_source
248 kDmaRequestMux0Disable = 0|0x100U, /**< Disable */
249 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
250 kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 receive complete */
251 kDmaRequestMux0LPSCI0Rx = 2|0x100U, /**< UART0 receive complete */
252 kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 transmit complete */
253 kDmaRequestMux0LPSCI0Tx = 3|0x100U, /**< UART0 transmit complete */
254 kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 receive complete */
255 kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 transmit complete */
256 kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 receive complete */
257 kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 transmit complete */
258 kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */
259 kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */
260 kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */
261 kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */
262 kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */
263 kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */
264 kDmaRequestMux0I2S0Rx = 14|0x100U, /**< I2S0 receive complete */
265 kDmaRequestMux0I2S0Tx = 15|0x100U, /**< I2S0 transmit complete */
266 kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 receive complete */
267 kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 transmit complete */
268 kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 receive complete */
269 kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 transmit complete */
270 kDmaRequestMux0Reserved20 = 20|0x100U, /**< Reserved20 */
271 kDmaRequestMux0Reserved21 = 21|0x100U, /**< Reserved21 */
272 kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0 transmission complete */
273 kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1 transmission complete */
274 kDmaRequestMux0TPM0Channel0 = 24|0x100U, /**< TPM0 channel 0 event (CMP or CAP) */
275 kDmaRequestMux0TPM0Channel1 = 25|0x100U, /**< TPM0 channel 1 event (CMP or CAP) */
276 kDmaRequestMux0TPM0Channel2 = 26|0x100U, /**< TPM0 channel 2 event (CMP or CAP) */
277 kDmaRequestMux0TPM0Channel3 = 27|0x100U, /**< TPM0 channel 3 event (CMP or CAP) */
278 kDmaRequestMux0TPM0Channel4 = 28|0x100U, /**< TPM0 channel 4 event (CMP or CAP) */
279 kDmaRequestMux0TPM0Channel5 = 29|0x100U, /**< TPM0 channel 5 event (CMP or CAP) */
280 kDmaRequestMux0Reserved30 = 30|0x100U, /**< Reserved30 */
281 kDmaRequestMux0Reserved31 = 31|0x100U, /**< Reserved31 */
282 kDmaRequestMux0TPM1Channel0 = 32|0x100U, /**< TPM1 channel 0 event (CMP or CAP) */
283 kDmaRequestMux0TPM1Channel1 = 33|0x100U, /**< TPM1 channel 1 event (CMP or CAP) */
284 kDmaRequestMux0TPM2Channel0 = 34|0x100U, /**< TPM2 channel 0 event (CMP or CAP) */
285 kDmaRequestMux0TPM2Channel1 = 35|0x100U, /**< TPM2 channel 1 event (CMP or CAP) */
286 kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */
287 kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */
288 kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */
289 kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */
290 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0 conversion complete */
291 kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */
292 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0 Output */
293 kDmaRequestMux0Reserved43 = 43|0x100U, /**< Reserved43 */
294 kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */
295 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0 buffer pointer reaches upper or lower limit */
296 kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */
297 kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */
298 kDmaRequestMux0Reserved48 = 48|0x100U, /**< Reserved48 */
299 kDmaRequestMux0PortA = 49|0x100U, /**< PORTA rising, falling or both edges */
300 kDmaRequestMux0Reserved50 = 50|0x100U, /**< Reserved50 */
301 kDmaRequestMux0PortC = 51|0x100U, /**< PORTC rising, falling or both edges */
302 kDmaRequestMux0PortD = 52|0x100U, /**< PORTD rising, falling or both edges */
303 kDmaRequestMux0Reserved53 = 53|0x100U, /**< Reserved53 */
304 kDmaRequestMux0TPM0Overflow = 54|0x100U, /**< TPM0 overflow */
305 kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< TPM1 overflow */
306 kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< TPM2 overflow */
307 kDmaRequestMux0TSI = 57|0x100U, /**< TSI0 event */
308 kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */
309 kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */
310 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< Always enabled 60 */
311 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< Always enabled 61 */
312 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< Always enabled 62 */
313 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< Always enabled 63 */
314 } dma_request_source_t;
321 */ /* end of group Mapping_Information */
324 /* ----------------------------------------------------------------------------
325 -- Device Peripheral Access Layer
326 ---------------------------------------------------------------------------- */
329 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
335 ** Start of section using anonymous unions
338 #if defined(__ARMCC_VERSION)
339 #if (__ARMCC_VERSION >= 6010050)
340 #pragma clang diagnostic push
345 #elif defined(__CWCC__)
347 #pragma cpp_extensions on
348 #elif defined(__GNUC__)
349 /* anonymous unions are enabled by default */
350 #elif defined(__IAR_SYSTEMS_ICC__)
351 #pragma language=extended
353 #error Not supported compiler type
357 # define __I volatile
361 # define __O volatile
365 # define __IO volatile
368 /* ----------------------------------------------------------------------------
369 -- ADC Peripheral Access Layer
370 ---------------------------------------------------------------------------- */
373 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
377 /** ADC - Register Layout Typedef */
379 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
380 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
381 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
382 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
383 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
384 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
385 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
386 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
387 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
388 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
389 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
390 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
391 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
392 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
393 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
394 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
395 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
396 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
397 uint8_t RESERVED_0[4];
398 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
399 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
400 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
401 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
402 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
403 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
404 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
407 /* ----------------------------------------------------------------------------
408 -- ADC Register Masks
409 ---------------------------------------------------------------------------- */
412 * @addtogroup ADC_Register_Masks ADC Register Masks
416 /*! @name SC1 - ADC Status and Control Registers 1 */
417 #define ADC_SC1_ADCH_MASK (0x1FU)
418 #define ADC_SC1_ADCH_SHIFT (0U)
419 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
420 #define ADC_SC1_DIFF_MASK (0x20U)
421 #define ADC_SC1_DIFF_SHIFT (5U)
422 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
423 #define ADC_SC1_AIEN_MASK (0x40U)
424 #define ADC_SC1_AIEN_SHIFT (6U)
425 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
426 #define ADC_SC1_COCO_MASK (0x80U)
427 #define ADC_SC1_COCO_SHIFT (7U)
428 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
430 /* The count of ADC_SC1 */
431 #define ADC_SC1_COUNT (2U)
433 /*! @name CFG1 - ADC Configuration Register 1 */
434 #define ADC_CFG1_ADICLK_MASK (0x3U)
435 #define ADC_CFG1_ADICLK_SHIFT (0U)
436 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
437 #define ADC_CFG1_MODE_MASK (0xCU)
438 #define ADC_CFG1_MODE_SHIFT (2U)
439 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
440 #define ADC_CFG1_ADLSMP_MASK (0x10U)
441 #define ADC_CFG1_ADLSMP_SHIFT (4U)
442 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
443 #define ADC_CFG1_ADIV_MASK (0x60U)
444 #define ADC_CFG1_ADIV_SHIFT (5U)
445 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
446 #define ADC_CFG1_ADLPC_MASK (0x80U)
447 #define ADC_CFG1_ADLPC_SHIFT (7U)
448 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
450 /*! @name CFG2 - ADC Configuration Register 2 */
451 #define ADC_CFG2_ADLSTS_MASK (0x3U)
452 #define ADC_CFG2_ADLSTS_SHIFT (0U)
453 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
454 #define ADC_CFG2_ADHSC_MASK (0x4U)
455 #define ADC_CFG2_ADHSC_SHIFT (2U)
456 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
457 #define ADC_CFG2_ADACKEN_MASK (0x8U)
458 #define ADC_CFG2_ADACKEN_SHIFT (3U)
459 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
460 #define ADC_CFG2_MUXSEL_MASK (0x10U)
461 #define ADC_CFG2_MUXSEL_SHIFT (4U)
462 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
464 /*! @name R - ADC Data Result Register */
465 #define ADC_R_D_MASK (0xFFFFU)
466 #define ADC_R_D_SHIFT (0U)
467 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
469 /* The count of ADC_R */
470 #define ADC_R_COUNT (2U)
472 /*! @name CV1 - Compare Value Registers */
473 #define ADC_CV1_CV_MASK (0xFFFFU)
474 #define ADC_CV1_CV_SHIFT (0U)
475 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
477 /*! @name CV2 - Compare Value Registers */
478 #define ADC_CV2_CV_MASK (0xFFFFU)
479 #define ADC_CV2_CV_SHIFT (0U)
480 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
482 /*! @name SC2 - Status and Control Register 2 */
483 #define ADC_SC2_REFSEL_MASK (0x3U)
484 #define ADC_SC2_REFSEL_SHIFT (0U)
485 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
486 #define ADC_SC2_DMAEN_MASK (0x4U)
487 #define ADC_SC2_DMAEN_SHIFT (2U)
488 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
489 #define ADC_SC2_ACREN_MASK (0x8U)
490 #define ADC_SC2_ACREN_SHIFT (3U)
491 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
492 #define ADC_SC2_ACFGT_MASK (0x10U)
493 #define ADC_SC2_ACFGT_SHIFT (4U)
494 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
495 #define ADC_SC2_ACFE_MASK (0x20U)
496 #define ADC_SC2_ACFE_SHIFT (5U)
497 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
498 #define ADC_SC2_ADTRG_MASK (0x40U)
499 #define ADC_SC2_ADTRG_SHIFT (6U)
500 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
501 #define ADC_SC2_ADACT_MASK (0x80U)
502 #define ADC_SC2_ADACT_SHIFT (7U)
503 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
505 /*! @name SC3 - Status and Control Register 3 */
506 #define ADC_SC3_AVGS_MASK (0x3U)
507 #define ADC_SC3_AVGS_SHIFT (0U)
508 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
509 #define ADC_SC3_AVGE_MASK (0x4U)
510 #define ADC_SC3_AVGE_SHIFT (2U)
511 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
512 #define ADC_SC3_ADCO_MASK (0x8U)
513 #define ADC_SC3_ADCO_SHIFT (3U)
514 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
515 #define ADC_SC3_CALF_MASK (0x40U)
516 #define ADC_SC3_CALF_SHIFT (6U)
517 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
518 #define ADC_SC3_CAL_MASK (0x80U)
519 #define ADC_SC3_CAL_SHIFT (7U)
520 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
522 /*! @name OFS - ADC Offset Correction Register */
523 #define ADC_OFS_OFS_MASK (0xFFFFU)
524 #define ADC_OFS_OFS_SHIFT (0U)
525 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
527 /*! @name PG - ADC Plus-Side Gain Register */
528 #define ADC_PG_PG_MASK (0xFFFFU)
529 #define ADC_PG_PG_SHIFT (0U)
530 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
532 /*! @name MG - ADC Minus-Side Gain Register */
533 #define ADC_MG_MG_MASK (0xFFFFU)
534 #define ADC_MG_MG_SHIFT (0U)
535 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
537 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */
538 #define ADC_CLPD_CLPD_MASK (0x3FU)
539 #define ADC_CLPD_CLPD_SHIFT (0U)
540 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
542 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */
543 #define ADC_CLPS_CLPS_MASK (0x3FU)
544 #define ADC_CLPS_CLPS_SHIFT (0U)
545 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
547 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
548 #define ADC_CLP4_CLP4_MASK (0x3FFU)
549 #define ADC_CLP4_CLP4_SHIFT (0U)
550 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
552 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
553 #define ADC_CLP3_CLP3_MASK (0x1FFU)
554 #define ADC_CLP3_CLP3_SHIFT (0U)
555 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
557 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
558 #define ADC_CLP2_CLP2_MASK (0xFFU)
559 #define ADC_CLP2_CLP2_SHIFT (0U)
560 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
562 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
563 #define ADC_CLP1_CLP1_MASK (0x7FU)
564 #define ADC_CLP1_CLP1_SHIFT (0U)
565 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
567 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
568 #define ADC_CLP0_CLP0_MASK (0x3FU)
569 #define ADC_CLP0_CLP0_SHIFT (0U)
570 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
572 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */
573 #define ADC_CLMD_CLMD_MASK (0x3FU)
574 #define ADC_CLMD_CLMD_SHIFT (0U)
575 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
577 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */
578 #define ADC_CLMS_CLMS_MASK (0x3FU)
579 #define ADC_CLMS_CLMS_SHIFT (0U)
580 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
582 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
583 #define ADC_CLM4_CLM4_MASK (0x3FFU)
584 #define ADC_CLM4_CLM4_SHIFT (0U)
585 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
587 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
588 #define ADC_CLM3_CLM3_MASK (0x1FFU)
589 #define ADC_CLM3_CLM3_SHIFT (0U)
590 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
592 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
593 #define ADC_CLM2_CLM2_MASK (0xFFU)
594 #define ADC_CLM2_CLM2_SHIFT (0U)
595 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
597 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
598 #define ADC_CLM1_CLM1_MASK (0x7FU)
599 #define ADC_CLM1_CLM1_SHIFT (0U)
600 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
602 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
603 #define ADC_CLM0_CLM0_MASK (0x3FU)
604 #define ADC_CLM0_CLM0_SHIFT (0U)
605 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
610 */ /* end of group ADC_Register_Masks */
613 /* ADC - Peripheral instance base addresses */
614 /** Peripheral ADC0 base address */
615 #define ADC0_BASE (0x4003B000u)
616 /** Peripheral ADC0 base pointer */
617 #define ADC0 ((ADC_Type *)ADC0_BASE)
618 /** Array initializer of ADC peripheral base addresses */
619 #define ADC_BASE_ADDRS { ADC0_BASE }
620 /** Array initializer of ADC peripheral base pointers */
621 #define ADC_BASE_PTRS { ADC0 }
622 /** Interrupt vectors for the ADC peripheral type */
623 #define ADC_IRQS { ADC0_IRQn }
627 */ /* end of group ADC_Peripheral_Access_Layer */
630 /* ----------------------------------------------------------------------------
631 -- CMP Peripheral Access Layer
632 ---------------------------------------------------------------------------- */
635 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
639 /** CMP - Register Layout Typedef */
641 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
642 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
643 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
644 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
645 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
646 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
649 /* ----------------------------------------------------------------------------
650 -- CMP Register Masks
651 ---------------------------------------------------------------------------- */
654 * @addtogroup CMP_Register_Masks CMP Register Masks
658 /*! @name CR0 - CMP Control Register 0 */
659 #define CMP_CR0_HYSTCTR_MASK (0x3U)
660 #define CMP_CR0_HYSTCTR_SHIFT (0U)
661 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
662 #define CMP_CR0_FILTER_CNT_MASK (0x70U)
663 #define CMP_CR0_FILTER_CNT_SHIFT (4U)
664 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
666 /*! @name CR1 - CMP Control Register 1 */
667 #define CMP_CR1_EN_MASK (0x1U)
668 #define CMP_CR1_EN_SHIFT (0U)
669 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
670 #define CMP_CR1_OPE_MASK (0x2U)
671 #define CMP_CR1_OPE_SHIFT (1U)
672 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
673 #define CMP_CR1_COS_MASK (0x4U)
674 #define CMP_CR1_COS_SHIFT (2U)
675 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
676 #define CMP_CR1_INV_MASK (0x8U)
677 #define CMP_CR1_INV_SHIFT (3U)
678 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
679 #define CMP_CR1_PMODE_MASK (0x10U)
680 #define CMP_CR1_PMODE_SHIFT (4U)
681 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
682 #define CMP_CR1_TRIGM_MASK (0x20U)
683 #define CMP_CR1_TRIGM_SHIFT (5U)
684 #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
685 #define CMP_CR1_WE_MASK (0x40U)
686 #define CMP_CR1_WE_SHIFT (6U)
687 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
688 #define CMP_CR1_SE_MASK (0x80U)
689 #define CMP_CR1_SE_SHIFT (7U)
690 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
692 /*! @name FPR - CMP Filter Period Register */
693 #define CMP_FPR_FILT_PER_MASK (0xFFU)
694 #define CMP_FPR_FILT_PER_SHIFT (0U)
695 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
697 /*! @name SCR - CMP Status and Control Register */
698 #define CMP_SCR_COUT_MASK (0x1U)
699 #define CMP_SCR_COUT_SHIFT (0U)
700 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
701 #define CMP_SCR_CFF_MASK (0x2U)
702 #define CMP_SCR_CFF_SHIFT (1U)
703 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
704 #define CMP_SCR_CFR_MASK (0x4U)
705 #define CMP_SCR_CFR_SHIFT (2U)
706 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
707 #define CMP_SCR_IEF_MASK (0x8U)
708 #define CMP_SCR_IEF_SHIFT (3U)
709 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
710 #define CMP_SCR_IER_MASK (0x10U)
711 #define CMP_SCR_IER_SHIFT (4U)
712 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
713 #define CMP_SCR_DMAEN_MASK (0x40U)
714 #define CMP_SCR_DMAEN_SHIFT (6U)
715 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
717 /*! @name DACCR - DAC Control Register */
718 #define CMP_DACCR_VOSEL_MASK (0x3FU)
719 #define CMP_DACCR_VOSEL_SHIFT (0U)
720 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
721 #define CMP_DACCR_VRSEL_MASK (0x40U)
722 #define CMP_DACCR_VRSEL_SHIFT (6U)
723 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
724 #define CMP_DACCR_DACEN_MASK (0x80U)
725 #define CMP_DACCR_DACEN_SHIFT (7U)
726 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
728 /*! @name MUXCR - MUX Control Register */
729 #define CMP_MUXCR_MSEL_MASK (0x7U)
730 #define CMP_MUXCR_MSEL_SHIFT (0U)
731 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
732 #define CMP_MUXCR_PSEL_MASK (0x38U)
733 #define CMP_MUXCR_PSEL_SHIFT (3U)
734 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
735 #define CMP_MUXCR_PSTM_MASK (0x80U)
736 #define CMP_MUXCR_PSTM_SHIFT (7U)
737 #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
742 */ /* end of group CMP_Register_Masks */
745 /* CMP - Peripheral instance base addresses */
746 /** Peripheral CMP0 base address */
747 #define CMP0_BASE (0x40073000u)
748 /** Peripheral CMP0 base pointer */
749 #define CMP0 ((CMP_Type *)CMP0_BASE)
750 /** Array initializer of CMP peripheral base addresses */
751 #define CMP_BASE_ADDRS { CMP0_BASE }
752 /** Array initializer of CMP peripheral base pointers */
753 #define CMP_BASE_PTRS { CMP0 }
754 /** Interrupt vectors for the CMP peripheral type */
755 #define CMP_IRQS { CMP0_IRQn }
759 */ /* end of group CMP_Peripheral_Access_Layer */
762 /* ----------------------------------------------------------------------------
763 -- DAC Peripheral Access Layer
764 ---------------------------------------------------------------------------- */
767 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
771 /** DAC - Register Layout Typedef */
773 struct { /* offset: 0x0, array step: 0x2 */
774 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
775 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
777 uint8_t RESERVED_0[28];
778 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
779 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
780 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
781 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
784 /* ----------------------------------------------------------------------------
785 -- DAC Register Masks
786 ---------------------------------------------------------------------------- */
789 * @addtogroup DAC_Register_Masks DAC Register Masks
793 /*! @name DATL - DAC Data Low Register */
794 #define DAC_DATL_DATA0_MASK (0xFFU)
795 #define DAC_DATL_DATA0_SHIFT (0U)
796 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
798 /* The count of DAC_DATL */
799 #define DAC_DATL_COUNT (2U)
801 /*! @name DATH - DAC Data High Register */
802 #define DAC_DATH_DATA1_MASK (0xFU)
803 #define DAC_DATH_DATA1_SHIFT (0U)
804 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
806 /* The count of DAC_DATH */
807 #define DAC_DATH_COUNT (2U)
809 /*! @name SR - DAC Status Register */
810 #define DAC_SR_DACBFRPBF_MASK (0x1U)
811 #define DAC_SR_DACBFRPBF_SHIFT (0U)
812 #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
813 #define DAC_SR_DACBFRPTF_MASK (0x2U)
814 #define DAC_SR_DACBFRPTF_SHIFT (1U)
815 #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
817 /*! @name C0 - DAC Control Register */
818 #define DAC_C0_DACBBIEN_MASK (0x1U)
819 #define DAC_C0_DACBBIEN_SHIFT (0U)
820 #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
821 #define DAC_C0_DACBTIEN_MASK (0x2U)
822 #define DAC_C0_DACBTIEN_SHIFT (1U)
823 #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
824 #define DAC_C0_LPEN_MASK (0x8U)
825 #define DAC_C0_LPEN_SHIFT (3U)
826 #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
827 #define DAC_C0_DACSWTRG_MASK (0x10U)
828 #define DAC_C0_DACSWTRG_SHIFT (4U)
829 #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
830 #define DAC_C0_DACTRGSEL_MASK (0x20U)
831 #define DAC_C0_DACTRGSEL_SHIFT (5U)
832 #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
833 #define DAC_C0_DACRFS_MASK (0x40U)
834 #define DAC_C0_DACRFS_SHIFT (6U)
835 #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
836 #define DAC_C0_DACEN_MASK (0x80U)
837 #define DAC_C0_DACEN_SHIFT (7U)
838 #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
840 /*! @name C1 - DAC Control Register 1 */
841 #define DAC_C1_DACBFEN_MASK (0x1U)
842 #define DAC_C1_DACBFEN_SHIFT (0U)
843 #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
844 #define DAC_C1_DACBFMD_MASK (0x4U)
845 #define DAC_C1_DACBFMD_SHIFT (2U)
846 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
847 #define DAC_C1_DMAEN_MASK (0x80U)
848 #define DAC_C1_DMAEN_SHIFT (7U)
849 #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
851 /*! @name C2 - DAC Control Register 2 */
852 #define DAC_C2_DACBFUP_MASK (0x1U)
853 #define DAC_C2_DACBFUP_SHIFT (0U)
854 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
855 #define DAC_C2_DACBFRP_MASK (0x10U)
856 #define DAC_C2_DACBFRP_SHIFT (4U)
857 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
862 */ /* end of group DAC_Register_Masks */
865 /* DAC - Peripheral instance base addresses */
866 /** Peripheral DAC0 base address */
867 #define DAC0_BASE (0x4003F000u)
868 /** Peripheral DAC0 base pointer */
869 #define DAC0 ((DAC_Type *)DAC0_BASE)
870 /** Array initializer of DAC peripheral base addresses */
871 #define DAC_BASE_ADDRS { DAC0_BASE }
872 /** Array initializer of DAC peripheral base pointers */
873 #define DAC_BASE_PTRS { DAC0 }
874 /** Interrupt vectors for the DAC peripheral type */
875 #define DAC_IRQS { DAC0_IRQn }
879 */ /* end of group DAC_Peripheral_Access_Layer */
882 /* ----------------------------------------------------------------------------
883 -- DMA Peripheral Access Layer
884 ---------------------------------------------------------------------------- */
887 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
891 /** DMA - Register Layout Typedef */
893 uint8_t RESERVED_0[256];
894 struct { /* offset: 0x100, array step: 0x10 */
895 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
896 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
897 union { /* offset: 0x108, array step: 0x10 */
898 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
899 struct { /* offset: 0x108, array step: 0x10 */
900 uint8_t RESERVED_0[3];
901 uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
902 } DMA_DSR_ACCESS8BIT;
904 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
908 /* ----------------------------------------------------------------------------
909 -- DMA Register Masks
910 ---------------------------------------------------------------------------- */
913 * @addtogroup DMA_Register_Masks DMA Register Masks
917 /*! @name SAR - Source Address Register */
918 #define DMA_SAR_SAR_MASK (0xFFFFFFFFU)
919 #define DMA_SAR_SAR_SHIFT (0U)
920 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SAR_SAR_SHIFT)) & DMA_SAR_SAR_MASK)
922 /* The count of DMA_SAR */
923 #define DMA_SAR_COUNT (4U)
925 /*! @name DAR - Destination Address Register */
926 #define DMA_DAR_DAR_MASK (0xFFFFFFFFU)
927 #define DMA_DAR_DAR_SHIFT (0U)
928 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DAR_DAR_SHIFT)) & DMA_DAR_DAR_MASK)
930 /* The count of DMA_DAR */
931 #define DMA_DAR_COUNT (4U)
933 /*! @name DSR_BCR - DMA Status Register / Byte Count Register */
934 #define DMA_DSR_BCR_BCR_MASK (0xFFFFFFU)
935 #define DMA_DSR_BCR_BCR_SHIFT (0U)
936 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BCR_SHIFT)) & DMA_DSR_BCR_BCR_MASK)
937 #define DMA_DSR_BCR_DONE_MASK (0x1000000U)
938 #define DMA_DSR_BCR_DONE_SHIFT (24U)
939 #define DMA_DSR_BCR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_DONE_SHIFT)) & DMA_DSR_BCR_DONE_MASK)
940 #define DMA_DSR_BCR_BSY_MASK (0x2000000U)
941 #define DMA_DSR_BCR_BSY_SHIFT (25U)
942 #define DMA_DSR_BCR_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BSY_SHIFT)) & DMA_DSR_BCR_BSY_MASK)
943 #define DMA_DSR_BCR_REQ_MASK (0x4000000U)
944 #define DMA_DSR_BCR_REQ_SHIFT (26U)
945 #define DMA_DSR_BCR_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_REQ_SHIFT)) & DMA_DSR_BCR_REQ_MASK)
946 #define DMA_DSR_BCR_BED_MASK (0x10000000U)
947 #define DMA_DSR_BCR_BED_SHIFT (28U)
948 #define DMA_DSR_BCR_BED(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BED_SHIFT)) & DMA_DSR_BCR_BED_MASK)
949 #define DMA_DSR_BCR_BES_MASK (0x20000000U)
950 #define DMA_DSR_BCR_BES_SHIFT (29U)
951 #define DMA_DSR_BCR_BES(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BES_SHIFT)) & DMA_DSR_BCR_BES_MASK)
952 #define DMA_DSR_BCR_CE_MASK (0x40000000U)
953 #define DMA_DSR_BCR_CE_SHIFT (30U)
954 #define DMA_DSR_BCR_CE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_CE_SHIFT)) & DMA_DSR_BCR_CE_MASK)
956 /* The count of DMA_DSR_BCR */
957 #define DMA_DSR_BCR_COUNT (4U)
959 /* The count of DMA_DSR */
960 #define DMA_DSR_COUNT (4U)
962 /*! @name DCR - DMA Control Register */
963 #define DMA_DCR_LCH2_MASK (0x3U)
964 #define DMA_DCR_LCH2_SHIFT (0U)
965 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH2_SHIFT)) & DMA_DCR_LCH2_MASK)
966 #define DMA_DCR_LCH1_MASK (0xCU)
967 #define DMA_DCR_LCH1_SHIFT (2U)
968 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH1_SHIFT)) & DMA_DCR_LCH1_MASK)
969 #define DMA_DCR_LINKCC_MASK (0x30U)
970 #define DMA_DCR_LINKCC_SHIFT (4U)
971 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LINKCC_SHIFT)) & DMA_DCR_LINKCC_MASK)
972 #define DMA_DCR_D_REQ_MASK (0x80U)
973 #define DMA_DCR_D_REQ_SHIFT (7U)
974 #define DMA_DCR_D_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_D_REQ_SHIFT)) & DMA_DCR_D_REQ_MASK)
975 #define DMA_DCR_DMOD_MASK (0xF00U)
976 #define DMA_DCR_DMOD_SHIFT (8U)
977 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DMOD_SHIFT)) & DMA_DCR_DMOD_MASK)
978 #define DMA_DCR_SMOD_MASK (0xF000U)
979 #define DMA_DCR_SMOD_SHIFT (12U)
980 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SMOD_SHIFT)) & DMA_DCR_SMOD_MASK)
981 #define DMA_DCR_START_MASK (0x10000U)
982 #define DMA_DCR_START_SHIFT (16U)
983 #define DMA_DCR_START(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_START_SHIFT)) & DMA_DCR_START_MASK)
984 #define DMA_DCR_DSIZE_MASK (0x60000U)
985 #define DMA_DCR_DSIZE_SHIFT (17U)
986 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DSIZE_SHIFT)) & DMA_DCR_DSIZE_MASK)
987 #define DMA_DCR_DINC_MASK (0x80000U)
988 #define DMA_DCR_DINC_SHIFT (19U)
989 #define DMA_DCR_DINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DINC_SHIFT)) & DMA_DCR_DINC_MASK)
990 #define DMA_DCR_SSIZE_MASK (0x300000U)
991 #define DMA_DCR_SSIZE_SHIFT (20U)
992 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SSIZE_SHIFT)) & DMA_DCR_SSIZE_MASK)
993 #define DMA_DCR_SINC_MASK (0x400000U)
994 #define DMA_DCR_SINC_SHIFT (22U)
995 #define DMA_DCR_SINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SINC_SHIFT)) & DMA_DCR_SINC_MASK)
996 #define DMA_DCR_EADREQ_MASK (0x800000U)
997 #define DMA_DCR_EADREQ_SHIFT (23U)
998 #define DMA_DCR_EADREQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EADREQ_SHIFT)) & DMA_DCR_EADREQ_MASK)
999 #define DMA_DCR_AA_MASK (0x10000000U)
1000 #define DMA_DCR_AA_SHIFT (28U)
1001 #define DMA_DCR_AA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_AA_SHIFT)) & DMA_DCR_AA_MASK)
1002 #define DMA_DCR_CS_MASK (0x20000000U)
1003 #define DMA_DCR_CS_SHIFT (29U)
1004 #define DMA_DCR_CS(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_CS_SHIFT)) & DMA_DCR_CS_MASK)
1005 #define DMA_DCR_ERQ_MASK (0x40000000U)
1006 #define DMA_DCR_ERQ_SHIFT (30U)
1007 #define DMA_DCR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_ERQ_SHIFT)) & DMA_DCR_ERQ_MASK)
1008 #define DMA_DCR_EINT_MASK (0x80000000U)
1009 #define DMA_DCR_EINT_SHIFT (31U)
1010 #define DMA_DCR_EINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EINT_SHIFT)) & DMA_DCR_EINT_MASK)
1012 /* The count of DMA_DCR */
1013 #define DMA_DCR_COUNT (4U)
1018 */ /* end of group DMA_Register_Masks */
1021 /* DMA - Peripheral instance base addresses */
1022 /** Peripheral DMA base address */
1023 #define DMA_BASE (0x40008000u)
1024 /** Peripheral DMA base pointer */
1025 #define DMA0 ((DMA_Type *)DMA_BASE)
1026 /** Array initializer of DMA peripheral base addresses */
1027 #define DMA_BASE_ADDRS { DMA_BASE }
1028 /** Array initializer of DMA peripheral base pointers */
1029 #define DMA_BASE_PTRS { DMA0 }
1030 /** Interrupt vectors for the DMA peripheral type */
1031 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
1035 */ /* end of group DMA_Peripheral_Access_Layer */
1038 /* ----------------------------------------------------------------------------
1039 -- DMAMUX Peripheral Access Layer
1040 ---------------------------------------------------------------------------- */
1043 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
1047 /** DMAMUX - Register Layout Typedef */
1049 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
1052 /* ----------------------------------------------------------------------------
1053 -- DMAMUX Register Masks
1054 ---------------------------------------------------------------------------- */
1057 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
1061 /*! @name CHCFG - Channel Configuration register */
1062 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
1063 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
1064 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
1065 #define DMAMUX_CHCFG_TRIG_MASK (0x40U)
1066 #define DMAMUX_CHCFG_TRIG_SHIFT (6U)
1067 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
1068 #define DMAMUX_CHCFG_ENBL_MASK (0x80U)
1069 #define DMAMUX_CHCFG_ENBL_SHIFT (7U)
1070 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
1072 /* The count of DMAMUX_CHCFG */
1073 #define DMAMUX_CHCFG_COUNT (4U)
1078 */ /* end of group DMAMUX_Register_Masks */
1081 /* DMAMUX - Peripheral instance base addresses */
1082 /** Peripheral DMAMUX0 base address */
1083 #define DMAMUX0_BASE (0x40021000u)
1084 /** Peripheral DMAMUX0 base pointer */
1085 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
1086 /** Array initializer of DMAMUX peripheral base addresses */
1087 #define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
1088 /** Array initializer of DMAMUX peripheral base pointers */
1089 #define DMAMUX_BASE_PTRS { DMAMUX0 }
1093 */ /* end of group DMAMUX_Peripheral_Access_Layer */
1096 /* ----------------------------------------------------------------------------
1097 -- FGPIO Peripheral Access Layer
1098 ---------------------------------------------------------------------------- */
1101 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
1105 /** FGPIO - Register Layout Typedef */
1107 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
1108 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
1109 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
1110 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
1111 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
1112 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
1115 /* ----------------------------------------------------------------------------
1116 -- FGPIO Register Masks
1117 ---------------------------------------------------------------------------- */
1120 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
1124 /*! @name PDOR - Port Data Output Register */
1125 #define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
1126 #define FGPIO_PDOR_PDO_SHIFT (0U)
1127 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK)
1129 /*! @name PSOR - Port Set Output Register */
1130 #define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
1131 #define FGPIO_PSOR_PTSO_SHIFT (0U)
1132 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK)
1134 /*! @name PCOR - Port Clear Output Register */
1135 #define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
1136 #define FGPIO_PCOR_PTCO_SHIFT (0U)
1137 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK)
1139 /*! @name PTOR - Port Toggle Output Register */
1140 #define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
1141 #define FGPIO_PTOR_PTTO_SHIFT (0U)
1142 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK)
1144 /*! @name PDIR - Port Data Input Register */
1145 #define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
1146 #define FGPIO_PDIR_PDI_SHIFT (0U)
1147 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK)
1149 /*! @name PDDR - Port Data Direction Register */
1150 #define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
1151 #define FGPIO_PDDR_PDD_SHIFT (0U)
1152 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK)
1157 */ /* end of group FGPIO_Register_Masks */
1160 /* FGPIO - Peripheral instance base addresses */
1161 /** Peripheral FGPIOA base address */
1162 #define FGPIOA_BASE (0xF8000000u)
1163 /** Peripheral FGPIOA base pointer */
1164 #define FGPIOA ((FGPIO_Type *)FGPIOA_BASE)
1165 /** Peripheral FGPIOB base address */
1166 #define FGPIOB_BASE (0xF8000040u)
1167 /** Peripheral FGPIOB base pointer */
1168 #define FGPIOB ((FGPIO_Type *)FGPIOB_BASE)
1169 /** Peripheral FGPIOC base address */
1170 #define FGPIOC_BASE (0xF8000080u)
1171 /** Peripheral FGPIOC base pointer */
1172 #define FGPIOC ((FGPIO_Type *)FGPIOC_BASE)
1173 /** Peripheral FGPIOD base address */
1174 #define FGPIOD_BASE (0xF80000C0u)
1175 /** Peripheral FGPIOD base pointer */
1176 #define FGPIOD ((FGPIO_Type *)FGPIOD_BASE)
1177 /** Peripheral FGPIOE base address */
1178 #define FGPIOE_BASE (0xF8000100u)
1179 /** Peripheral FGPIOE base pointer */
1180 #define FGPIOE ((FGPIO_Type *)FGPIOE_BASE)
1181 /** Array initializer of FGPIO peripheral base addresses */
1182 #define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE, FGPIOD_BASE, FGPIOE_BASE }
1183 /** Array initializer of FGPIO peripheral base pointers */
1184 #define FGPIO_BASE_PTRS { FGPIOA, FGPIOB, FGPIOC, FGPIOD, FGPIOE }
1188 */ /* end of group FGPIO_Peripheral_Access_Layer */
1191 /* ----------------------------------------------------------------------------
1192 -- FTFA Peripheral Access Layer
1193 ---------------------------------------------------------------------------- */
1196 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
1200 /** FTFA - Register Layout Typedef */
1202 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
1203 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
1204 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
1205 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
1206 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
1207 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
1208 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
1209 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
1210 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
1211 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
1212 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
1213 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
1214 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
1215 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
1216 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
1217 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
1218 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
1219 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
1220 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
1221 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
1224 /* ----------------------------------------------------------------------------
1225 -- FTFA Register Masks
1226 ---------------------------------------------------------------------------- */
1229 * @addtogroup FTFA_Register_Masks FTFA Register Masks
1233 /*! @name FSTAT - Flash Status Register */
1234 #define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
1235 #define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
1236 #define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
1237 #define FTFA_FSTAT_FPVIOL_MASK (0x10U)
1238 #define FTFA_FSTAT_FPVIOL_SHIFT (4U)
1239 #define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
1240 #define FTFA_FSTAT_ACCERR_MASK (0x20U)
1241 #define FTFA_FSTAT_ACCERR_SHIFT (5U)
1242 #define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
1243 #define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
1244 #define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
1245 #define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
1246 #define FTFA_FSTAT_CCIF_MASK (0x80U)
1247 #define FTFA_FSTAT_CCIF_SHIFT (7U)
1248 #define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
1250 /*! @name FCNFG - Flash Configuration Register */
1251 #define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
1252 #define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
1253 #define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
1254 #define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
1255 #define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
1256 #define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
1257 #define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
1258 #define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
1259 #define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
1260 #define FTFA_FCNFG_CCIE_MASK (0x80U)
1261 #define FTFA_FCNFG_CCIE_SHIFT (7U)
1262 #define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
1264 /*! @name FSEC - Flash Security Register */
1265 #define FTFA_FSEC_SEC_MASK (0x3U)
1266 #define FTFA_FSEC_SEC_SHIFT (0U)
1267 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
1268 #define FTFA_FSEC_FSLACC_MASK (0xCU)
1269 #define FTFA_FSEC_FSLACC_SHIFT (2U)
1270 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
1271 #define FTFA_FSEC_MEEN_MASK (0x30U)
1272 #define FTFA_FSEC_MEEN_SHIFT (4U)
1273 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
1274 #define FTFA_FSEC_KEYEN_MASK (0xC0U)
1275 #define FTFA_FSEC_KEYEN_SHIFT (6U)
1276 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
1278 /*! @name FOPT - Flash Option Register */
1279 #define FTFA_FOPT_OPT_MASK (0xFFU)
1280 #define FTFA_FOPT_OPT_SHIFT (0U)
1281 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
1283 /*! @name FCCOB3 - Flash Common Command Object Registers */
1284 #define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
1285 #define FTFA_FCCOB3_CCOBn_SHIFT (0U)
1286 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
1288 /*! @name FCCOB2 - Flash Common Command Object Registers */
1289 #define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
1290 #define FTFA_FCCOB2_CCOBn_SHIFT (0U)
1291 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
1293 /*! @name FCCOB1 - Flash Common Command Object Registers */
1294 #define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
1295 #define FTFA_FCCOB1_CCOBn_SHIFT (0U)
1296 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
1298 /*! @name FCCOB0 - Flash Common Command Object Registers */
1299 #define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
1300 #define FTFA_FCCOB0_CCOBn_SHIFT (0U)
1301 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
1303 /*! @name FCCOB7 - Flash Common Command Object Registers */
1304 #define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
1305 #define FTFA_FCCOB7_CCOBn_SHIFT (0U)
1306 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
1308 /*! @name FCCOB6 - Flash Common Command Object Registers */
1309 #define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
1310 #define FTFA_FCCOB6_CCOBn_SHIFT (0U)
1311 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
1313 /*! @name FCCOB5 - Flash Common Command Object Registers */
1314 #define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
1315 #define FTFA_FCCOB5_CCOBn_SHIFT (0U)
1316 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
1318 /*! @name FCCOB4 - Flash Common Command Object Registers */
1319 #define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
1320 #define FTFA_FCCOB4_CCOBn_SHIFT (0U)
1321 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
1323 /*! @name FCCOBB - Flash Common Command Object Registers */
1324 #define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
1325 #define FTFA_FCCOBB_CCOBn_SHIFT (0U)
1326 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
1328 /*! @name FCCOBA - Flash Common Command Object Registers */
1329 #define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
1330 #define FTFA_FCCOBA_CCOBn_SHIFT (0U)
1331 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
1333 /*! @name FCCOB9 - Flash Common Command Object Registers */
1334 #define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
1335 #define FTFA_FCCOB9_CCOBn_SHIFT (0U)
1336 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
1338 /*! @name FCCOB8 - Flash Common Command Object Registers */
1339 #define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
1340 #define FTFA_FCCOB8_CCOBn_SHIFT (0U)
1341 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
1343 /*! @name FPROT3 - Program Flash Protection Registers */
1344 #define FTFA_FPROT3_PROT_MASK (0xFFU)
1345 #define FTFA_FPROT3_PROT_SHIFT (0U)
1346 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
1348 /*! @name FPROT2 - Program Flash Protection Registers */
1349 #define FTFA_FPROT2_PROT_MASK (0xFFU)
1350 #define FTFA_FPROT2_PROT_SHIFT (0U)
1351 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
1353 /*! @name FPROT1 - Program Flash Protection Registers */
1354 #define FTFA_FPROT1_PROT_MASK (0xFFU)
1355 #define FTFA_FPROT1_PROT_SHIFT (0U)
1356 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
1358 /*! @name FPROT0 - Program Flash Protection Registers */
1359 #define FTFA_FPROT0_PROT_MASK (0xFFU)
1360 #define FTFA_FPROT0_PROT_SHIFT (0U)
1361 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
1366 */ /* end of group FTFA_Register_Masks */
1369 /* FTFA - Peripheral instance base addresses */
1370 /** Peripheral FTFA base address */
1371 #define FTFA_BASE (0x40020000u)
1372 /** Peripheral FTFA base pointer */
1373 #define FTFA ((FTFA_Type *)FTFA_BASE)
1374 /** Array initializer of FTFA peripheral base addresses */
1375 #define FTFA_BASE_ADDRS { FTFA_BASE }
1376 /** Array initializer of FTFA peripheral base pointers */
1377 #define FTFA_BASE_PTRS { FTFA }
1378 /** Interrupt vectors for the FTFA peripheral type */
1379 #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
1383 */ /* end of group FTFA_Peripheral_Access_Layer */
1386 /* ----------------------------------------------------------------------------
1387 -- GPIO Peripheral Access Layer
1388 ---------------------------------------------------------------------------- */
1391 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
1395 /** GPIO - Register Layout Typedef */
1397 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
1398 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
1399 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
1400 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
1401 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
1402 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
1405 /* ----------------------------------------------------------------------------
1406 -- GPIO Register Masks
1407 ---------------------------------------------------------------------------- */
1410 * @addtogroup GPIO_Register_Masks GPIO Register Masks
1414 /*! @name PDOR - Port Data Output Register */
1415 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
1416 #define GPIO_PDOR_PDO_SHIFT (0U)
1417 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
1419 /*! @name PSOR - Port Set Output Register */
1420 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
1421 #define GPIO_PSOR_PTSO_SHIFT (0U)
1422 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
1424 /*! @name PCOR - Port Clear Output Register */
1425 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
1426 #define GPIO_PCOR_PTCO_SHIFT (0U)
1427 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
1429 /*! @name PTOR - Port Toggle Output Register */
1430 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
1431 #define GPIO_PTOR_PTTO_SHIFT (0U)
1432 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
1434 /*! @name PDIR - Port Data Input Register */
1435 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
1436 #define GPIO_PDIR_PDI_SHIFT (0U)
1437 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
1439 /*! @name PDDR - Port Data Direction Register */
1440 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
1441 #define GPIO_PDDR_PDD_SHIFT (0U)
1442 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
1447 */ /* end of group GPIO_Register_Masks */
1450 /* GPIO - Peripheral instance base addresses */
1451 /** Peripheral GPIOA base address */
1452 #define GPIOA_BASE (0x400FF000u)
1453 /** Peripheral GPIOA base pointer */
1454 #define GPIOA ((GPIO_Type *)GPIOA_BASE)
1455 /** Peripheral GPIOB base address */
1456 #define GPIOB_BASE (0x400FF040u)
1457 /** Peripheral GPIOB base pointer */
1458 #define GPIOB ((GPIO_Type *)GPIOB_BASE)
1459 /** Peripheral GPIOC base address */
1460 #define GPIOC_BASE (0x400FF080u)
1461 /** Peripheral GPIOC base pointer */
1462 #define GPIOC ((GPIO_Type *)GPIOC_BASE)
1463 /** Peripheral GPIOD base address */
1464 #define GPIOD_BASE (0x400FF0C0u)
1465 /** Peripheral GPIOD base pointer */
1466 #define GPIOD ((GPIO_Type *)GPIOD_BASE)
1467 /** Peripheral GPIOE base address */
1468 #define GPIOE_BASE (0x400FF100u)
1469 /** Peripheral GPIOE base pointer */
1470 #define GPIOE ((GPIO_Type *)GPIOE_BASE)
1471 /** Array initializer of GPIO peripheral base addresses */
1472 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
1473 /** Array initializer of GPIO peripheral base pointers */
1474 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
1478 */ /* end of group GPIO_Peripheral_Access_Layer */
1481 /* ----------------------------------------------------------------------------
1482 -- I2C Peripheral Access Layer
1483 ---------------------------------------------------------------------------- */
1486 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
1490 /** I2C - Register Layout Typedef */
1492 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
1493 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
1494 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
1495 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
1496 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
1497 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
1498 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
1499 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
1500 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
1501 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
1502 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
1503 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
1506 /* ----------------------------------------------------------------------------
1507 -- I2C Register Masks
1508 ---------------------------------------------------------------------------- */
1511 * @addtogroup I2C_Register_Masks I2C Register Masks
1515 /*! @name A1 - I2C Address Register 1 */
1516 #define I2C_A1_AD_MASK (0xFEU)
1517 #define I2C_A1_AD_SHIFT (1U)
1518 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
1520 /*! @name F - I2C Frequency Divider register */
1521 #define I2C_F_ICR_MASK (0x3FU)
1522 #define I2C_F_ICR_SHIFT (0U)
1523 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
1524 #define I2C_F_MULT_MASK (0xC0U)
1525 #define I2C_F_MULT_SHIFT (6U)
1526 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
1528 /*! @name C1 - I2C Control Register 1 */
1529 #define I2C_C1_DMAEN_MASK (0x1U)
1530 #define I2C_C1_DMAEN_SHIFT (0U)
1531 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
1532 #define I2C_C1_WUEN_MASK (0x2U)
1533 #define I2C_C1_WUEN_SHIFT (1U)
1534 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
1535 #define I2C_C1_RSTA_MASK (0x4U)
1536 #define I2C_C1_RSTA_SHIFT (2U)
1537 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
1538 #define I2C_C1_TXAK_MASK (0x8U)
1539 #define I2C_C1_TXAK_SHIFT (3U)
1540 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
1541 #define I2C_C1_TX_MASK (0x10U)
1542 #define I2C_C1_TX_SHIFT (4U)
1543 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
1544 #define I2C_C1_MST_MASK (0x20U)
1545 #define I2C_C1_MST_SHIFT (5U)
1546 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
1547 #define I2C_C1_IICIE_MASK (0x40U)
1548 #define I2C_C1_IICIE_SHIFT (6U)
1549 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
1550 #define I2C_C1_IICEN_MASK (0x80U)
1551 #define I2C_C1_IICEN_SHIFT (7U)
1552 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
1554 /*! @name S - I2C Status register */
1555 #define I2C_S_RXAK_MASK (0x1U)
1556 #define I2C_S_RXAK_SHIFT (0U)
1557 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
1558 #define I2C_S_IICIF_MASK (0x2U)
1559 #define I2C_S_IICIF_SHIFT (1U)
1560 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
1561 #define I2C_S_SRW_MASK (0x4U)
1562 #define I2C_S_SRW_SHIFT (2U)
1563 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
1564 #define I2C_S_RAM_MASK (0x8U)
1565 #define I2C_S_RAM_SHIFT (3U)
1566 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
1567 #define I2C_S_ARBL_MASK (0x10U)
1568 #define I2C_S_ARBL_SHIFT (4U)
1569 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
1570 #define I2C_S_BUSY_MASK (0x20U)
1571 #define I2C_S_BUSY_SHIFT (5U)
1572 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
1573 #define I2C_S_IAAS_MASK (0x40U)
1574 #define I2C_S_IAAS_SHIFT (6U)
1575 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
1576 #define I2C_S_TCF_MASK (0x80U)
1577 #define I2C_S_TCF_SHIFT (7U)
1578 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
1580 /*! @name D - I2C Data I/O register */
1581 #define I2C_D_DATA_MASK (0xFFU)
1582 #define I2C_D_DATA_SHIFT (0U)
1583 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
1585 /*! @name C2 - I2C Control Register 2 */
1586 #define I2C_C2_AD_MASK (0x7U)
1587 #define I2C_C2_AD_SHIFT (0U)
1588 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
1589 #define I2C_C2_RMEN_MASK (0x8U)
1590 #define I2C_C2_RMEN_SHIFT (3U)
1591 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
1592 #define I2C_C2_SBRC_MASK (0x10U)
1593 #define I2C_C2_SBRC_SHIFT (4U)
1594 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
1595 #define I2C_C2_HDRS_MASK (0x20U)
1596 #define I2C_C2_HDRS_SHIFT (5U)
1597 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
1598 #define I2C_C2_ADEXT_MASK (0x40U)
1599 #define I2C_C2_ADEXT_SHIFT (6U)
1600 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
1601 #define I2C_C2_GCAEN_MASK (0x80U)
1602 #define I2C_C2_GCAEN_SHIFT (7U)
1603 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
1605 /*! @name FLT - I2C Programmable Input Glitch Filter register */
1606 #define I2C_FLT_FLT_MASK (0xFU)
1607 #define I2C_FLT_FLT_SHIFT (0U)
1608 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
1609 #define I2C_FLT_STARTF_MASK (0x10U)
1610 #define I2C_FLT_STARTF_SHIFT (4U)
1611 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
1612 #define I2C_FLT_SSIE_MASK (0x20U)
1613 #define I2C_FLT_SSIE_SHIFT (5U)
1614 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
1615 #define I2C_FLT_STOPF_MASK (0x40U)
1616 #define I2C_FLT_STOPF_SHIFT (6U)
1617 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
1618 #define I2C_FLT_SHEN_MASK (0x80U)
1619 #define I2C_FLT_SHEN_SHIFT (7U)
1620 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
1622 /*! @name RA - I2C Range Address register */
1623 #define I2C_RA_RAD_MASK (0xFEU)
1624 #define I2C_RA_RAD_SHIFT (1U)
1625 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
1627 /*! @name SMB - I2C SMBus Control and Status register */
1628 #define I2C_SMB_SHTF2IE_MASK (0x1U)
1629 #define I2C_SMB_SHTF2IE_SHIFT (0U)
1630 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
1631 #define I2C_SMB_SHTF2_MASK (0x2U)
1632 #define I2C_SMB_SHTF2_SHIFT (1U)
1633 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
1634 #define I2C_SMB_SHTF1_MASK (0x4U)
1635 #define I2C_SMB_SHTF1_SHIFT (2U)
1636 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
1637 #define I2C_SMB_SLTF_MASK (0x8U)
1638 #define I2C_SMB_SLTF_SHIFT (3U)
1639 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
1640 #define I2C_SMB_TCKSEL_MASK (0x10U)
1641 #define I2C_SMB_TCKSEL_SHIFT (4U)
1642 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
1643 #define I2C_SMB_SIICAEN_MASK (0x20U)
1644 #define I2C_SMB_SIICAEN_SHIFT (5U)
1645 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
1646 #define I2C_SMB_ALERTEN_MASK (0x40U)
1647 #define I2C_SMB_ALERTEN_SHIFT (6U)
1648 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
1649 #define I2C_SMB_FACK_MASK (0x80U)
1650 #define I2C_SMB_FACK_SHIFT (7U)
1651 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
1653 /*! @name A2 - I2C Address Register 2 */
1654 #define I2C_A2_SAD_MASK (0xFEU)
1655 #define I2C_A2_SAD_SHIFT (1U)
1656 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
1658 /*! @name SLTH - I2C SCL Low Timeout Register High */
1659 #define I2C_SLTH_SSLT_MASK (0xFFU)
1660 #define I2C_SLTH_SSLT_SHIFT (0U)
1661 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
1663 /*! @name SLTL - I2C SCL Low Timeout Register Low */
1664 #define I2C_SLTL_SSLT_MASK (0xFFU)
1665 #define I2C_SLTL_SSLT_SHIFT (0U)
1666 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
1671 */ /* end of group I2C_Register_Masks */
1674 /* I2C - Peripheral instance base addresses */
1675 /** Peripheral I2C0 base address */
1676 #define I2C0_BASE (0x40066000u)
1677 /** Peripheral I2C0 base pointer */
1678 #define I2C0 ((I2C_Type *)I2C0_BASE)
1679 /** Peripheral I2C1 base address */
1680 #define I2C1_BASE (0x40067000u)
1681 /** Peripheral I2C1 base pointer */
1682 #define I2C1 ((I2C_Type *)I2C1_BASE)
1683 /** Array initializer of I2C peripheral base addresses */
1684 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
1685 /** Array initializer of I2C peripheral base pointers */
1686 #define I2C_BASE_PTRS { I2C0, I2C1 }
1687 /** Interrupt vectors for the I2C peripheral type */
1688 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
1692 */ /* end of group I2C_Peripheral_Access_Layer */
1695 /* ----------------------------------------------------------------------------
1696 -- I2S Peripheral Access Layer
1697 ---------------------------------------------------------------------------- */
1700 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
1704 /** I2S - Register Layout Typedef */
1706 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
1707 uint8_t RESERVED_0[4];
1708 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
1709 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
1710 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
1711 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
1712 uint8_t RESERVED_1[8];
1713 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
1714 uint8_t RESERVED_2[60];
1715 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
1716 uint8_t RESERVED_3[28];
1717 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
1718 uint8_t RESERVED_4[4];
1719 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
1720 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
1721 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
1722 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
1723 uint8_t RESERVED_5[8];
1724 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
1725 uint8_t RESERVED_6[60];
1726 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
1727 uint8_t RESERVED_7[28];
1728 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
1729 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
1732 /* ----------------------------------------------------------------------------
1733 -- I2S Register Masks
1734 ---------------------------------------------------------------------------- */
1737 * @addtogroup I2S_Register_Masks I2S Register Masks
1741 /*! @name TCSR - SAI Transmit Control Register */
1742 #define I2S_TCSR_FWDE_MASK (0x2U)
1743 #define I2S_TCSR_FWDE_SHIFT (1U)
1744 #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
1745 #define I2S_TCSR_FWIE_MASK (0x200U)
1746 #define I2S_TCSR_FWIE_SHIFT (9U)
1747 #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
1748 #define I2S_TCSR_FEIE_MASK (0x400U)
1749 #define I2S_TCSR_FEIE_SHIFT (10U)
1750 #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
1751 #define I2S_TCSR_SEIE_MASK (0x800U)
1752 #define I2S_TCSR_SEIE_SHIFT (11U)
1753 #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
1754 #define I2S_TCSR_WSIE_MASK (0x1000U)
1755 #define I2S_TCSR_WSIE_SHIFT (12U)
1756 #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
1757 #define I2S_TCSR_FWF_MASK (0x20000U)
1758 #define I2S_TCSR_FWF_SHIFT (17U)
1759 #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
1760 #define I2S_TCSR_FEF_MASK (0x40000U)
1761 #define I2S_TCSR_FEF_SHIFT (18U)
1762 #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
1763 #define I2S_TCSR_SEF_MASK (0x80000U)
1764 #define I2S_TCSR_SEF_SHIFT (19U)
1765 #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
1766 #define I2S_TCSR_WSF_MASK (0x100000U)
1767 #define I2S_TCSR_WSF_SHIFT (20U)
1768 #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
1769 #define I2S_TCSR_SR_MASK (0x1000000U)
1770 #define I2S_TCSR_SR_SHIFT (24U)
1771 #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
1772 #define I2S_TCSR_FR_MASK (0x2000000U)
1773 #define I2S_TCSR_FR_SHIFT (25U)
1774 #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
1775 #define I2S_TCSR_BCE_MASK (0x10000000U)
1776 #define I2S_TCSR_BCE_SHIFT (28U)
1777 #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
1778 #define I2S_TCSR_DBGE_MASK (0x20000000U)
1779 #define I2S_TCSR_DBGE_SHIFT (29U)
1780 #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
1781 #define I2S_TCSR_STOPE_MASK (0x40000000U)
1782 #define I2S_TCSR_STOPE_SHIFT (30U)
1783 #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
1784 #define I2S_TCSR_TE_MASK (0x80000000U)
1785 #define I2S_TCSR_TE_SHIFT (31U)
1786 #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
1788 /*! @name TCR2 - SAI Transmit Configuration 2 Register */
1789 #define I2S_TCR2_DIV_MASK (0xFFU)
1790 #define I2S_TCR2_DIV_SHIFT (0U)
1791 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
1792 #define I2S_TCR2_BCD_MASK (0x1000000U)
1793 #define I2S_TCR2_BCD_SHIFT (24U)
1794 #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
1795 #define I2S_TCR2_BCP_MASK (0x2000000U)
1796 #define I2S_TCR2_BCP_SHIFT (25U)
1797 #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
1798 #define I2S_TCR2_MSEL_MASK (0xC000000U)
1799 #define I2S_TCR2_MSEL_SHIFT (26U)
1800 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
1801 #define I2S_TCR2_BCI_MASK (0x10000000U)
1802 #define I2S_TCR2_BCI_SHIFT (28U)
1803 #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
1804 #define I2S_TCR2_BCS_MASK (0x20000000U)
1805 #define I2S_TCR2_BCS_SHIFT (29U)
1806 #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
1807 #define I2S_TCR2_SYNC_MASK (0xC0000000U)
1808 #define I2S_TCR2_SYNC_SHIFT (30U)
1809 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
1811 /*! @name TCR3 - SAI Transmit Configuration 3 Register */
1812 #define I2S_TCR3_WDFL_MASK (0x1U)
1813 #define I2S_TCR3_WDFL_SHIFT (0U)
1814 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
1815 #define I2S_TCR3_TCE_MASK (0x10000U)
1816 #define I2S_TCR3_TCE_SHIFT (16U)
1817 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
1819 /*! @name TCR4 - SAI Transmit Configuration 4 Register */
1820 #define I2S_TCR4_FSD_MASK (0x1U)
1821 #define I2S_TCR4_FSD_SHIFT (0U)
1822 #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
1823 #define I2S_TCR4_FSP_MASK (0x2U)
1824 #define I2S_TCR4_FSP_SHIFT (1U)
1825 #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
1826 #define I2S_TCR4_FSE_MASK (0x8U)
1827 #define I2S_TCR4_FSE_SHIFT (3U)
1828 #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
1829 #define I2S_TCR4_MF_MASK (0x10U)
1830 #define I2S_TCR4_MF_SHIFT (4U)
1831 #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
1832 #define I2S_TCR4_SYWD_MASK (0x1F00U)
1833 #define I2S_TCR4_SYWD_SHIFT (8U)
1834 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
1835 #define I2S_TCR4_FRSZ_MASK (0x10000U)
1836 #define I2S_TCR4_FRSZ_SHIFT (16U)
1837 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
1839 /*! @name TCR5 - SAI Transmit Configuration 5 Register */
1840 #define I2S_TCR5_FBT_MASK (0x1F00U)
1841 #define I2S_TCR5_FBT_SHIFT (8U)
1842 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
1843 #define I2S_TCR5_W0W_MASK (0x1F0000U)
1844 #define I2S_TCR5_W0W_SHIFT (16U)
1845 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
1846 #define I2S_TCR5_WNW_MASK (0x1F000000U)
1847 #define I2S_TCR5_WNW_SHIFT (24U)
1848 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
1850 /*! @name TDR - SAI Transmit Data Register */
1851 #define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
1852 #define I2S_TDR_TDR_SHIFT (0U)
1853 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
1855 /* The count of I2S_TDR */
1856 #define I2S_TDR_COUNT (1U)
1858 /*! @name TMR - SAI Transmit Mask Register */
1859 #define I2S_TMR_TWM_MASK (0x3U)
1860 #define I2S_TMR_TWM_SHIFT (0U)
1861 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
1863 /*! @name RCSR - SAI Receive Control Register */
1864 #define I2S_RCSR_FWDE_MASK (0x2U)
1865 #define I2S_RCSR_FWDE_SHIFT (1U)
1866 #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
1867 #define I2S_RCSR_FWIE_MASK (0x200U)
1868 #define I2S_RCSR_FWIE_SHIFT (9U)
1869 #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
1870 #define I2S_RCSR_FEIE_MASK (0x400U)
1871 #define I2S_RCSR_FEIE_SHIFT (10U)
1872 #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
1873 #define I2S_RCSR_SEIE_MASK (0x800U)
1874 #define I2S_RCSR_SEIE_SHIFT (11U)
1875 #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
1876 #define I2S_RCSR_WSIE_MASK (0x1000U)
1877 #define I2S_RCSR_WSIE_SHIFT (12U)
1878 #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
1879 #define I2S_RCSR_FWF_MASK (0x20000U)
1880 #define I2S_RCSR_FWF_SHIFT (17U)
1881 #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
1882 #define I2S_RCSR_FEF_MASK (0x40000U)
1883 #define I2S_RCSR_FEF_SHIFT (18U)
1884 #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
1885 #define I2S_RCSR_SEF_MASK (0x80000U)
1886 #define I2S_RCSR_SEF_SHIFT (19U)
1887 #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
1888 #define I2S_RCSR_WSF_MASK (0x100000U)
1889 #define I2S_RCSR_WSF_SHIFT (20U)
1890 #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
1891 #define I2S_RCSR_SR_MASK (0x1000000U)
1892 #define I2S_RCSR_SR_SHIFT (24U)
1893 #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
1894 #define I2S_RCSR_FR_MASK (0x2000000U)
1895 #define I2S_RCSR_FR_SHIFT (25U)
1896 #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
1897 #define I2S_RCSR_BCE_MASK (0x10000000U)
1898 #define I2S_RCSR_BCE_SHIFT (28U)
1899 #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
1900 #define I2S_RCSR_DBGE_MASK (0x20000000U)
1901 #define I2S_RCSR_DBGE_SHIFT (29U)
1902 #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
1903 #define I2S_RCSR_STOPE_MASK (0x40000000U)
1904 #define I2S_RCSR_STOPE_SHIFT (30U)
1905 #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
1906 #define I2S_RCSR_RE_MASK (0x80000000U)
1907 #define I2S_RCSR_RE_SHIFT (31U)
1908 #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
1910 /*! @name RCR2 - SAI Receive Configuration 2 Register */
1911 #define I2S_RCR2_DIV_MASK (0xFFU)
1912 #define I2S_RCR2_DIV_SHIFT (0U)
1913 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
1914 #define I2S_RCR2_BCD_MASK (0x1000000U)
1915 #define I2S_RCR2_BCD_SHIFT (24U)
1916 #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
1917 #define I2S_RCR2_BCP_MASK (0x2000000U)
1918 #define I2S_RCR2_BCP_SHIFT (25U)
1919 #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
1920 #define I2S_RCR2_MSEL_MASK (0xC000000U)
1921 #define I2S_RCR2_MSEL_SHIFT (26U)
1922 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
1923 #define I2S_RCR2_BCI_MASK (0x10000000U)
1924 #define I2S_RCR2_BCI_SHIFT (28U)
1925 #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
1926 #define I2S_RCR2_BCS_MASK (0x20000000U)
1927 #define I2S_RCR2_BCS_SHIFT (29U)
1928 #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
1929 #define I2S_RCR2_SYNC_MASK (0xC0000000U)
1930 #define I2S_RCR2_SYNC_SHIFT (30U)
1931 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
1933 /*! @name RCR3 - SAI Receive Configuration 3 Register */
1934 #define I2S_RCR3_WDFL_MASK (0x1U)
1935 #define I2S_RCR3_WDFL_SHIFT (0U)
1936 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
1937 #define I2S_RCR3_RCE_MASK (0x10000U)
1938 #define I2S_RCR3_RCE_SHIFT (16U)
1939 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
1941 /*! @name RCR4 - SAI Receive Configuration 4 Register */
1942 #define I2S_RCR4_FSD_MASK (0x1U)
1943 #define I2S_RCR4_FSD_SHIFT (0U)
1944 #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
1945 #define I2S_RCR4_FSP_MASK (0x2U)
1946 #define I2S_RCR4_FSP_SHIFT (1U)
1947 #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
1948 #define I2S_RCR4_FSE_MASK (0x8U)
1949 #define I2S_RCR4_FSE_SHIFT (3U)
1950 #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
1951 #define I2S_RCR4_MF_MASK (0x10U)
1952 #define I2S_RCR4_MF_SHIFT (4U)
1953 #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
1954 #define I2S_RCR4_SYWD_MASK (0x1F00U)
1955 #define I2S_RCR4_SYWD_SHIFT (8U)
1956 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
1957 #define I2S_RCR4_FRSZ_MASK (0x10000U)
1958 #define I2S_RCR4_FRSZ_SHIFT (16U)
1959 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
1961 /*! @name RCR5 - SAI Receive Configuration 5 Register */
1962 #define I2S_RCR5_FBT_MASK (0x1F00U)
1963 #define I2S_RCR5_FBT_SHIFT (8U)
1964 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
1965 #define I2S_RCR5_W0W_MASK (0x1F0000U)
1966 #define I2S_RCR5_W0W_SHIFT (16U)
1967 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
1968 #define I2S_RCR5_WNW_MASK (0x1F000000U)
1969 #define I2S_RCR5_WNW_SHIFT (24U)
1970 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
1972 /*! @name RDR - SAI Receive Data Register */
1973 #define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
1974 #define I2S_RDR_RDR_SHIFT (0U)
1975 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
1977 /* The count of I2S_RDR */
1978 #define I2S_RDR_COUNT (1U)
1980 /*! @name RMR - SAI Receive Mask Register */
1981 #define I2S_RMR_RWM_MASK (0x3U)
1982 #define I2S_RMR_RWM_SHIFT (0U)
1983 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
1985 /*! @name MCR - SAI MCLK Control Register */
1986 #define I2S_MCR_MICS_MASK (0x3000000U)
1987 #define I2S_MCR_MICS_SHIFT (24U)
1988 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
1989 #define I2S_MCR_MOE_MASK (0x40000000U)
1990 #define I2S_MCR_MOE_SHIFT (30U)
1991 #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
1992 #define I2S_MCR_DUF_MASK (0x80000000U)
1993 #define I2S_MCR_DUF_SHIFT (31U)
1994 #define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
1996 /*! @name MDR - SAI MCLK Divide Register */
1997 #define I2S_MDR_DIVIDE_MASK (0xFFFU)
1998 #define I2S_MDR_DIVIDE_SHIFT (0U)
1999 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
2000 #define I2S_MDR_FRACT_MASK (0xFF000U)
2001 #define I2S_MDR_FRACT_SHIFT (12U)
2002 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
2007 */ /* end of group I2S_Register_Masks */
2010 /* I2S - Peripheral instance base addresses */
2011 /** Peripheral I2S0 base address */
2012 #define I2S0_BASE (0x4002F000u)
2013 /** Peripheral I2S0 base pointer */
2014 #define I2S0 ((I2S_Type *)I2S0_BASE)
2015 /** Array initializer of I2S peripheral base addresses */
2016 #define I2S_BASE_ADDRS { I2S0_BASE }
2017 /** Array initializer of I2S peripheral base pointers */
2018 #define I2S_BASE_PTRS { I2S0 }
2019 /** Interrupt vectors for the I2S peripheral type */
2020 #define I2S_RX_IRQS { I2S0_IRQn }
2021 #define I2S_TX_IRQS { I2S0_IRQn }
2025 */ /* end of group I2S_Peripheral_Access_Layer */
2028 /* ----------------------------------------------------------------------------
2029 -- LLWU Peripheral Access Layer
2030 ---------------------------------------------------------------------------- */
2033 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
2037 /** LLWU - Register Layout Typedef */
2039 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
2040 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
2041 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
2042 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
2043 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
2044 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
2045 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
2046 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
2047 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
2048 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
2051 /* ----------------------------------------------------------------------------
2052 -- LLWU Register Masks
2053 ---------------------------------------------------------------------------- */
2056 * @addtogroup LLWU_Register_Masks LLWU Register Masks
2060 /*! @name PE1 - LLWU Pin Enable 1 register */
2061 #define LLWU_PE1_WUPE0_MASK (0x3U)
2062 #define LLWU_PE1_WUPE0_SHIFT (0U)
2063 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
2064 #define LLWU_PE1_WUPE1_MASK (0xCU)
2065 #define LLWU_PE1_WUPE1_SHIFT (2U)
2066 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
2067 #define LLWU_PE1_WUPE2_MASK (0x30U)
2068 #define LLWU_PE1_WUPE2_SHIFT (4U)
2069 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
2070 #define LLWU_PE1_WUPE3_MASK (0xC0U)
2071 #define LLWU_PE1_WUPE3_SHIFT (6U)
2072 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
2074 /*! @name PE2 - LLWU Pin Enable 2 register */
2075 #define LLWU_PE2_WUPE4_MASK (0x3U)
2076 #define LLWU_PE2_WUPE4_SHIFT (0U)
2077 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
2078 #define LLWU_PE2_WUPE5_MASK (0xCU)
2079 #define LLWU_PE2_WUPE5_SHIFT (2U)
2080 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
2081 #define LLWU_PE2_WUPE6_MASK (0x30U)
2082 #define LLWU_PE2_WUPE6_SHIFT (4U)
2083 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
2084 #define LLWU_PE2_WUPE7_MASK (0xC0U)
2085 #define LLWU_PE2_WUPE7_SHIFT (6U)
2086 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
2088 /*! @name PE3 - LLWU Pin Enable 3 register */
2089 #define LLWU_PE3_WUPE8_MASK (0x3U)
2090 #define LLWU_PE3_WUPE8_SHIFT (0U)
2091 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
2092 #define LLWU_PE3_WUPE9_MASK (0xCU)
2093 #define LLWU_PE3_WUPE9_SHIFT (2U)
2094 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
2095 #define LLWU_PE3_WUPE10_MASK (0x30U)
2096 #define LLWU_PE3_WUPE10_SHIFT (4U)
2097 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
2098 #define LLWU_PE3_WUPE11_MASK (0xC0U)
2099 #define LLWU_PE3_WUPE11_SHIFT (6U)
2100 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
2102 /*! @name PE4 - LLWU Pin Enable 4 register */
2103 #define LLWU_PE4_WUPE12_MASK (0x3U)
2104 #define LLWU_PE4_WUPE12_SHIFT (0U)
2105 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
2106 #define LLWU_PE4_WUPE13_MASK (0xCU)
2107 #define LLWU_PE4_WUPE13_SHIFT (2U)
2108 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
2109 #define LLWU_PE4_WUPE14_MASK (0x30U)
2110 #define LLWU_PE4_WUPE14_SHIFT (4U)
2111 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
2112 #define LLWU_PE4_WUPE15_MASK (0xC0U)
2113 #define LLWU_PE4_WUPE15_SHIFT (6U)
2114 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
2116 /*! @name ME - LLWU Module Enable register */
2117 #define LLWU_ME_WUME0_MASK (0x1U)
2118 #define LLWU_ME_WUME0_SHIFT (0U)
2119 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
2120 #define LLWU_ME_WUME1_MASK (0x2U)
2121 #define LLWU_ME_WUME1_SHIFT (1U)
2122 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
2123 #define LLWU_ME_WUME2_MASK (0x4U)
2124 #define LLWU_ME_WUME2_SHIFT (2U)
2125 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
2126 #define LLWU_ME_WUME3_MASK (0x8U)
2127 #define LLWU_ME_WUME3_SHIFT (3U)
2128 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
2129 #define LLWU_ME_WUME4_MASK (0x10U)
2130 #define LLWU_ME_WUME4_SHIFT (4U)
2131 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
2132 #define LLWU_ME_WUME5_MASK (0x20U)
2133 #define LLWU_ME_WUME5_SHIFT (5U)
2134 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
2135 #define LLWU_ME_WUME6_MASK (0x40U)
2136 #define LLWU_ME_WUME6_SHIFT (6U)
2137 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
2138 #define LLWU_ME_WUME7_MASK (0x80U)
2139 #define LLWU_ME_WUME7_SHIFT (7U)
2140 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
2142 /*! @name F1 - LLWU Flag 1 register */
2143 #define LLWU_F1_WUF0_MASK (0x1U)
2144 #define LLWU_F1_WUF0_SHIFT (0U)
2145 #define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
2146 #define LLWU_F1_WUF1_MASK (0x2U)
2147 #define LLWU_F1_WUF1_SHIFT (1U)
2148 #define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
2149 #define LLWU_F1_WUF2_MASK (0x4U)
2150 #define LLWU_F1_WUF2_SHIFT (2U)
2151 #define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
2152 #define LLWU_F1_WUF3_MASK (0x8U)
2153 #define LLWU_F1_WUF3_SHIFT (3U)
2154 #define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
2155 #define LLWU_F1_WUF4_MASK (0x10U)
2156 #define LLWU_F1_WUF4_SHIFT (4U)
2157 #define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
2158 #define LLWU_F1_WUF5_MASK (0x20U)
2159 #define LLWU_F1_WUF5_SHIFT (5U)
2160 #define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
2161 #define LLWU_F1_WUF6_MASK (0x40U)
2162 #define LLWU_F1_WUF6_SHIFT (6U)
2163 #define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
2164 #define LLWU_F1_WUF7_MASK (0x80U)
2165 #define LLWU_F1_WUF7_SHIFT (7U)
2166 #define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
2168 /*! @name F2 - LLWU Flag 2 register */
2169 #define LLWU_F2_WUF8_MASK (0x1U)
2170 #define LLWU_F2_WUF8_SHIFT (0U)
2171 #define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
2172 #define LLWU_F2_WUF9_MASK (0x2U)
2173 #define LLWU_F2_WUF9_SHIFT (1U)
2174 #define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
2175 #define LLWU_F2_WUF10_MASK (0x4U)
2176 #define LLWU_F2_WUF10_SHIFT (2U)
2177 #define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
2178 #define LLWU_F2_WUF11_MASK (0x8U)
2179 #define LLWU_F2_WUF11_SHIFT (3U)
2180 #define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
2181 #define LLWU_F2_WUF12_MASK (0x10U)
2182 #define LLWU_F2_WUF12_SHIFT (4U)
2183 #define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
2184 #define LLWU_F2_WUF13_MASK (0x20U)
2185 #define LLWU_F2_WUF13_SHIFT (5U)
2186 #define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
2187 #define LLWU_F2_WUF14_MASK (0x40U)
2188 #define LLWU_F2_WUF14_SHIFT (6U)
2189 #define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
2190 #define LLWU_F2_WUF15_MASK (0x80U)
2191 #define LLWU_F2_WUF15_SHIFT (7U)
2192 #define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
2194 /*! @name F3 - LLWU Flag 3 register */
2195 #define LLWU_F3_MWUF0_MASK (0x1U)
2196 #define LLWU_F3_MWUF0_SHIFT (0U)
2197 #define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
2198 #define LLWU_F3_MWUF1_MASK (0x2U)
2199 #define LLWU_F3_MWUF1_SHIFT (1U)
2200 #define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
2201 #define LLWU_F3_MWUF2_MASK (0x4U)
2202 #define LLWU_F3_MWUF2_SHIFT (2U)
2203 #define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
2204 #define LLWU_F3_MWUF3_MASK (0x8U)
2205 #define LLWU_F3_MWUF3_SHIFT (3U)
2206 #define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
2207 #define LLWU_F3_MWUF4_MASK (0x10U)
2208 #define LLWU_F3_MWUF4_SHIFT (4U)
2209 #define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
2210 #define LLWU_F3_MWUF5_MASK (0x20U)
2211 #define LLWU_F3_MWUF5_SHIFT (5U)
2212 #define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
2213 #define LLWU_F3_MWUF6_MASK (0x40U)
2214 #define LLWU_F3_MWUF6_SHIFT (6U)
2215 #define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
2216 #define LLWU_F3_MWUF7_MASK (0x80U)
2217 #define LLWU_F3_MWUF7_SHIFT (7U)
2218 #define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
2220 /*! @name FILT1 - LLWU Pin Filter 1 register */
2221 #define LLWU_FILT1_FILTSEL_MASK (0xFU)
2222 #define LLWU_FILT1_FILTSEL_SHIFT (0U)
2223 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
2224 #define LLWU_FILT1_FILTE_MASK (0x60U)
2225 #define LLWU_FILT1_FILTE_SHIFT (5U)
2226 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
2227 #define LLWU_FILT1_FILTF_MASK (0x80U)
2228 #define LLWU_FILT1_FILTF_SHIFT (7U)
2229 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
2231 /*! @name FILT2 - LLWU Pin Filter 2 register */
2232 #define LLWU_FILT2_FILTSEL_MASK (0xFU)
2233 #define LLWU_FILT2_FILTSEL_SHIFT (0U)
2234 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
2235 #define LLWU_FILT2_FILTE_MASK (0x60U)
2236 #define LLWU_FILT2_FILTE_SHIFT (5U)
2237 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
2238 #define LLWU_FILT2_FILTF_MASK (0x80U)
2239 #define LLWU_FILT2_FILTF_SHIFT (7U)
2240 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
2245 */ /* end of group LLWU_Register_Masks */
2248 /* LLWU - Peripheral instance base addresses */
2249 /** Peripheral LLWU base address */
2250 #define LLWU_BASE (0x4007C000u)
2251 /** Peripheral LLWU base pointer */
2252 #define LLWU ((LLWU_Type *)LLWU_BASE)
2253 /** Array initializer of LLWU peripheral base addresses */
2254 #define LLWU_BASE_ADDRS { LLWU_BASE }
2255 /** Array initializer of LLWU peripheral base pointers */
2256 #define LLWU_BASE_PTRS { LLWU }
2257 /** Interrupt vectors for the LLWU peripheral type */
2258 #define LLWU_IRQS { LLWU_IRQn }
2262 */ /* end of group LLWU_Peripheral_Access_Layer */
2265 /* ----------------------------------------------------------------------------
2266 -- LPTMR Peripheral Access Layer
2267 ---------------------------------------------------------------------------- */
2270 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
2274 /** LPTMR - Register Layout Typedef */
2276 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
2277 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
2278 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
2279 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
2282 /* ----------------------------------------------------------------------------
2283 -- LPTMR Register Masks
2284 ---------------------------------------------------------------------------- */
2287 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
2291 /*! @name CSR - Low Power Timer Control Status Register */
2292 #define LPTMR_CSR_TEN_MASK (0x1U)
2293 #define LPTMR_CSR_TEN_SHIFT (0U)
2294 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
2295 #define LPTMR_CSR_TMS_MASK (0x2U)
2296 #define LPTMR_CSR_TMS_SHIFT (1U)
2297 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
2298 #define LPTMR_CSR_TFC_MASK (0x4U)
2299 #define LPTMR_CSR_TFC_SHIFT (2U)
2300 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
2301 #define LPTMR_CSR_TPP_MASK (0x8U)
2302 #define LPTMR_CSR_TPP_SHIFT (3U)
2303 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
2304 #define LPTMR_CSR_TPS_MASK (0x30U)
2305 #define LPTMR_CSR_TPS_SHIFT (4U)
2306 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
2307 #define LPTMR_CSR_TIE_MASK (0x40U)
2308 #define LPTMR_CSR_TIE_SHIFT (6U)
2309 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
2310 #define LPTMR_CSR_TCF_MASK (0x80U)
2311 #define LPTMR_CSR_TCF_SHIFT (7U)
2312 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
2314 /*! @name PSR - Low Power Timer Prescale Register */
2315 #define LPTMR_PSR_PCS_MASK (0x3U)
2316 #define LPTMR_PSR_PCS_SHIFT (0U)
2317 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
2318 #define LPTMR_PSR_PBYP_MASK (0x4U)
2319 #define LPTMR_PSR_PBYP_SHIFT (2U)
2320 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
2321 #define LPTMR_PSR_PRESCALE_MASK (0x78U)
2322 #define LPTMR_PSR_PRESCALE_SHIFT (3U)
2323 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
2325 /*! @name CMR - Low Power Timer Compare Register */
2326 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
2327 #define LPTMR_CMR_COMPARE_SHIFT (0U)
2328 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
2330 /*! @name CNR - Low Power Timer Counter Register */
2331 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
2332 #define LPTMR_CNR_COUNTER_SHIFT (0U)
2333 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
2338 */ /* end of group LPTMR_Register_Masks */
2341 /* LPTMR - Peripheral instance base addresses */
2342 /** Peripheral LPTMR0 base address */
2343 #define LPTMR0_BASE (0x40040000u)
2344 /** Peripheral LPTMR0 base pointer */
2345 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
2346 /** Array initializer of LPTMR peripheral base addresses */
2347 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
2348 /** Array initializer of LPTMR peripheral base pointers */
2349 #define LPTMR_BASE_PTRS { LPTMR0 }
2350 /** Interrupt vectors for the LPTMR peripheral type */
2351 #define LPTMR_IRQS { LPTMR0_IRQn }
2355 */ /* end of group LPTMR_Peripheral_Access_Layer */
2358 /* ----------------------------------------------------------------------------
2359 -- MCG Peripheral Access Layer
2360 ---------------------------------------------------------------------------- */
2363 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
2367 /** MCG - Register Layout Typedef */
2369 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
2370 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
2371 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
2372 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
2373 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
2374 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
2375 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
2376 uint8_t RESERVED_0[1];
2377 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
2378 uint8_t RESERVED_1[1];
2379 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
2380 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
2381 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
2382 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
2383 uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
2384 uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
2387 /* ----------------------------------------------------------------------------
2388 -- MCG Register Masks
2389 ---------------------------------------------------------------------------- */
2392 * @addtogroup MCG_Register_Masks MCG Register Masks
2396 /*! @name C1 - MCG Control 1 Register */
2397 #define MCG_C1_IREFSTEN_MASK (0x1U)
2398 #define MCG_C1_IREFSTEN_SHIFT (0U)
2399 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
2400 #define MCG_C1_IRCLKEN_MASK (0x2U)
2401 #define MCG_C1_IRCLKEN_SHIFT (1U)
2402 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
2403 #define MCG_C1_IREFS_MASK (0x4U)
2404 #define MCG_C1_IREFS_SHIFT (2U)
2405 #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
2406 #define MCG_C1_FRDIV_MASK (0x38U)
2407 #define MCG_C1_FRDIV_SHIFT (3U)
2408 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
2409 #define MCG_C1_CLKS_MASK (0xC0U)
2410 #define MCG_C1_CLKS_SHIFT (6U)
2411 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
2413 /*! @name C2 - MCG Control 2 Register */
2414 #define MCG_C2_IRCS_MASK (0x1U)
2415 #define MCG_C2_IRCS_SHIFT (0U)
2416 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
2417 #define MCG_C2_LP_MASK (0x2U)
2418 #define MCG_C2_LP_SHIFT (1U)
2419 #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
2420 #define MCG_C2_EREFS0_MASK (0x4U)
2421 #define MCG_C2_EREFS0_SHIFT (2U)
2422 #define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK)
2423 #define MCG_C2_HGO0_MASK (0x8U)
2424 #define MCG_C2_HGO0_SHIFT (3U)
2425 #define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK)
2426 #define MCG_C2_RANGE0_MASK (0x30U)
2427 #define MCG_C2_RANGE0_SHIFT (4U)
2428 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK)
2429 #define MCG_C2_FCFTRIM_MASK (0x40U)
2430 #define MCG_C2_FCFTRIM_SHIFT (6U)
2431 #define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
2432 #define MCG_C2_LOCRE0_MASK (0x80U)
2433 #define MCG_C2_LOCRE0_SHIFT (7U)
2434 #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
2436 /*! @name C3 - MCG Control 3 Register */
2437 #define MCG_C3_SCTRIM_MASK (0xFFU)
2438 #define MCG_C3_SCTRIM_SHIFT (0U)
2439 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
2441 /*! @name C4 - MCG Control 4 Register */
2442 #define MCG_C4_SCFTRIM_MASK (0x1U)
2443 #define MCG_C4_SCFTRIM_SHIFT (0U)
2444 #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
2445 #define MCG_C4_FCTRIM_MASK (0x1EU)
2446 #define MCG_C4_FCTRIM_SHIFT (1U)
2447 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
2448 #define MCG_C4_DRST_DRS_MASK (0x60U)
2449 #define MCG_C4_DRST_DRS_SHIFT (5U)
2450 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
2451 #define MCG_C4_DMX32_MASK (0x80U)
2452 #define MCG_C4_DMX32_SHIFT (7U)
2453 #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
2455 /*! @name C5 - MCG Control 5 Register */
2456 #define MCG_C5_PRDIV0_MASK (0x1FU)
2457 #define MCG_C5_PRDIV0_SHIFT (0U)
2458 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
2459 #define MCG_C5_PLLSTEN0_MASK (0x20U)
2460 #define MCG_C5_PLLSTEN0_SHIFT (5U)
2461 #define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
2462 #define MCG_C5_PLLCLKEN0_MASK (0x40U)
2463 #define MCG_C5_PLLCLKEN0_SHIFT (6U)
2464 #define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
2466 /*! @name C6 - MCG Control 6 Register */
2467 #define MCG_C6_VDIV0_MASK (0x1FU)
2468 #define MCG_C6_VDIV0_SHIFT (0U)
2469 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
2470 #define MCG_C6_CME0_MASK (0x20U)
2471 #define MCG_C6_CME0_SHIFT (5U)
2472 #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
2473 #define MCG_C6_PLLS_MASK (0x40U)
2474 #define MCG_C6_PLLS_SHIFT (6U)
2475 #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
2476 #define MCG_C6_LOLIE0_MASK (0x80U)
2477 #define MCG_C6_LOLIE0_SHIFT (7U)
2478 #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
2480 /*! @name S - MCG Status Register */
2481 #define MCG_S_IRCST_MASK (0x1U)
2482 #define MCG_S_IRCST_SHIFT (0U)
2483 #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
2484 #define MCG_S_OSCINIT0_MASK (0x2U)
2485 #define MCG_S_OSCINIT0_SHIFT (1U)
2486 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
2487 #define MCG_S_CLKST_MASK (0xCU)
2488 #define MCG_S_CLKST_SHIFT (2U)
2489 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
2490 #define MCG_S_IREFST_MASK (0x10U)
2491 #define MCG_S_IREFST_SHIFT (4U)
2492 #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
2493 #define MCG_S_PLLST_MASK (0x20U)
2494 #define MCG_S_PLLST_SHIFT (5U)
2495 #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
2496 #define MCG_S_LOCK0_MASK (0x40U)
2497 #define MCG_S_LOCK0_SHIFT (6U)
2498 #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
2499 #define MCG_S_LOLS0_MASK (0x80U)
2500 #define MCG_S_LOLS0_SHIFT (7U)
2501 #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
2503 /*! @name SC - MCG Status and Control Register */
2504 #define MCG_SC_LOCS0_MASK (0x1U)
2505 #define MCG_SC_LOCS0_SHIFT (0U)
2506 #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
2507 #define MCG_SC_FCRDIV_MASK (0xEU)
2508 #define MCG_SC_FCRDIV_SHIFT (1U)
2509 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
2510 #define MCG_SC_FLTPRSRV_MASK (0x10U)
2511 #define MCG_SC_FLTPRSRV_SHIFT (4U)
2512 #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
2513 #define MCG_SC_ATMF_MASK (0x20U)
2514 #define MCG_SC_ATMF_SHIFT (5U)
2515 #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
2516 #define MCG_SC_ATMS_MASK (0x40U)
2517 #define MCG_SC_ATMS_SHIFT (6U)
2518 #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
2519 #define MCG_SC_ATME_MASK (0x80U)
2520 #define MCG_SC_ATME_SHIFT (7U)
2521 #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
2523 /*! @name ATCVH - MCG Auto Trim Compare Value High Register */
2524 #define MCG_ATCVH_ATCVH_MASK (0xFFU)
2525 #define MCG_ATCVH_ATCVH_SHIFT (0U)
2526 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
2528 /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
2529 #define MCG_ATCVL_ATCVL_MASK (0xFFU)
2530 #define MCG_ATCVL_ATCVL_SHIFT (0U)
2531 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
2533 /*! @name C7 - MCG Control 7 Register */
2534 #define MCG_C7_OSCSEL_MASK (0x1U)
2535 #define MCG_C7_OSCSEL_SHIFT (0U)
2536 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
2538 /*! @name C8 - MCG Control 8 Register */
2539 #define MCG_C8_LOLRE_MASK (0x40U)
2540 #define MCG_C8_LOLRE_SHIFT (6U)
2541 #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
2546 */ /* end of group MCG_Register_Masks */
2549 /* MCG - Peripheral instance base addresses */
2550 /** Peripheral MCG base address */
2551 #define MCG_BASE (0x40064000u)
2552 /** Peripheral MCG base pointer */
2553 #define MCG ((MCG_Type *)MCG_BASE)
2554 /** Array initializer of MCG peripheral base addresses */
2555 #define MCG_BASE_ADDRS { MCG_BASE }
2556 /** Array initializer of MCG peripheral base pointers */
2557 #define MCG_BASE_PTRS { MCG }
2558 /** Interrupt vectors for the MCG peripheral type */
2559 #define MCG_IRQS { MCG_IRQn }
2560 /* MCG C2[EREFS] backward compatibility */
2561 #define MCG_C2_EREFS_MASK (MCG_C2_EREFS0_MASK)
2562 #define MCG_C2_EREFS_SHIFT (MCG_C2_EREFS0_SHIFT)
2563 #define MCG_C2_EREFS_WIDTH (MCG_C2_EREFS0_WIDTH)
2564 #define MCG_C2_EREFS(x) (MCG_C2_EREFS0(x))
2566 /* MCG C2[HGO] backward compatibility */
2567 #define MCG_C2_HGO_MASK (MCG_C2_HGO0_MASK)
2568 #define MCG_C2_HGO_SHIFT (MCG_C2_HGO0_SHIFT)
2569 #define MCG_C2_HGO_WIDTH (MCG_C2_HGO0_WIDTH)
2570 #define MCG_C2_HGO(x) (MCG_C2_HGO0(x))
2572 /* MCG C2[RANGE] backward compatibility */
2573 #define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK)
2574 #define MCG_C2_RANGE_SHIFT (MCG_C2_RANGE0_SHIFT)
2575 #define MCG_C2_RANGE_WIDTH (MCG_C2_RANGE0_WIDTH)
2576 #define MCG_C2_RANGE(x) (MCG_C2_RANGE0(x))
2581 */ /* end of group MCG_Peripheral_Access_Layer */
2584 /* ----------------------------------------------------------------------------
2585 -- MCM Peripheral Access Layer
2586 ---------------------------------------------------------------------------- */
2589 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
2593 /** MCM - Register Layout Typedef */
2595 uint8_t RESERVED_0[8];
2596 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
2597 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
2598 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
2599 uint8_t RESERVED_1[48];
2600 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
2603 /* ----------------------------------------------------------------------------
2604 -- MCM Register Masks
2605 ---------------------------------------------------------------------------- */
2608 * @addtogroup MCM_Register_Masks MCM Register Masks
2612 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
2613 #define MCM_PLASC_ASC_MASK (0xFFU)
2614 #define MCM_PLASC_ASC_SHIFT (0U)
2615 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
2617 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
2618 #define MCM_PLAMC_AMC_MASK (0xFFU)
2619 #define MCM_PLAMC_AMC_SHIFT (0U)
2620 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
2622 /*! @name PLACR - Platform Control Register */
2623 #define MCM_PLACR_ARB_MASK (0x200U)
2624 #define MCM_PLACR_ARB_SHIFT (9U)
2625 #define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
2626 #define MCM_PLACR_CFCC_MASK (0x400U)
2627 #define MCM_PLACR_CFCC_SHIFT (10U)
2628 #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK)
2629 #define MCM_PLACR_DFCDA_MASK (0x800U)
2630 #define MCM_PLACR_DFCDA_SHIFT (11U)
2631 #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK)
2632 #define MCM_PLACR_DFCIC_MASK (0x1000U)
2633 #define MCM_PLACR_DFCIC_SHIFT (12U)
2634 #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK)
2635 #define MCM_PLACR_DFCC_MASK (0x2000U)
2636 #define MCM_PLACR_DFCC_SHIFT (13U)
2637 #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK)
2638 #define MCM_PLACR_EFDS_MASK (0x4000U)
2639 #define MCM_PLACR_EFDS_SHIFT (14U)
2640 #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
2641 #define MCM_PLACR_DFCS_MASK (0x8000U)
2642 #define MCM_PLACR_DFCS_SHIFT (15U)
2643 #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK)
2644 #define MCM_PLACR_ESFC_MASK (0x10000U)
2645 #define MCM_PLACR_ESFC_SHIFT (16U)
2646 #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK)
2648 /*! @name CPO - Compute Operation Control Register */
2649 #define MCM_CPO_CPOREQ_MASK (0x1U)
2650 #define MCM_CPO_CPOREQ_SHIFT (0U)
2651 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
2652 #define MCM_CPO_CPOACK_MASK (0x2U)
2653 #define MCM_CPO_CPOACK_SHIFT (1U)
2654 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
2655 #define MCM_CPO_CPOWOI_MASK (0x4U)
2656 #define MCM_CPO_CPOWOI_SHIFT (2U)
2657 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
2662 */ /* end of group MCM_Register_Masks */
2665 /* MCM - Peripheral instance base addresses */
2666 /** Peripheral MCM base address */
2667 #define MCM_BASE (0xF0003000u)
2668 /** Peripheral MCM base pointer */
2669 #define MCM ((MCM_Type *)MCM_BASE)
2670 /** Array initializer of MCM peripheral base addresses */
2671 #define MCM_BASE_ADDRS { MCM_BASE }
2672 /** Array initializer of MCM peripheral base pointers */
2673 #define MCM_BASE_PTRS { MCM }
2677 */ /* end of group MCM_Peripheral_Access_Layer */
2680 /* ----------------------------------------------------------------------------
2681 -- MTB Peripheral Access Layer
2682 ---------------------------------------------------------------------------- */
2685 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
2689 /** MTB - Register Layout Typedef */
2691 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
2692 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
2693 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
2694 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
2695 uint8_t RESERVED_0[3824];
2696 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
2697 uint8_t RESERVED_1[156];
2698 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
2699 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
2700 uint8_t RESERVED_2[8];
2701 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
2702 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
2703 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
2704 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
2705 uint8_t RESERVED_3[8];
2706 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
2707 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
2708 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
2709 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
2710 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
2711 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
2712 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
2713 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
2714 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
2715 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
2716 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
2719 /* ----------------------------------------------------------------------------
2720 -- MTB Register Masks
2721 ---------------------------------------------------------------------------- */
2724 * @addtogroup MTB_Register_Masks MTB Register Masks
2728 /*! @name POSITION - MTB Position Register */
2729 #define MTB_POSITION_WRAP_MASK (0x4U)
2730 #define MTB_POSITION_WRAP_SHIFT (2U)
2731 #define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
2732 #define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U)
2733 #define MTB_POSITION_POINTER_SHIFT (3U)
2734 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
2736 /*! @name MASTER - MTB Master Register */
2737 #define MTB_MASTER_MASK_MASK (0x1FU)
2738 #define MTB_MASTER_MASK_SHIFT (0U)
2739 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
2740 #define MTB_MASTER_TSTARTEN_MASK (0x20U)
2741 #define MTB_MASTER_TSTARTEN_SHIFT (5U)
2742 #define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
2743 #define MTB_MASTER_TSTOPEN_MASK (0x40U)
2744 #define MTB_MASTER_TSTOPEN_SHIFT (6U)
2745 #define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
2746 #define MTB_MASTER_SFRWPRIV_MASK (0x80U)
2747 #define MTB_MASTER_SFRWPRIV_SHIFT (7U)
2748 #define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
2749 #define MTB_MASTER_RAMPRIV_MASK (0x100U)
2750 #define MTB_MASTER_RAMPRIV_SHIFT (8U)
2751 #define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
2752 #define MTB_MASTER_HALTREQ_MASK (0x200U)
2753 #define MTB_MASTER_HALTREQ_SHIFT (9U)
2754 #define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
2755 #define MTB_MASTER_EN_MASK (0x80000000U)
2756 #define MTB_MASTER_EN_SHIFT (31U)
2757 #define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
2759 /*! @name FLOW - MTB Flow Register */
2760 #define MTB_FLOW_AUTOSTOP_MASK (0x1U)
2761 #define MTB_FLOW_AUTOSTOP_SHIFT (0U)
2762 #define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
2763 #define MTB_FLOW_AUTOHALT_MASK (0x2U)
2764 #define MTB_FLOW_AUTOHALT_SHIFT (1U)
2765 #define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
2766 #define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U)
2767 #define MTB_FLOW_WATERMARK_SHIFT (3U)
2768 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
2770 /*! @name BASE - MTB Base Register */
2771 #define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU)
2772 #define MTB_BASE_BASEADDR_SHIFT (0U)
2773 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK)
2775 /*! @name MODECTRL - Integration Mode Control Register */
2776 #define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU)
2777 #define MTB_MODECTRL_MODECTRL_SHIFT (0U)
2778 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK)
2780 /*! @name TAGSET - Claim TAG Set Register */
2781 #define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU)
2782 #define MTB_TAGSET_TAGSET_SHIFT (0U)
2783 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK)
2785 /*! @name TAGCLEAR - Claim TAG Clear Register */
2786 #define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU)
2787 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U)
2788 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK)
2790 /*! @name LOCKACCESS - Lock Access Register */
2791 #define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU)
2792 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U)
2793 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK)
2795 /*! @name LOCKSTAT - Lock Status Register */
2796 #define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU)
2797 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U)
2798 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK)
2800 /*! @name AUTHSTAT - Authentication Status Register */
2801 #define MTB_AUTHSTAT_BIT0_MASK (0x1U)
2802 #define MTB_AUTHSTAT_BIT0_SHIFT (0U)
2803 #define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK)
2804 #define MTB_AUTHSTAT_BIT1_MASK (0x2U)
2805 #define MTB_AUTHSTAT_BIT1_SHIFT (1U)
2806 #define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK)
2807 #define MTB_AUTHSTAT_BIT2_MASK (0x4U)
2808 #define MTB_AUTHSTAT_BIT2_SHIFT (2U)
2809 #define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK)
2810 #define MTB_AUTHSTAT_BIT3_MASK (0x8U)
2811 #define MTB_AUTHSTAT_BIT3_SHIFT (3U)
2812 #define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK)
2814 /*! @name DEVICEARCH - Device Architecture Register */
2815 #define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU)
2816 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U)
2817 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK)
2819 /*! @name DEVICECFG - Device Configuration Register */
2820 #define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
2821 #define MTB_DEVICECFG_DEVICECFG_SHIFT (0U)
2822 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK)
2824 /*! @name DEVICETYPID - Device Type Identifier Register */
2825 #define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
2826 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U)
2827 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK)
2829 /*! @name PERIPHID4 - Peripheral ID Register */
2830 #define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
2831 #define MTB_PERIPHID4_PERIPHID_SHIFT (0U)
2832 #define MTB_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK)
2834 /*! @name PERIPHID5 - Peripheral ID Register */
2835 #define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
2836 #define MTB_PERIPHID5_PERIPHID_SHIFT (0U)
2837 #define MTB_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK)
2839 /*! @name PERIPHID6 - Peripheral ID Register */
2840 #define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
2841 #define MTB_PERIPHID6_PERIPHID_SHIFT (0U)
2842 #define MTB_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK)
2844 /*! @name PERIPHID7 - Peripheral ID Register */
2845 #define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
2846 #define MTB_PERIPHID7_PERIPHID_SHIFT (0U)
2847 #define MTB_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK)
2849 /*! @name PERIPHID0 - Peripheral ID Register */
2850 #define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
2851 #define MTB_PERIPHID0_PERIPHID_SHIFT (0U)
2852 #define MTB_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK)
2854 /*! @name PERIPHID1 - Peripheral ID Register */
2855 #define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
2856 #define MTB_PERIPHID1_PERIPHID_SHIFT (0U)
2857 #define MTB_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK)
2859 /*! @name PERIPHID2 - Peripheral ID Register */
2860 #define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
2861 #define MTB_PERIPHID2_PERIPHID_SHIFT (0U)
2862 #define MTB_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK)
2864 /*! @name PERIPHID3 - Peripheral ID Register */
2865 #define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
2866 #define MTB_PERIPHID3_PERIPHID_SHIFT (0U)
2867 #define MTB_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK)
2869 /*! @name COMPID - Component ID Register */
2870 #define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU)
2871 #define MTB_COMPID_COMPID_SHIFT (0U)
2872 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK)
2874 /* The count of MTB_COMPID */
2875 #define MTB_COMPID_COUNT (4U)
2880 */ /* end of group MTB_Register_Masks */
2883 /* MTB - Peripheral instance base addresses */
2884 /** Peripheral MTB base address */
2885 #define MTB_BASE (0xF0000000u)
2886 /** Peripheral MTB base pointer */
2887 #define MTB ((MTB_Type *)MTB_BASE)
2888 /** Array initializer of MTB peripheral base addresses */
2889 #define MTB_BASE_ADDRS { MTB_BASE }
2890 /** Array initializer of MTB peripheral base pointers */
2891 #define MTB_BASE_PTRS { MTB }
2895 */ /* end of group MTB_Peripheral_Access_Layer */
2898 /* ----------------------------------------------------------------------------
2899 -- MTBDWT Peripheral Access Layer
2900 ---------------------------------------------------------------------------- */
2903 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
2907 /** MTBDWT - Register Layout Typedef */
2909 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
2910 uint8_t RESERVED_0[28];
2911 struct { /* offset: 0x20, array step: 0x10 */
2912 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
2913 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
2914 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
2915 uint8_t RESERVED_0[4];
2917 uint8_t RESERVED_1[448];
2918 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
2919 uint8_t RESERVED_2[3524];
2920 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
2921 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
2922 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
2923 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
2924 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
2925 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
2926 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
2927 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
2928 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
2929 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
2930 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
2933 /* ----------------------------------------------------------------------------
2934 -- MTBDWT Register Masks
2935 ---------------------------------------------------------------------------- */
2938 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
2942 /*! @name CTRL - MTB DWT Control Register */
2943 #define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU)
2944 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U)
2945 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK)
2946 #define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U)
2947 #define MTBDWT_CTRL_NUMCMP_SHIFT (28U)
2948 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK)
2950 /*! @name COMP - MTB_DWT Comparator Register */
2951 #define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU)
2952 #define MTBDWT_COMP_COMP_SHIFT (0U)
2953 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK)
2955 /* The count of MTBDWT_COMP */
2956 #define MTBDWT_COMP_COUNT (2U)
2958 /*! @name MASK - MTB_DWT Comparator Mask Register */
2959 #define MTBDWT_MASK_MASK_MASK (0x1FU)
2960 #define MTBDWT_MASK_MASK_SHIFT (0U)
2961 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK)
2963 /* The count of MTBDWT_MASK */
2964 #define MTBDWT_MASK_COUNT (2U)
2966 /*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */
2967 #define MTBDWT_FCT_FUNCTION_MASK (0xFU)
2968 #define MTBDWT_FCT_FUNCTION_SHIFT (0U)
2969 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK)
2970 #define MTBDWT_FCT_DATAVMATCH_MASK (0x100U)
2971 #define MTBDWT_FCT_DATAVMATCH_SHIFT (8U)
2972 #define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK)
2973 #define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U)
2974 #define MTBDWT_FCT_DATAVSIZE_SHIFT (10U)
2975 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK)
2976 #define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U)
2977 #define MTBDWT_FCT_DATAVADDR0_SHIFT (12U)
2978 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK)
2979 #define MTBDWT_FCT_MATCHED_MASK (0x1000000U)
2980 #define MTBDWT_FCT_MATCHED_SHIFT (24U)
2981 #define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK)
2983 /* The count of MTBDWT_FCT */
2984 #define MTBDWT_FCT_COUNT (2U)
2986 /*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */
2987 #define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U)
2988 #define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U)
2989 #define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK)
2990 #define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U)
2991 #define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U)
2992 #define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK)
2993 #define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U)
2994 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U)
2995 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK)
2997 /*! @name DEVICECFG - Device Configuration Register */
2998 #define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
2999 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U)
3000 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK)
3002 /*! @name DEVICETYPID - Device Type Identifier Register */
3003 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
3004 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U)
3005 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
3007 /*! @name PERIPHID4 - Peripheral ID Register */
3008 #define MTBDWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
3009 #define MTBDWT_PERIPHID4_PERIPHID_SHIFT (0U)
3010 #define MTBDWT_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK)
3012 /*! @name PERIPHID5 - Peripheral ID Register */
3013 #define MTBDWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
3014 #define MTBDWT_PERIPHID5_PERIPHID_SHIFT (0U)
3015 #define MTBDWT_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK)
3017 /*! @name PERIPHID6 - Peripheral ID Register */
3018 #define MTBDWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
3019 #define MTBDWT_PERIPHID6_PERIPHID_SHIFT (0U)
3020 #define MTBDWT_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK)
3022 /*! @name PERIPHID7 - Peripheral ID Register */
3023 #define MTBDWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
3024 #define MTBDWT_PERIPHID7_PERIPHID_SHIFT (0U)
3025 #define MTBDWT_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK)
3027 /*! @name PERIPHID0 - Peripheral ID Register */
3028 #define MTBDWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
3029 #define MTBDWT_PERIPHID0_PERIPHID_SHIFT (0U)
3030 #define MTBDWT_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK)
3032 /*! @name PERIPHID1 - Peripheral ID Register */
3033 #define MTBDWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
3034 #define MTBDWT_PERIPHID1_PERIPHID_SHIFT (0U)
3035 #define MTBDWT_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK)
3037 /*! @name PERIPHID2 - Peripheral ID Register */
3038 #define MTBDWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
3039 #define MTBDWT_PERIPHID2_PERIPHID_SHIFT (0U)
3040 #define MTBDWT_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK)
3042 /*! @name PERIPHID3 - Peripheral ID Register */
3043 #define MTBDWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
3044 #define MTBDWT_PERIPHID3_PERIPHID_SHIFT (0U)
3045 #define MTBDWT_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK)
3047 /*! @name COMPID - Component ID Register */
3048 #define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU)
3049 #define MTBDWT_COMPID_COMPID_SHIFT (0U)
3050 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK)
3052 /* The count of MTBDWT_COMPID */
3053 #define MTBDWT_COMPID_COUNT (4U)
3058 */ /* end of group MTBDWT_Register_Masks */
3061 /* MTBDWT - Peripheral instance base addresses */
3062 /** Peripheral MTBDWT base address */
3063 #define MTBDWT_BASE (0xF0001000u)
3064 /** Peripheral MTBDWT base pointer */
3065 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
3066 /** Array initializer of MTBDWT peripheral base addresses */
3067 #define MTBDWT_BASE_ADDRS { MTBDWT_BASE }
3068 /** Array initializer of MTBDWT peripheral base pointers */
3069 #define MTBDWT_BASE_PTRS { MTBDWT }
3073 */ /* end of group MTBDWT_Peripheral_Access_Layer */
3076 /* ----------------------------------------------------------------------------
3077 -- NV Peripheral Access Layer
3078 ---------------------------------------------------------------------------- */
3081 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
3085 /** NV - Register Layout Typedef */
3087 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
3088 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
3089 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
3090 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
3091 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
3092 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
3093 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
3094 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
3095 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
3096 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
3097 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
3098 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
3099 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
3100 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
3103 /* ----------------------------------------------------------------------------
3104 -- NV Register Masks
3105 ---------------------------------------------------------------------------- */
3108 * @addtogroup NV_Register_Masks NV Register Masks
3112 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */
3113 #define NV_BACKKEY3_KEY_MASK (0xFFU)
3114 #define NV_BACKKEY3_KEY_SHIFT (0U)
3115 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
3117 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */
3118 #define NV_BACKKEY2_KEY_MASK (0xFFU)
3119 #define NV_BACKKEY2_KEY_SHIFT (0U)
3120 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
3122 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */
3123 #define NV_BACKKEY1_KEY_MASK (0xFFU)
3124 #define NV_BACKKEY1_KEY_SHIFT (0U)
3125 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
3127 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */
3128 #define NV_BACKKEY0_KEY_MASK (0xFFU)
3129 #define NV_BACKKEY0_KEY_SHIFT (0U)
3130 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
3132 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */
3133 #define NV_BACKKEY7_KEY_MASK (0xFFU)
3134 #define NV_BACKKEY7_KEY_SHIFT (0U)
3135 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
3137 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */
3138 #define NV_BACKKEY6_KEY_MASK (0xFFU)
3139 #define NV_BACKKEY6_KEY_SHIFT (0U)
3140 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
3142 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */
3143 #define NV_BACKKEY5_KEY_MASK (0xFFU)
3144 #define NV_BACKKEY5_KEY_SHIFT (0U)
3145 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
3147 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */
3148 #define NV_BACKKEY4_KEY_MASK (0xFFU)
3149 #define NV_BACKKEY4_KEY_SHIFT (0U)
3150 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
3152 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
3153 #define NV_FPROT3_PROT_MASK (0xFFU)
3154 #define NV_FPROT3_PROT_SHIFT (0U)
3155 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
3157 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
3158 #define NV_FPROT2_PROT_MASK (0xFFU)
3159 #define NV_FPROT2_PROT_SHIFT (0U)
3160 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
3162 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
3163 #define NV_FPROT1_PROT_MASK (0xFFU)
3164 #define NV_FPROT1_PROT_SHIFT (0U)
3165 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
3167 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
3168 #define NV_FPROT0_PROT_MASK (0xFFU)
3169 #define NV_FPROT0_PROT_SHIFT (0U)
3170 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
3172 /*! @name FSEC - Non-volatile Flash Security Register */
3173 #define NV_FSEC_SEC_MASK (0x3U)
3174 #define NV_FSEC_SEC_SHIFT (0U)
3175 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
3176 #define NV_FSEC_FSLACC_MASK (0xCU)
3177 #define NV_FSEC_FSLACC_SHIFT (2U)
3178 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
3179 #define NV_FSEC_MEEN_MASK (0x30U)
3180 #define NV_FSEC_MEEN_SHIFT (4U)
3181 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
3182 #define NV_FSEC_KEYEN_MASK (0xC0U)
3183 #define NV_FSEC_KEYEN_SHIFT (6U)
3184 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
3186 /*! @name FOPT - Non-volatile Flash Option Register */
3187 #define NV_FOPT_LPBOOT0_MASK (0x1U)
3188 #define NV_FOPT_LPBOOT0_SHIFT (0U)
3189 #define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK)
3190 #define NV_FOPT_NMI_DIS_MASK (0x4U)
3191 #define NV_FOPT_NMI_DIS_SHIFT (2U)
3192 #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
3193 #define NV_FOPT_RESET_PIN_CFG_MASK (0x8U)
3194 #define NV_FOPT_RESET_PIN_CFG_SHIFT (3U)
3195 #define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK)
3196 #define NV_FOPT_LPBOOT1_MASK (0x10U)
3197 #define NV_FOPT_LPBOOT1_SHIFT (4U)
3198 #define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK)
3199 #define NV_FOPT_FAST_INIT_MASK (0x20U)
3200 #define NV_FOPT_FAST_INIT_SHIFT (5U)
3201 #define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
3206 */ /* end of group NV_Register_Masks */
3209 /* NV - Peripheral instance base addresses */
3210 /** Peripheral FTFA_FlashConfig base address */
3211 #define FTFA_FlashConfig_BASE (0x400u)
3212 /** Peripheral FTFA_FlashConfig base pointer */
3213 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
3214 /** Array initializer of NV peripheral base addresses */
3215 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
3216 /** Array initializer of NV peripheral base pointers */
3217 #define NV_BASE_PTRS { FTFA_FlashConfig }
3221 */ /* end of group NV_Peripheral_Access_Layer */
3224 /* ----------------------------------------------------------------------------
3225 -- OSC Peripheral Access Layer
3226 ---------------------------------------------------------------------------- */
3229 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
3233 /** OSC - Register Layout Typedef */
3235 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
3238 /* ----------------------------------------------------------------------------
3239 -- OSC Register Masks
3240 ---------------------------------------------------------------------------- */
3243 * @addtogroup OSC_Register_Masks OSC Register Masks
3247 /*! @name CR - OSC Control Register */
3248 #define OSC_CR_SC16P_MASK (0x1U)
3249 #define OSC_CR_SC16P_SHIFT (0U)
3250 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
3251 #define OSC_CR_SC8P_MASK (0x2U)
3252 #define OSC_CR_SC8P_SHIFT (1U)
3253 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
3254 #define OSC_CR_SC4P_MASK (0x4U)
3255 #define OSC_CR_SC4P_SHIFT (2U)
3256 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
3257 #define OSC_CR_SC2P_MASK (0x8U)
3258 #define OSC_CR_SC2P_SHIFT (3U)
3259 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
3260 #define OSC_CR_EREFSTEN_MASK (0x20U)
3261 #define OSC_CR_EREFSTEN_SHIFT (5U)
3262 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
3263 #define OSC_CR_ERCLKEN_MASK (0x80U)
3264 #define OSC_CR_ERCLKEN_SHIFT (7U)
3265 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
3270 */ /* end of group OSC_Register_Masks */
3273 /* OSC - Peripheral instance base addresses */
3274 /** Peripheral OSC0 base address */
3275 #define OSC0_BASE (0x40065000u)
3276 /** Peripheral OSC0 base pointer */
3277 #define OSC0 ((OSC_Type *)OSC0_BASE)
3278 /** Array initializer of OSC peripheral base addresses */
3279 #define OSC_BASE_ADDRS { OSC0_BASE }
3280 /** Array initializer of OSC peripheral base pointers */
3281 #define OSC_BASE_PTRS { OSC0 }
3285 */ /* end of group OSC_Peripheral_Access_Layer */
3288 /* ----------------------------------------------------------------------------
3289 -- PIT Peripheral Access Layer
3290 ---------------------------------------------------------------------------- */
3293 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
3297 /** PIT - Register Layout Typedef */
3299 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
3300 uint8_t RESERVED_0[220];
3301 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
3302 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
3303 uint8_t RESERVED_1[24];
3304 struct { /* offset: 0x100, array step: 0x10 */
3305 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
3306 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
3307 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
3308 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
3312 /* ----------------------------------------------------------------------------
3313 -- PIT Register Masks
3314 ---------------------------------------------------------------------------- */
3317 * @addtogroup PIT_Register_Masks PIT Register Masks
3321 /*! @name MCR - PIT Module Control Register */
3322 #define PIT_MCR_FRZ_MASK (0x1U)
3323 #define PIT_MCR_FRZ_SHIFT (0U)
3324 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
3325 #define PIT_MCR_MDIS_MASK (0x2U)
3326 #define PIT_MCR_MDIS_SHIFT (1U)
3327 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
3329 /*! @name LTMR64H - PIT Upper Lifetime Timer Register */
3330 #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
3331 #define PIT_LTMR64H_LTH_SHIFT (0U)
3332 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
3334 /*! @name LTMR64L - PIT Lower Lifetime Timer Register */
3335 #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
3336 #define PIT_LTMR64L_LTL_SHIFT (0U)
3337 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
3339 /*! @name LDVAL - Timer Load Value Register */
3340 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
3341 #define PIT_LDVAL_TSV_SHIFT (0U)
3342 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
3344 /* The count of PIT_LDVAL */
3345 #define PIT_LDVAL_COUNT (2U)
3347 /*! @name CVAL - Current Timer Value Register */
3348 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
3349 #define PIT_CVAL_TVL_SHIFT (0U)
3350 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
3352 /* The count of PIT_CVAL */
3353 #define PIT_CVAL_COUNT (2U)
3355 /*! @name TCTRL - Timer Control Register */
3356 #define PIT_TCTRL_TEN_MASK (0x1U)
3357 #define PIT_TCTRL_TEN_SHIFT (0U)
3358 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
3359 #define PIT_TCTRL_TIE_MASK (0x2U)
3360 #define PIT_TCTRL_TIE_SHIFT (1U)
3361 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
3362 #define PIT_TCTRL_CHN_MASK (0x4U)
3363 #define PIT_TCTRL_CHN_SHIFT (2U)
3364 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
3366 /* The count of PIT_TCTRL */
3367 #define PIT_TCTRL_COUNT (2U)
3369 /*! @name TFLG - Timer Flag Register */
3370 #define PIT_TFLG_TIF_MASK (0x1U)
3371 #define PIT_TFLG_TIF_SHIFT (0U)
3372 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
3374 /* The count of PIT_TFLG */
3375 #define PIT_TFLG_COUNT (2U)
3380 */ /* end of group PIT_Register_Masks */
3383 /* PIT - Peripheral instance base addresses */
3384 /** Peripheral PIT base address */
3385 #define PIT_BASE (0x40037000u)
3386 /** Peripheral PIT base pointer */
3387 #define PIT ((PIT_Type *)PIT_BASE)
3388 /** Array initializer of PIT peripheral base addresses */
3389 #define PIT_BASE_ADDRS { PIT_BASE }
3390 /** Array initializer of PIT peripheral base pointers */
3391 #define PIT_BASE_PTRS { PIT }
3392 /** Interrupt vectors for the PIT peripheral type */
3393 #define PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }
3397 */ /* end of group PIT_Peripheral_Access_Layer */
3400 /* ----------------------------------------------------------------------------
3401 -- PMC Peripheral Access Layer
3402 ---------------------------------------------------------------------------- */
3405 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
3409 /** PMC - Register Layout Typedef */
3411 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
3412 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
3413 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
3416 /* ----------------------------------------------------------------------------
3417 -- PMC Register Masks
3418 ---------------------------------------------------------------------------- */
3421 * @addtogroup PMC_Register_Masks PMC Register Masks
3425 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
3426 #define PMC_LVDSC1_LVDV_MASK (0x3U)
3427 #define PMC_LVDSC1_LVDV_SHIFT (0U)
3428 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
3429 #define PMC_LVDSC1_LVDRE_MASK (0x10U)
3430 #define PMC_LVDSC1_LVDRE_SHIFT (4U)
3431 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
3432 #define PMC_LVDSC1_LVDIE_MASK (0x20U)
3433 #define PMC_LVDSC1_LVDIE_SHIFT (5U)
3434 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
3435 #define PMC_LVDSC1_LVDACK_MASK (0x40U)
3436 #define PMC_LVDSC1_LVDACK_SHIFT (6U)
3437 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
3438 #define PMC_LVDSC1_LVDF_MASK (0x80U)
3439 #define PMC_LVDSC1_LVDF_SHIFT (7U)
3440 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
3442 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
3443 #define PMC_LVDSC2_LVWV_MASK (0x3U)
3444 #define PMC_LVDSC2_LVWV_SHIFT (0U)
3445 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
3446 #define PMC_LVDSC2_LVWIE_MASK (0x20U)
3447 #define PMC_LVDSC2_LVWIE_SHIFT (5U)
3448 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
3449 #define PMC_LVDSC2_LVWACK_MASK (0x40U)
3450 #define PMC_LVDSC2_LVWACK_SHIFT (6U)
3451 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
3452 #define PMC_LVDSC2_LVWF_MASK (0x80U)
3453 #define PMC_LVDSC2_LVWF_SHIFT (7U)
3454 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
3456 /*! @name REGSC - Regulator Status And Control register */
3457 #define PMC_REGSC_BGBE_MASK (0x1U)
3458 #define PMC_REGSC_BGBE_SHIFT (0U)
3459 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
3460 #define PMC_REGSC_REGONS_MASK (0x4U)
3461 #define PMC_REGSC_REGONS_SHIFT (2U)
3462 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
3463 #define PMC_REGSC_ACKISO_MASK (0x8U)
3464 #define PMC_REGSC_ACKISO_SHIFT (3U)
3465 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
3466 #define PMC_REGSC_BGEN_MASK (0x10U)
3467 #define PMC_REGSC_BGEN_SHIFT (4U)
3468 #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
3473 */ /* end of group PMC_Register_Masks */
3476 /* PMC - Peripheral instance base addresses */
3477 /** Peripheral PMC base address */
3478 #define PMC_BASE (0x4007D000u)
3479 /** Peripheral PMC base pointer */
3480 #define PMC ((PMC_Type *)PMC_BASE)
3481 /** Array initializer of PMC peripheral base addresses */
3482 #define PMC_BASE_ADDRS { PMC_BASE }
3483 /** Array initializer of PMC peripheral base pointers */
3484 #define PMC_BASE_PTRS { PMC }
3485 /** Interrupt vectors for the PMC peripheral type */
3486 #define PMC_IRQS { LVD_LVW_IRQn }
3490 */ /* end of group PMC_Peripheral_Access_Layer */
3493 /* ----------------------------------------------------------------------------
3494 -- PORT Peripheral Access Layer
3495 ---------------------------------------------------------------------------- */
3498 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
3502 /** PORT - Register Layout Typedef */
3504 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
3505 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
3506 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
3507 uint8_t RESERVED_0[24];
3508 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
3511 /* ----------------------------------------------------------------------------
3512 -- PORT Register Masks
3513 ---------------------------------------------------------------------------- */
3516 * @addtogroup PORT_Register_Masks PORT Register Masks
3520 /*! @name PCR - Pin Control Register n */
3521 #define PORT_PCR_PS_MASK (0x1U)
3522 #define PORT_PCR_PS_SHIFT (0U)
3523 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
3524 #define PORT_PCR_PE_MASK (0x2U)
3525 #define PORT_PCR_PE_SHIFT (1U)
3526 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
3527 #define PORT_PCR_SRE_MASK (0x4U)
3528 #define PORT_PCR_SRE_SHIFT (2U)
3529 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
3530 #define PORT_PCR_PFE_MASK (0x10U)
3531 #define PORT_PCR_PFE_SHIFT (4U)
3532 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
3533 #define PORT_PCR_DSE_MASK (0x40U)
3534 #define PORT_PCR_DSE_SHIFT (6U)
3535 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
3536 #define PORT_PCR_MUX_MASK (0x700U)
3537 #define PORT_PCR_MUX_SHIFT (8U)
3538 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
3539 #define PORT_PCR_IRQC_MASK (0xF0000U)
3540 #define PORT_PCR_IRQC_SHIFT (16U)
3541 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
3542 #define PORT_PCR_ISF_MASK (0x1000000U)
3543 #define PORT_PCR_ISF_SHIFT (24U)
3544 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
3546 /* The count of PORT_PCR */
3547 #define PORT_PCR_COUNT (32U)
3549 /*! @name GPCLR - Global Pin Control Low Register */
3550 #define PORT_GPCLR_GPWD_MASK (0xFFFFU)
3551 #define PORT_GPCLR_GPWD_SHIFT (0U)
3552 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
3553 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
3554 #define PORT_GPCLR_GPWE_SHIFT (16U)
3555 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
3557 /*! @name GPCHR - Global Pin Control High Register */
3558 #define PORT_GPCHR_GPWD_MASK (0xFFFFU)
3559 #define PORT_GPCHR_GPWD_SHIFT (0U)
3560 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
3561 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
3562 #define PORT_GPCHR_GPWE_SHIFT (16U)
3563 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
3565 /*! @name ISFR - Interrupt Status Flag Register */
3566 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
3567 #define PORT_ISFR_ISF_SHIFT (0U)
3568 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
3573 */ /* end of group PORT_Register_Masks */
3576 /* PORT - Peripheral instance base addresses */
3577 /** Peripheral PORTA base address */
3578 #define PORTA_BASE (0x40049000u)
3579 /** Peripheral PORTA base pointer */
3580 #define PORTA ((PORT_Type *)PORTA_BASE)
3581 /** Peripheral PORTB base address */
3582 #define PORTB_BASE (0x4004A000u)
3583 /** Peripheral PORTB base pointer */
3584 #define PORTB ((PORT_Type *)PORTB_BASE)
3585 /** Peripheral PORTC base address */
3586 #define PORTC_BASE (0x4004B000u)
3587 /** Peripheral PORTC base pointer */
3588 #define PORTC ((PORT_Type *)PORTC_BASE)
3589 /** Peripheral PORTD base address */
3590 #define PORTD_BASE (0x4004C000u)
3591 /** Peripheral PORTD base pointer */
3592 #define PORTD ((PORT_Type *)PORTD_BASE)
3593 /** Peripheral PORTE base address */
3594 #define PORTE_BASE (0x4004D000u)
3595 /** Peripheral PORTE base pointer */
3596 #define PORTE ((PORT_Type *)PORTE_BASE)
3597 /** Array initializer of PORT peripheral base addresses */
3598 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
3599 /** Array initializer of PORT peripheral base pointers */
3600 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
3601 /** Interrupt vectors for the PORT peripheral type */
3602 #define PORT_IRQS { PORTA_IRQn, NotAvail_IRQn, PORTC_PORTD_IRQn, PORTC_PORTD_IRQn, NotAvail_IRQn }
3606 */ /* end of group PORT_Peripheral_Access_Layer */
3609 /* ----------------------------------------------------------------------------
3610 -- RCM Peripheral Access Layer
3611 ---------------------------------------------------------------------------- */
3614 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
3618 /** RCM - Register Layout Typedef */
3620 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
3621 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
3622 uint8_t RESERVED_0[2];
3623 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
3624 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
3627 /* ----------------------------------------------------------------------------
3628 -- RCM Register Masks
3629 ---------------------------------------------------------------------------- */
3632 * @addtogroup RCM_Register_Masks RCM Register Masks
3636 /*! @name SRS0 - System Reset Status Register 0 */
3637 #define RCM_SRS0_WAKEUP_MASK (0x1U)
3638 #define RCM_SRS0_WAKEUP_SHIFT (0U)
3639 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
3640 #define RCM_SRS0_LVD_MASK (0x2U)
3641 #define RCM_SRS0_LVD_SHIFT (1U)
3642 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
3643 #define RCM_SRS0_LOC_MASK (0x4U)
3644 #define RCM_SRS0_LOC_SHIFT (2U)
3645 #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
3646 #define RCM_SRS0_LOL_MASK (0x8U)
3647 #define RCM_SRS0_LOL_SHIFT (3U)
3648 #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
3649 #define RCM_SRS0_WDOG_MASK (0x20U)
3650 #define RCM_SRS0_WDOG_SHIFT (5U)
3651 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
3652 #define RCM_SRS0_PIN_MASK (0x40U)
3653 #define RCM_SRS0_PIN_SHIFT (6U)
3654 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
3655 #define RCM_SRS0_POR_MASK (0x80U)
3656 #define RCM_SRS0_POR_SHIFT (7U)
3657 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
3659 /*! @name SRS1 - System Reset Status Register 1 */
3660 #define RCM_SRS1_LOCKUP_MASK (0x2U)
3661 #define RCM_SRS1_LOCKUP_SHIFT (1U)
3662 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
3663 #define RCM_SRS1_SW_MASK (0x4U)
3664 #define RCM_SRS1_SW_SHIFT (2U)
3665 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
3666 #define RCM_SRS1_MDM_AP_MASK (0x8U)
3667 #define RCM_SRS1_MDM_AP_SHIFT (3U)
3668 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
3669 #define RCM_SRS1_SACKERR_MASK (0x20U)
3670 #define RCM_SRS1_SACKERR_SHIFT (5U)
3671 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
3673 /*! @name RPFC - Reset Pin Filter Control register */
3674 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
3675 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
3676 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
3677 #define RCM_RPFC_RSTFLTSS_MASK (0x4U)
3678 #define RCM_RPFC_RSTFLTSS_SHIFT (2U)
3679 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
3681 /*! @name RPFW - Reset Pin Filter Width register */
3682 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
3683 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
3684 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
3689 */ /* end of group RCM_Register_Masks */
3692 /* RCM - Peripheral instance base addresses */
3693 /** Peripheral RCM base address */
3694 #define RCM_BASE (0x4007F000u)
3695 /** Peripheral RCM base pointer */
3696 #define RCM ((RCM_Type *)RCM_BASE)
3697 /** Array initializer of RCM peripheral base addresses */
3698 #define RCM_BASE_ADDRS { RCM_BASE }
3699 /** Array initializer of RCM peripheral base pointers */
3700 #define RCM_BASE_PTRS { RCM }
3704 */ /* end of group RCM_Peripheral_Access_Layer */
3707 /* ----------------------------------------------------------------------------
3708 -- ROM Peripheral Access Layer
3709 ---------------------------------------------------------------------------- */
3712 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
3716 /** ROM - Register Layout Typedef */
3718 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
3719 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
3720 uint8_t RESERVED_0[4028];
3721 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
3722 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
3723 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
3724 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
3725 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
3726 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
3727 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
3728 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
3729 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
3730 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
3733 /* ----------------------------------------------------------------------------
3734 -- ROM Register Masks
3735 ---------------------------------------------------------------------------- */
3738 * @addtogroup ROM_Register_Masks ROM Register Masks
3742 /*! @name ENTRY - Entry */
3743 #define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU)
3744 #define ROM_ENTRY_ENTRY_SHIFT (0U)
3745 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK)
3747 /* The count of ROM_ENTRY */
3748 #define ROM_ENTRY_COUNT (3U)
3750 /*! @name TABLEMARK - End of Table Marker Register */
3751 #define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU)
3752 #define ROM_TABLEMARK_MARK_SHIFT (0U)
3753 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK)
3755 /*! @name SYSACCESS - System Access Register */
3756 #define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU)
3757 #define ROM_SYSACCESS_SYSACCESS_SHIFT (0U)
3758 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK)
3760 /*! @name PERIPHID4 - Peripheral ID Register */
3761 #define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
3762 #define ROM_PERIPHID4_PERIPHID_SHIFT (0U)
3763 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK)
3765 /*! @name PERIPHID5 - Peripheral ID Register */
3766 #define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
3767 #define ROM_PERIPHID5_PERIPHID_SHIFT (0U)
3768 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK)
3770 /*! @name PERIPHID6 - Peripheral ID Register */
3771 #define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
3772 #define ROM_PERIPHID6_PERIPHID_SHIFT (0U)
3773 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK)
3775 /*! @name PERIPHID7 - Peripheral ID Register */
3776 #define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
3777 #define ROM_PERIPHID7_PERIPHID_SHIFT (0U)
3778 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK)
3780 /*! @name PERIPHID0 - Peripheral ID Register */
3781 #define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
3782 #define ROM_PERIPHID0_PERIPHID_SHIFT (0U)
3783 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK)
3785 /*! @name PERIPHID1 - Peripheral ID Register */
3786 #define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
3787 #define ROM_PERIPHID1_PERIPHID_SHIFT (0U)
3788 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK)
3790 /*! @name PERIPHID2 - Peripheral ID Register */
3791 #define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
3792 #define ROM_PERIPHID2_PERIPHID_SHIFT (0U)
3793 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK)
3795 /*! @name PERIPHID3 - Peripheral ID Register */
3796 #define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
3797 #define ROM_PERIPHID3_PERIPHID_SHIFT (0U)
3798 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK)
3800 /*! @name COMPID - Component ID Register */
3801 #define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU)
3802 #define ROM_COMPID_COMPID_SHIFT (0U)
3803 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK)
3805 /* The count of ROM_COMPID */
3806 #define ROM_COMPID_COUNT (4U)
3811 */ /* end of group ROM_Register_Masks */
3814 /* ROM - Peripheral instance base addresses */
3815 /** Peripheral ROM base address */
3816 #define ROM_BASE (0xF0002000u)
3817 /** Peripheral ROM base pointer */
3818 #define ROM ((ROM_Type *)ROM_BASE)
3819 /** Array initializer of ROM peripheral base addresses */
3820 #define ROM_BASE_ADDRS { ROM_BASE }
3821 /** Array initializer of ROM peripheral base pointers */
3822 #define ROM_BASE_PTRS { ROM }
3826 */ /* end of group ROM_Peripheral_Access_Layer */
3829 /* ----------------------------------------------------------------------------
3830 -- RTC Peripheral Access Layer
3831 ---------------------------------------------------------------------------- */
3834 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
3838 /** RTC - Register Layout Typedef */
3840 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
3841 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
3842 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
3843 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
3844 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
3845 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
3846 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
3847 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
3850 /* ----------------------------------------------------------------------------
3851 -- RTC Register Masks
3852 ---------------------------------------------------------------------------- */
3855 * @addtogroup RTC_Register_Masks RTC Register Masks
3859 /*! @name TSR - RTC Time Seconds Register */
3860 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
3861 #define RTC_TSR_TSR_SHIFT (0U)
3862 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
3864 /*! @name TPR - RTC Time Prescaler Register */
3865 #define RTC_TPR_TPR_MASK (0xFFFFU)
3866 #define RTC_TPR_TPR_SHIFT (0U)
3867 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
3869 /*! @name TAR - RTC Time Alarm Register */
3870 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
3871 #define RTC_TAR_TAR_SHIFT (0U)
3872 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
3874 /*! @name TCR - RTC Time Compensation Register */
3875 #define RTC_TCR_TCR_MASK (0xFFU)
3876 #define RTC_TCR_TCR_SHIFT (0U)
3877 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
3878 #define RTC_TCR_CIR_MASK (0xFF00U)
3879 #define RTC_TCR_CIR_SHIFT (8U)
3880 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
3881 #define RTC_TCR_TCV_MASK (0xFF0000U)
3882 #define RTC_TCR_TCV_SHIFT (16U)
3883 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
3884 #define RTC_TCR_CIC_MASK (0xFF000000U)
3885 #define RTC_TCR_CIC_SHIFT (24U)
3886 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
3888 /*! @name CR - RTC Control Register */
3889 #define RTC_CR_SWR_MASK (0x1U)
3890 #define RTC_CR_SWR_SHIFT (0U)
3891 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
3892 #define RTC_CR_WPE_MASK (0x2U)
3893 #define RTC_CR_WPE_SHIFT (1U)
3894 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
3895 #define RTC_CR_SUP_MASK (0x4U)
3896 #define RTC_CR_SUP_SHIFT (2U)
3897 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
3898 #define RTC_CR_UM_MASK (0x8U)
3899 #define RTC_CR_UM_SHIFT (3U)
3900 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
3901 #define RTC_CR_WPS_MASK (0x10U)
3902 #define RTC_CR_WPS_SHIFT (4U)
3903 #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
3904 #define RTC_CR_OSCE_MASK (0x100U)
3905 #define RTC_CR_OSCE_SHIFT (8U)
3906 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
3907 #define RTC_CR_CLKO_MASK (0x200U)
3908 #define RTC_CR_CLKO_SHIFT (9U)
3909 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
3910 #define RTC_CR_SC16P_MASK (0x400U)
3911 #define RTC_CR_SC16P_SHIFT (10U)
3912 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
3913 #define RTC_CR_SC8P_MASK (0x800U)
3914 #define RTC_CR_SC8P_SHIFT (11U)
3915 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
3916 #define RTC_CR_SC4P_MASK (0x1000U)
3917 #define RTC_CR_SC4P_SHIFT (12U)
3918 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
3919 #define RTC_CR_SC2P_MASK (0x2000U)
3920 #define RTC_CR_SC2P_SHIFT (13U)
3921 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
3923 /*! @name SR - RTC Status Register */
3924 #define RTC_SR_TIF_MASK (0x1U)
3925 #define RTC_SR_TIF_SHIFT (0U)
3926 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
3927 #define RTC_SR_TOF_MASK (0x2U)
3928 #define RTC_SR_TOF_SHIFT (1U)
3929 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
3930 #define RTC_SR_TAF_MASK (0x4U)
3931 #define RTC_SR_TAF_SHIFT (2U)
3932 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
3933 #define RTC_SR_TCE_MASK (0x10U)
3934 #define RTC_SR_TCE_SHIFT (4U)
3935 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
3937 /*! @name LR - RTC Lock Register */
3938 #define RTC_LR_TCL_MASK (0x8U)
3939 #define RTC_LR_TCL_SHIFT (3U)
3940 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
3941 #define RTC_LR_CRL_MASK (0x10U)
3942 #define RTC_LR_CRL_SHIFT (4U)
3943 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
3944 #define RTC_LR_SRL_MASK (0x20U)
3945 #define RTC_LR_SRL_SHIFT (5U)
3946 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
3947 #define RTC_LR_LRL_MASK (0x40U)
3948 #define RTC_LR_LRL_SHIFT (6U)
3949 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
3951 /*! @name IER - RTC Interrupt Enable Register */
3952 #define RTC_IER_TIIE_MASK (0x1U)
3953 #define RTC_IER_TIIE_SHIFT (0U)
3954 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
3955 #define RTC_IER_TOIE_MASK (0x2U)
3956 #define RTC_IER_TOIE_SHIFT (1U)
3957 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
3958 #define RTC_IER_TAIE_MASK (0x4U)
3959 #define RTC_IER_TAIE_SHIFT (2U)
3960 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
3961 #define RTC_IER_TSIE_MASK (0x10U)
3962 #define RTC_IER_TSIE_SHIFT (4U)
3963 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
3964 #define RTC_IER_WPON_MASK (0x80U)
3965 #define RTC_IER_WPON_SHIFT (7U)
3966 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
3971 */ /* end of group RTC_Register_Masks */
3974 /* RTC - Peripheral instance base addresses */
3975 /** Peripheral RTC base address */
3976 #define RTC_BASE (0x4003D000u)
3977 /** Peripheral RTC base pointer */
3978 #define RTC ((RTC_Type *)RTC_BASE)
3979 /** Array initializer of RTC peripheral base addresses */
3980 #define RTC_BASE_ADDRS { RTC_BASE }
3981 /** Array initializer of RTC peripheral base pointers */
3982 #define RTC_BASE_PTRS { RTC }
3983 /** Interrupt vectors for the RTC peripheral type */
3984 #define RTC_IRQS { RTC_IRQn }
3985 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
3989 */ /* end of group RTC_Peripheral_Access_Layer */
3992 /* ----------------------------------------------------------------------------
3993 -- SIM Peripheral Access Layer
3994 ---------------------------------------------------------------------------- */
3997 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
4001 /** SIM - Register Layout Typedef */
4003 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
4004 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
4005 uint8_t RESERVED_0[4092];
4006 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
4007 uint8_t RESERVED_1[4];
4008 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
4009 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
4010 uint8_t RESERVED_2[4];
4011 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
4012 uint8_t RESERVED_3[8];
4013 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
4014 uint8_t RESERVED_4[12];
4015 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
4016 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
4017 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
4018 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
4019 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
4020 uint8_t RESERVED_5[4];
4021 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
4022 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
4023 uint8_t RESERVED_6[4];
4024 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
4025 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
4026 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
4027 uint8_t RESERVED_7[156];
4028 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
4029 __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */
4032 /* ----------------------------------------------------------------------------
4033 -- SIM Register Masks
4034 ---------------------------------------------------------------------------- */
4037 * @addtogroup SIM_Register_Masks SIM Register Masks
4041 /*! @name SOPT1 - System Options Register 1 */
4042 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
4043 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
4044 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
4045 #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
4046 #define SIM_SOPT1_USBVSTBY_SHIFT (29U)
4047 #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
4048 #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
4049 #define SIM_SOPT1_USBSSTBY_SHIFT (30U)
4050 #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
4051 #define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
4052 #define SIM_SOPT1_USBREGEN_SHIFT (31U)
4053 #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
4055 /*! @name SOPT1CFG - SOPT1 Configuration Register */
4056 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
4057 #define SIM_SOPT1CFG_URWE_SHIFT (24U)
4058 #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
4059 #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
4060 #define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
4061 #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
4062 #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
4063 #define SIM_SOPT1CFG_USSWE_SHIFT (26U)
4064 #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
4066 /*! @name SOPT2 - System Options Register 2 */
4067 #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
4068 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
4069 #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
4070 #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
4071 #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
4072 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
4073 #define SIM_SOPT2_PLLFLLSEL_MASK (0x10000U)
4074 #define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
4075 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
4076 #define SIM_SOPT2_USBSRC_MASK (0x40000U)
4077 #define SIM_SOPT2_USBSRC_SHIFT (18U)
4078 #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
4079 #define SIM_SOPT2_TPMSRC_MASK (0x3000000U)
4080 #define SIM_SOPT2_TPMSRC_SHIFT (24U)
4081 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
4082 #define SIM_SOPT2_UART0SRC_MASK (0xC000000U)
4083 #define SIM_SOPT2_UART0SRC_SHIFT (26U)
4084 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_UART0SRC_SHIFT)) & SIM_SOPT2_UART0SRC_MASK)
4086 /*! @name SOPT4 - System Options Register 4 */
4087 #define SIM_SOPT4_TPM1CH0SRC_MASK (0xC0000U)
4088 #define SIM_SOPT4_TPM1CH0SRC_SHIFT (18U)
4089 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CH0SRC_SHIFT)) & SIM_SOPT4_TPM1CH0SRC_MASK)
4090 #define SIM_SOPT4_TPM2CH0SRC_MASK (0x100000U)
4091 #define SIM_SOPT4_TPM2CH0SRC_SHIFT (20U)
4092 #define SIM_SOPT4_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CH0SRC_SHIFT)) & SIM_SOPT4_TPM2CH0SRC_MASK)
4093 #define SIM_SOPT4_TPM0CLKSEL_MASK (0x1000000U)
4094 #define SIM_SOPT4_TPM0CLKSEL_SHIFT (24U)
4095 #define SIM_SOPT4_TPM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM0CLKSEL_SHIFT)) & SIM_SOPT4_TPM0CLKSEL_MASK)
4096 #define SIM_SOPT4_TPM1CLKSEL_MASK (0x2000000U)
4097 #define SIM_SOPT4_TPM1CLKSEL_SHIFT (25U)
4098 #define SIM_SOPT4_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CLKSEL_SHIFT)) & SIM_SOPT4_TPM1CLKSEL_MASK)
4099 #define SIM_SOPT4_TPM2CLKSEL_MASK (0x4000000U)
4100 #define SIM_SOPT4_TPM2CLKSEL_SHIFT (26U)
4101 #define SIM_SOPT4_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CLKSEL_SHIFT)) & SIM_SOPT4_TPM2CLKSEL_MASK)
4103 /*! @name SOPT5 - System Options Register 5 */
4104 #define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
4105 #define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
4106 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
4107 #define SIM_SOPT5_UART0RXSRC_MASK (0x4U)
4108 #define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
4109 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
4110 #define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
4111 #define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
4112 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
4113 #define SIM_SOPT5_UART1RXSRC_MASK (0x40U)
4114 #define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
4115 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
4116 #define SIM_SOPT5_UART0ODE_MASK (0x10000U)
4117 #define SIM_SOPT5_UART0ODE_SHIFT (16U)
4118 #define SIM_SOPT5_UART0ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0ODE_SHIFT)) & SIM_SOPT5_UART0ODE_MASK)
4119 #define SIM_SOPT5_UART1ODE_MASK (0x20000U)
4120 #define SIM_SOPT5_UART1ODE_SHIFT (17U)
4121 #define SIM_SOPT5_UART1ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1ODE_SHIFT)) & SIM_SOPT5_UART1ODE_MASK)
4122 #define SIM_SOPT5_UART2ODE_MASK (0x40000U)
4123 #define SIM_SOPT5_UART2ODE_SHIFT (18U)
4124 #define SIM_SOPT5_UART2ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART2ODE_SHIFT)) & SIM_SOPT5_UART2ODE_MASK)
4126 /*! @name SOPT7 - System Options Register 7 */
4127 #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
4128 #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
4129 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
4130 #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
4131 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
4132 #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
4133 #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
4134 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
4135 #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
4137 /*! @name SDID - System Device Identification Register */
4138 #define SIM_SDID_PINID_MASK (0xFU)
4139 #define SIM_SDID_PINID_SHIFT (0U)
4140 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
4141 #define SIM_SDID_DIEID_MASK (0xF80U)
4142 #define SIM_SDID_DIEID_SHIFT (7U)
4143 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
4144 #define SIM_SDID_REVID_MASK (0xF000U)
4145 #define SIM_SDID_REVID_SHIFT (12U)
4146 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
4147 #define SIM_SDID_SRAMSIZE_MASK (0xF0000U)
4148 #define SIM_SDID_SRAMSIZE_SHIFT (16U)
4149 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK)
4150 #define SIM_SDID_SERIESID_MASK (0xF00000U)
4151 #define SIM_SDID_SERIESID_SHIFT (20U)
4152 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
4153 #define SIM_SDID_SUBFAMID_MASK (0xF000000U)
4154 #define SIM_SDID_SUBFAMID_SHIFT (24U)
4155 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
4156 #define SIM_SDID_FAMID_MASK (0xF0000000U)
4157 #define SIM_SDID_FAMID_SHIFT (28U)
4158 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
4160 /*! @name SCGC4 - System Clock Gating Control Register 4 */
4161 #define SIM_SCGC4_I2C0_MASK (0x40U)
4162 #define SIM_SCGC4_I2C0_SHIFT (6U)
4163 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
4164 #define SIM_SCGC4_I2C1_MASK (0x80U)
4165 #define SIM_SCGC4_I2C1_SHIFT (7U)
4166 #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
4167 #define SIM_SCGC4_UART0_MASK (0x400U)
4168 #define SIM_SCGC4_UART0_SHIFT (10U)
4169 #define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
4170 #define SIM_SCGC4_UART1_MASK (0x800U)
4171 #define SIM_SCGC4_UART1_SHIFT (11U)
4172 #define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
4173 #define SIM_SCGC4_UART2_MASK (0x1000U)
4174 #define SIM_SCGC4_UART2_SHIFT (12U)
4175 #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
4176 #define SIM_SCGC4_USBOTG_MASK (0x40000U)
4177 #define SIM_SCGC4_USBOTG_SHIFT (18U)
4178 #define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
4179 #define SIM_SCGC4_CMP_MASK (0x80000U)
4180 #define SIM_SCGC4_CMP_SHIFT (19U)
4181 #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
4182 #define SIM_SCGC4_SPI0_MASK (0x400000U)
4183 #define SIM_SCGC4_SPI0_SHIFT (22U)
4184 #define SIM_SCGC4_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI0_SHIFT)) & SIM_SCGC4_SPI0_MASK)
4185 #define SIM_SCGC4_SPI1_MASK (0x800000U)
4186 #define SIM_SCGC4_SPI1_SHIFT (23U)
4187 #define SIM_SCGC4_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI1_SHIFT)) & SIM_SCGC4_SPI1_MASK)
4189 /*! @name SCGC5 - System Clock Gating Control Register 5 */
4190 #define SIM_SCGC5_LPTMR_MASK (0x1U)
4191 #define SIM_SCGC5_LPTMR_SHIFT (0U)
4192 #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
4193 #define SIM_SCGC5_TSI_MASK (0x20U)
4194 #define SIM_SCGC5_TSI_SHIFT (5U)
4195 #define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
4196 #define SIM_SCGC5_PORTA_MASK (0x200U)
4197 #define SIM_SCGC5_PORTA_SHIFT (9U)
4198 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
4199 #define SIM_SCGC5_PORTB_MASK (0x400U)
4200 #define SIM_SCGC5_PORTB_SHIFT (10U)
4201 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
4202 #define SIM_SCGC5_PORTC_MASK (0x800U)
4203 #define SIM_SCGC5_PORTC_SHIFT (11U)
4204 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
4205 #define SIM_SCGC5_PORTD_MASK (0x1000U)
4206 #define SIM_SCGC5_PORTD_SHIFT (12U)
4207 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
4208 #define SIM_SCGC5_PORTE_MASK (0x2000U)
4209 #define SIM_SCGC5_PORTE_SHIFT (13U)
4210 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
4212 /*! @name SCGC6 - System Clock Gating Control Register 6 */
4213 #define SIM_SCGC6_FTF_MASK (0x1U)
4214 #define SIM_SCGC6_FTF_SHIFT (0U)
4215 #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
4216 #define SIM_SCGC6_DMAMUX_MASK (0x2U)
4217 #define SIM_SCGC6_DMAMUX_SHIFT (1U)
4218 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
4219 #define SIM_SCGC6_I2S_MASK (0x8000U)
4220 #define SIM_SCGC6_I2S_SHIFT (15U)
4221 #define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
4222 #define SIM_SCGC6_PIT_MASK (0x800000U)
4223 #define SIM_SCGC6_PIT_SHIFT (23U)
4224 #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
4225 #define SIM_SCGC6_TPM0_MASK (0x1000000U)
4226 #define SIM_SCGC6_TPM0_SHIFT (24U)
4227 #define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK)
4228 #define SIM_SCGC6_TPM1_MASK (0x2000000U)
4229 #define SIM_SCGC6_TPM1_SHIFT (25U)
4230 #define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK)
4231 #define SIM_SCGC6_TPM2_MASK (0x4000000U)
4232 #define SIM_SCGC6_TPM2_SHIFT (26U)
4233 #define SIM_SCGC6_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK)
4234 #define SIM_SCGC6_ADC0_MASK (0x8000000U)
4235 #define SIM_SCGC6_ADC0_SHIFT (27U)
4236 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
4237 #define SIM_SCGC6_RTC_MASK (0x20000000U)
4238 #define SIM_SCGC6_RTC_SHIFT (29U)
4239 #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
4240 #define SIM_SCGC6_DAC0_MASK (0x80000000U)
4241 #define SIM_SCGC6_DAC0_SHIFT (31U)
4242 #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
4244 /*! @name SCGC7 - System Clock Gating Control Register 7 */
4245 #define SIM_SCGC7_DMA_MASK (0x100U)
4246 #define SIM_SCGC7_DMA_SHIFT (8U)
4247 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
4249 /*! @name CLKDIV1 - System Clock Divider Register 1 */
4250 #define SIM_CLKDIV1_OUTDIV4_MASK (0x70000U)
4251 #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
4252 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
4253 #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
4254 #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
4255 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
4257 /*! @name FCFG1 - Flash Configuration Register 1 */
4258 #define SIM_FCFG1_FLASHDIS_MASK (0x1U)
4259 #define SIM_FCFG1_FLASHDIS_SHIFT (0U)
4260 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
4261 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
4262 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
4263 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
4264 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
4265 #define SIM_FCFG1_PFSIZE_SHIFT (24U)
4266 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
4268 /*! @name FCFG2 - Flash Configuration Register 2 */
4269 #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
4270 #define SIM_FCFG2_MAXADDR1_SHIFT (16U)
4271 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
4272 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
4273 #define SIM_FCFG2_MAXADDR0_SHIFT (24U)
4274 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
4276 /*! @name UIDMH - Unique Identification Register Mid-High */
4277 #define SIM_UIDMH_UID_MASK (0xFFFFU)
4278 #define SIM_UIDMH_UID_SHIFT (0U)
4279 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
4281 /*! @name UIDML - Unique Identification Register Mid Low */
4282 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
4283 #define SIM_UIDML_UID_SHIFT (0U)
4284 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
4286 /*! @name UIDL - Unique Identification Register Low */
4287 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
4288 #define SIM_UIDL_UID_SHIFT (0U)
4289 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
4291 /*! @name COPC - COP Control Register */
4292 #define SIM_COPC_COPW_MASK (0x1U)
4293 #define SIM_COPC_COPW_SHIFT (0U)
4294 #define SIM_COPC_COPW(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPW_SHIFT)) & SIM_COPC_COPW_MASK)
4295 #define SIM_COPC_COPCLKS_MASK (0x2U)
4296 #define SIM_COPC_COPCLKS_SHIFT (1U)
4297 #define SIM_COPC_COPCLKS(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKS_SHIFT)) & SIM_COPC_COPCLKS_MASK)
4298 #define SIM_COPC_COPT_MASK (0xCU)
4299 #define SIM_COPC_COPT_SHIFT (2U)
4300 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPT_SHIFT)) & SIM_COPC_COPT_MASK)
4302 /*! @name SRVCOP - Service COP */
4303 #define SIM_SRVCOP_SRVCOP_MASK (0xFFU)
4304 #define SIM_SRVCOP_SRVCOP_SHIFT (0U)
4305 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRVCOP_SRVCOP_SHIFT)) & SIM_SRVCOP_SRVCOP_MASK)
4310 */ /* end of group SIM_Register_Masks */
4313 /* SIM - Peripheral instance base addresses */
4314 /** Peripheral SIM base address */
4315 #define SIM_BASE (0x40047000u)
4316 /** Peripheral SIM base pointer */
4317 #define SIM ((SIM_Type *)SIM_BASE)
4318 /** Array initializer of SIM peripheral base addresses */
4319 #define SIM_BASE_ADDRS { SIM_BASE }
4320 /** Array initializer of SIM peripheral base pointers */
4321 #define SIM_BASE_PTRS { SIM }
4325 */ /* end of group SIM_Peripheral_Access_Layer */
4328 /* ----------------------------------------------------------------------------
4329 -- SMC Peripheral Access Layer
4330 ---------------------------------------------------------------------------- */
4333 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
4337 /** SMC - Register Layout Typedef */
4339 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
4340 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
4341 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
4342 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
4345 /* ----------------------------------------------------------------------------
4346 -- SMC Register Masks
4347 ---------------------------------------------------------------------------- */
4350 * @addtogroup SMC_Register_Masks SMC Register Masks
4354 /*! @name PMPROT - Power Mode Protection register */
4355 #define SMC_PMPROT_AVLLS_MASK (0x2U)
4356 #define SMC_PMPROT_AVLLS_SHIFT (1U)
4357 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
4358 #define SMC_PMPROT_ALLS_MASK (0x8U)
4359 #define SMC_PMPROT_ALLS_SHIFT (3U)
4360 #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
4361 #define SMC_PMPROT_AVLP_MASK (0x20U)
4362 #define SMC_PMPROT_AVLP_SHIFT (5U)
4363 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
4365 /*! @name PMCTRL - Power Mode Control register */
4366 #define SMC_PMCTRL_STOPM_MASK (0x7U)
4367 #define SMC_PMCTRL_STOPM_SHIFT (0U)
4368 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
4369 #define SMC_PMCTRL_STOPA_MASK (0x8U)
4370 #define SMC_PMCTRL_STOPA_SHIFT (3U)
4371 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
4372 #define SMC_PMCTRL_RUNM_MASK (0x60U)
4373 #define SMC_PMCTRL_RUNM_SHIFT (5U)
4374 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
4376 /*! @name STOPCTRL - Stop Control Register */
4377 #define SMC_STOPCTRL_VLLSM_MASK (0x7U)
4378 #define SMC_STOPCTRL_VLLSM_SHIFT (0U)
4379 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_VLLSM_SHIFT)) & SMC_STOPCTRL_VLLSM_MASK)
4380 #define SMC_STOPCTRL_PORPO_MASK (0x20U)
4381 #define SMC_STOPCTRL_PORPO_SHIFT (5U)
4382 #define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
4383 #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
4384 #define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
4385 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
4387 /*! @name PMSTAT - Power Mode Status register */
4388 #define SMC_PMSTAT_PMSTAT_MASK (0x7FU)
4389 #define SMC_PMSTAT_PMSTAT_SHIFT (0U)
4390 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
4395 */ /* end of group SMC_Register_Masks */
4398 /* SMC - Peripheral instance base addresses */
4399 /** Peripheral SMC base address */
4400 #define SMC_BASE (0x4007E000u)
4401 /** Peripheral SMC base pointer */
4402 #define SMC ((SMC_Type *)SMC_BASE)
4403 /** Array initializer of SMC peripheral base addresses */
4404 #define SMC_BASE_ADDRS { SMC_BASE }
4405 /** Array initializer of SMC peripheral base pointers */
4406 #define SMC_BASE_PTRS { SMC }
4410 */ /* end of group SMC_Peripheral_Access_Layer */
4413 /* ----------------------------------------------------------------------------
4414 -- SPI Peripheral Access Layer
4415 ---------------------------------------------------------------------------- */
4418 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
4422 /** SPI - Register Layout Typedef */
4424 __IO uint8_t S; /**< SPI Status Register, offset: 0x0 */
4425 __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */
4426 __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */
4427 __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */
4428 __IO uint8_t ML; /**< SPI Match Register low, offset: 0x4 */
4429 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
4430 __IO uint8_t DL; /**< SPI Data Register low, offset: 0x6 */
4431 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
4432 uint8_t RESERVED_0[2];
4433 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
4434 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
4437 /* ----------------------------------------------------------------------------
4438 -- SPI Register Masks
4439 ---------------------------------------------------------------------------- */
4442 * @addtogroup SPI_Register_Masks SPI Register Masks
4446 /*! @name S - SPI Status Register */
4447 #define SPI_S_RFIFOEF_MASK (0x1U)
4448 #define SPI_S_RFIFOEF_SHIFT (0U)
4449 #define SPI_S_RFIFOEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RFIFOEF_SHIFT)) & SPI_S_RFIFOEF_MASK)
4450 #define SPI_S_TXFULLF_MASK (0x2U)
4451 #define SPI_S_TXFULLF_SHIFT (1U)
4452 #define SPI_S_TXFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TXFULLF_SHIFT)) & SPI_S_TXFULLF_MASK)
4453 #define SPI_S_TNEAREF_MASK (0x4U)
4454 #define SPI_S_TNEAREF_SHIFT (2U)
4455 #define SPI_S_TNEAREF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TNEAREF_SHIFT)) & SPI_S_TNEAREF_MASK)
4456 #define SPI_S_RNFULLF_MASK (0x8U)
4457 #define SPI_S_RNFULLF_SHIFT (3U)
4458 #define SPI_S_RNFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RNFULLF_SHIFT)) & SPI_S_RNFULLF_MASK)
4459 #define SPI_S_MODF_MASK (0x10U)
4460 #define SPI_S_MODF_SHIFT (4U)
4461 #define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK)
4462 #define SPI_S_SPTEF_MASK (0x20U)
4463 #define SPI_S_SPTEF_SHIFT (5U)
4464 #define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK)
4465 #define SPI_S_SPMF_MASK (0x40U)
4466 #define SPI_S_SPMF_SHIFT (6U)
4467 #define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK)
4468 #define SPI_S_SPRF_MASK (0x80U)
4469 #define SPI_S_SPRF_SHIFT (7U)
4470 #define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK)
4472 /*! @name BR - SPI Baud Rate Register */
4473 #define SPI_BR_SPR_MASK (0xFU)
4474 #define SPI_BR_SPR_SHIFT (0U)
4475 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK)
4476 #define SPI_BR_SPPR_MASK (0x70U)
4477 #define SPI_BR_SPPR_SHIFT (4U)
4478 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK)
4480 /*! @name C2 - SPI Control Register 2 */
4481 #define SPI_C2_SPC0_MASK (0x1U)
4482 #define SPI_C2_SPC0_SHIFT (0U)
4483 #define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK)
4484 #define SPI_C2_SPISWAI_MASK (0x2U)
4485 #define SPI_C2_SPISWAI_SHIFT (1U)
4486 #define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK)
4487 #define SPI_C2_RXDMAE_MASK (0x4U)
4488 #define SPI_C2_RXDMAE_SHIFT (2U)
4489 #define SPI_C2_RXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_RXDMAE_SHIFT)) & SPI_C2_RXDMAE_MASK)
4490 #define SPI_C2_BIDIROE_MASK (0x8U)
4491 #define SPI_C2_BIDIROE_SHIFT (3U)
4492 #define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK)
4493 #define SPI_C2_MODFEN_MASK (0x10U)
4494 #define SPI_C2_MODFEN_SHIFT (4U)
4495 #define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK)
4496 #define SPI_C2_TXDMAE_MASK (0x20U)
4497 #define SPI_C2_TXDMAE_SHIFT (5U)
4498 #define SPI_C2_TXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_TXDMAE_SHIFT)) & SPI_C2_TXDMAE_MASK)
4499 #define SPI_C2_SPIMODE_MASK (0x40U)
4500 #define SPI_C2_SPIMODE_SHIFT (6U)
4501 #define SPI_C2_SPIMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPIMODE_SHIFT)) & SPI_C2_SPIMODE_MASK)
4502 #define SPI_C2_SPMIE_MASK (0x80U)
4503 #define SPI_C2_SPMIE_SHIFT (7U)
4504 #define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK)
4506 /*! @name C1 - SPI Control Register 1 */
4507 #define SPI_C1_LSBFE_MASK (0x1U)
4508 #define SPI_C1_LSBFE_SHIFT (0U)
4509 #define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK)
4510 #define SPI_C1_SSOE_MASK (0x2U)
4511 #define SPI_C1_SSOE_SHIFT (1U)
4512 #define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK)
4513 #define SPI_C1_CPHA_MASK (0x4U)
4514 #define SPI_C1_CPHA_SHIFT (2U)
4515 #define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK)
4516 #define SPI_C1_CPOL_MASK (0x8U)
4517 #define SPI_C1_CPOL_SHIFT (3U)
4518 #define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK)
4519 #define SPI_C1_MSTR_MASK (0x10U)
4520 #define SPI_C1_MSTR_SHIFT (4U)
4521 #define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK)
4522 #define SPI_C1_SPTIE_MASK (0x20U)
4523 #define SPI_C1_SPTIE_SHIFT (5U)
4524 #define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK)
4525 #define SPI_C1_SPE_MASK (0x40U)
4526 #define SPI_C1_SPE_SHIFT (6U)
4527 #define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK)
4528 #define SPI_C1_SPIE_MASK (0x80U)
4529 #define SPI_C1_SPIE_SHIFT (7U)
4530 #define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK)
4532 /*! @name ML - SPI Match Register low */
4533 #define SPI_ML_Bits_MASK (0xFFU)
4534 #define SPI_ML_Bits_SHIFT (0U)
4535 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_ML_Bits_SHIFT)) & SPI_ML_Bits_MASK)
4537 /*! @name MH - SPI match register high */
4538 #define SPI_MH_Bits_MASK (0xFFU)
4539 #define SPI_MH_Bits_SHIFT (0U)
4540 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_MH_Bits_SHIFT)) & SPI_MH_Bits_MASK)
4542 /*! @name DL - SPI Data Register low */
4543 #define SPI_DL_Bits_MASK (0xFFU)
4544 #define SPI_DL_Bits_SHIFT (0U)
4545 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DL_Bits_SHIFT)) & SPI_DL_Bits_MASK)
4547 /*! @name DH - SPI data register high */
4548 #define SPI_DH_Bits_MASK (0xFFU)
4549 #define SPI_DH_Bits_SHIFT (0U)
4550 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DH_Bits_SHIFT)) & SPI_DH_Bits_MASK)
4552 /*! @name CI - SPI clear interrupt register */
4553 #define SPI_CI_SPRFCI_MASK (0x1U)
4554 #define SPI_CI_SPRFCI_SHIFT (0U)
4555 #define SPI_CI_SPRFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPRFCI_SHIFT)) & SPI_CI_SPRFCI_MASK)
4556 #define SPI_CI_SPTEFCI_MASK (0x2U)
4557 #define SPI_CI_SPTEFCI_SHIFT (1U)
4558 #define SPI_CI_SPTEFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPTEFCI_SHIFT)) & SPI_CI_SPTEFCI_MASK)
4559 #define SPI_CI_RNFULLFCI_MASK (0x4U)
4560 #define SPI_CI_RNFULLFCI_SHIFT (2U)
4561 #define SPI_CI_RNFULLFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RNFULLFCI_SHIFT)) & SPI_CI_RNFULLFCI_MASK)
4562 #define SPI_CI_TNEAREFCI_MASK (0x8U)
4563 #define SPI_CI_TNEAREFCI_SHIFT (3U)
4564 #define SPI_CI_TNEAREFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TNEAREFCI_SHIFT)) & SPI_CI_TNEAREFCI_MASK)
4565 #define SPI_CI_RXFOF_MASK (0x10U)
4566 #define SPI_CI_RXFOF_SHIFT (4U)
4567 #define SPI_CI_RXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFOF_SHIFT)) & SPI_CI_RXFOF_MASK)
4568 #define SPI_CI_TXFOF_MASK (0x20U)
4569 #define SPI_CI_TXFOF_SHIFT (5U)
4570 #define SPI_CI_TXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFOF_SHIFT)) & SPI_CI_TXFOF_MASK)
4571 #define SPI_CI_RXFERR_MASK (0x40U)
4572 #define SPI_CI_RXFERR_SHIFT (6U)
4573 #define SPI_CI_RXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFERR_SHIFT)) & SPI_CI_RXFERR_MASK)
4574 #define SPI_CI_TXFERR_MASK (0x80U)
4575 #define SPI_CI_TXFERR_SHIFT (7U)
4576 #define SPI_CI_TXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFERR_SHIFT)) & SPI_CI_TXFERR_MASK)
4578 /*! @name C3 - SPI control register 3 */
4579 #define SPI_C3_FIFOMODE_MASK (0x1U)
4580 #define SPI_C3_FIFOMODE_SHIFT (0U)
4581 #define SPI_C3_FIFOMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_FIFOMODE_SHIFT)) & SPI_C3_FIFOMODE_MASK)
4582 #define SPI_C3_RNFULLIEN_MASK (0x2U)
4583 #define SPI_C3_RNFULLIEN_SHIFT (1U)
4584 #define SPI_C3_RNFULLIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLIEN_SHIFT)) & SPI_C3_RNFULLIEN_MASK)
4585 #define SPI_C3_TNEARIEN_MASK (0x4U)
4586 #define SPI_C3_TNEARIEN_SHIFT (2U)
4587 #define SPI_C3_TNEARIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEARIEN_SHIFT)) & SPI_C3_TNEARIEN_MASK)
4588 #define SPI_C3_INTCLR_MASK (0x8U)
4589 #define SPI_C3_INTCLR_SHIFT (3U)
4590 #define SPI_C3_INTCLR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_INTCLR_SHIFT)) & SPI_C3_INTCLR_MASK)
4591 #define SPI_C3_RNFULLF_MARK_MASK (0x10U)
4592 #define SPI_C3_RNFULLF_MARK_SHIFT (4U)
4593 #define SPI_C3_RNFULLF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLF_MARK_SHIFT)) & SPI_C3_RNFULLF_MARK_MASK)
4594 #define SPI_C3_TNEAREF_MARK_MASK (0x20U)
4595 #define SPI_C3_TNEAREF_MARK_SHIFT (5U)
4596 #define SPI_C3_TNEAREF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEAREF_MARK_SHIFT)) & SPI_C3_TNEAREF_MARK_MASK)
4601 */ /* end of group SPI_Register_Masks */
4604 /* SPI - Peripheral instance base addresses */
4605 /** Peripheral SPI0 base address */
4606 #define SPI0_BASE (0x40076000u)
4607 /** Peripheral SPI0 base pointer */
4608 #define SPI0 ((SPI_Type *)SPI0_BASE)
4609 /** Peripheral SPI1 base address */
4610 #define SPI1_BASE (0x40077000u)
4611 /** Peripheral SPI1 base pointer */
4612 #define SPI1 ((SPI_Type *)SPI1_BASE)
4613 /** Array initializer of SPI peripheral base addresses */
4614 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
4615 /** Array initializer of SPI peripheral base pointers */
4616 #define SPI_BASE_PTRS { SPI0, SPI1 }
4617 /** Interrupt vectors for the SPI peripheral type */
4618 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
4622 */ /* end of group SPI_Peripheral_Access_Layer */
4625 /* ----------------------------------------------------------------------------
4626 -- TPM Peripheral Access Layer
4627 ---------------------------------------------------------------------------- */
4630 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
4634 /** TPM - Register Layout Typedef */
4636 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
4637 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
4638 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
4639 struct { /* offset: 0xC, array step: 0x8 */
4640 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
4641 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
4643 uint8_t RESERVED_0[20];
4644 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
4645 uint8_t RESERVED_1[48];
4646 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
4649 /* ----------------------------------------------------------------------------
4650 -- TPM Register Masks
4651 ---------------------------------------------------------------------------- */
4654 * @addtogroup TPM_Register_Masks TPM Register Masks
4658 /*! @name SC - Status and Control */
4659 #define TPM_SC_PS_MASK (0x7U)
4660 #define TPM_SC_PS_SHIFT (0U)
4661 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
4662 #define TPM_SC_CMOD_MASK (0x18U)
4663 #define TPM_SC_CMOD_SHIFT (3U)
4664 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
4665 #define TPM_SC_CPWMS_MASK (0x20U)
4666 #define TPM_SC_CPWMS_SHIFT (5U)
4667 #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
4668 #define TPM_SC_TOIE_MASK (0x40U)
4669 #define TPM_SC_TOIE_SHIFT (6U)
4670 #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
4671 #define TPM_SC_TOF_MASK (0x80U)
4672 #define TPM_SC_TOF_SHIFT (7U)
4673 #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
4674 #define TPM_SC_DMA_MASK (0x100U)
4675 #define TPM_SC_DMA_SHIFT (8U)
4676 #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
4678 /*! @name CNT - Counter */
4679 #define TPM_CNT_COUNT_MASK (0xFFFFU)
4680 #define TPM_CNT_COUNT_SHIFT (0U)
4681 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
4683 /*! @name MOD - Modulo */
4684 #define TPM_MOD_MOD_MASK (0xFFFFU)
4685 #define TPM_MOD_MOD_SHIFT (0U)
4686 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
4688 /*! @name CnSC - Channel (n) Status and Control */
4689 #define TPM_CnSC_DMA_MASK (0x1U)
4690 #define TPM_CnSC_DMA_SHIFT (0U)
4691 #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
4692 #define TPM_CnSC_ELSA_MASK (0x4U)
4693 #define TPM_CnSC_ELSA_SHIFT (2U)
4694 #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
4695 #define TPM_CnSC_ELSB_MASK (0x8U)
4696 #define TPM_CnSC_ELSB_SHIFT (3U)
4697 #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
4698 #define TPM_CnSC_MSA_MASK (0x10U)
4699 #define TPM_CnSC_MSA_SHIFT (4U)
4700 #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
4701 #define TPM_CnSC_MSB_MASK (0x20U)
4702 #define TPM_CnSC_MSB_SHIFT (5U)
4703 #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
4704 #define TPM_CnSC_CHIE_MASK (0x40U)
4705 #define TPM_CnSC_CHIE_SHIFT (6U)
4706 #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
4707 #define TPM_CnSC_CHF_MASK (0x80U)
4708 #define TPM_CnSC_CHF_SHIFT (7U)
4709 #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
4711 /* The count of TPM_CnSC */
4712 #define TPM_CnSC_COUNT (6U)
4714 /*! @name CnV - Channel (n) Value */
4715 #define TPM_CnV_VAL_MASK (0xFFFFU)
4716 #define TPM_CnV_VAL_SHIFT (0U)
4717 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
4719 /* The count of TPM_CnV */
4720 #define TPM_CnV_COUNT (6U)
4722 /*! @name STATUS - Capture and Compare Status */
4723 #define TPM_STATUS_CH0F_MASK (0x1U)
4724 #define TPM_STATUS_CH0F_SHIFT (0U)
4725 #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
4726 #define TPM_STATUS_CH1F_MASK (0x2U)
4727 #define TPM_STATUS_CH1F_SHIFT (1U)
4728 #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
4729 #define TPM_STATUS_CH2F_MASK (0x4U)
4730 #define TPM_STATUS_CH2F_SHIFT (2U)
4731 #define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
4732 #define TPM_STATUS_CH3F_MASK (0x8U)
4733 #define TPM_STATUS_CH3F_SHIFT (3U)
4734 #define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
4735 #define TPM_STATUS_CH4F_MASK (0x10U)
4736 #define TPM_STATUS_CH4F_SHIFT (4U)
4737 #define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK)
4738 #define TPM_STATUS_CH5F_MASK (0x20U)
4739 #define TPM_STATUS_CH5F_SHIFT (5U)
4740 #define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK)
4741 #define TPM_STATUS_TOF_MASK (0x100U)
4742 #define TPM_STATUS_TOF_SHIFT (8U)
4743 #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
4745 /*! @name CONF - Configuration */
4746 #define TPM_CONF_DOZEEN_MASK (0x20U)
4747 #define TPM_CONF_DOZEEN_SHIFT (5U)
4748 #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
4749 #define TPM_CONF_DBGMODE_MASK (0xC0U)
4750 #define TPM_CONF_DBGMODE_SHIFT (6U)
4751 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
4752 #define TPM_CONF_GTBEEN_MASK (0x200U)
4753 #define TPM_CONF_GTBEEN_SHIFT (9U)
4754 #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
4755 #define TPM_CONF_CSOT_MASK (0x10000U)
4756 #define TPM_CONF_CSOT_SHIFT (16U)
4757 #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
4758 #define TPM_CONF_CSOO_MASK (0x20000U)
4759 #define TPM_CONF_CSOO_SHIFT (17U)
4760 #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
4761 #define TPM_CONF_CROT_MASK (0x40000U)
4762 #define TPM_CONF_CROT_SHIFT (18U)
4763 #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
4764 #define TPM_CONF_TRGSEL_MASK (0xF000000U)
4765 #define TPM_CONF_TRGSEL_SHIFT (24U)
4766 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
4771 */ /* end of group TPM_Register_Masks */
4774 /* TPM - Peripheral instance base addresses */
4775 /** Peripheral TPM0 base address */
4776 #define TPM0_BASE (0x40038000u)
4777 /** Peripheral TPM0 base pointer */
4778 #define TPM0 ((TPM_Type *)TPM0_BASE)
4779 /** Peripheral TPM1 base address */
4780 #define TPM1_BASE (0x40039000u)
4781 /** Peripheral TPM1 base pointer */
4782 #define TPM1 ((TPM_Type *)TPM1_BASE)
4783 /** Peripheral TPM2 base address */
4784 #define TPM2_BASE (0x4003A000u)
4785 /** Peripheral TPM2 base pointer */
4786 #define TPM2 ((TPM_Type *)TPM2_BASE)
4787 /** Array initializer of TPM peripheral base addresses */
4788 #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE }
4789 /** Array initializer of TPM peripheral base pointers */
4790 #define TPM_BASE_PTRS { TPM0, TPM1, TPM2 }
4791 /** Interrupt vectors for the TPM peripheral type */
4792 #define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
4796 */ /* end of group TPM_Peripheral_Access_Layer */
4799 /* ----------------------------------------------------------------------------
4800 -- TSI Peripheral Access Layer
4801 ---------------------------------------------------------------------------- */
4804 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
4808 /** TSI - Register Layout Typedef */
4810 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
4811 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
4812 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
4815 /* ----------------------------------------------------------------------------
4816 -- TSI Register Masks
4817 ---------------------------------------------------------------------------- */
4820 * @addtogroup TSI_Register_Masks TSI Register Masks
4824 /*! @name GENCS - TSI General Control and Status Register */
4825 #define TSI_GENCS_CURSW_MASK (0x2U)
4826 #define TSI_GENCS_CURSW_SHIFT (1U)
4827 #define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
4828 #define TSI_GENCS_EOSF_MASK (0x4U)
4829 #define TSI_GENCS_EOSF_SHIFT (2U)
4830 #define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
4831 #define TSI_GENCS_SCNIP_MASK (0x8U)
4832 #define TSI_GENCS_SCNIP_SHIFT (3U)
4833 #define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
4834 #define TSI_GENCS_STM_MASK (0x10U)
4835 #define TSI_GENCS_STM_SHIFT (4U)
4836 #define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
4837 #define TSI_GENCS_STPE_MASK (0x20U)
4838 #define TSI_GENCS_STPE_SHIFT (5U)
4839 #define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
4840 #define TSI_GENCS_TSIIEN_MASK (0x40U)
4841 #define TSI_GENCS_TSIIEN_SHIFT (6U)
4842 #define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
4843 #define TSI_GENCS_TSIEN_MASK (0x80U)
4844 #define TSI_GENCS_TSIEN_SHIFT (7U)
4845 #define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
4846 #define TSI_GENCS_NSCN_MASK (0x1F00U)
4847 #define TSI_GENCS_NSCN_SHIFT (8U)
4848 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
4849 #define TSI_GENCS_PS_MASK (0xE000U)
4850 #define TSI_GENCS_PS_SHIFT (13U)
4851 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
4852 #define TSI_GENCS_EXTCHRG_MASK (0x70000U)
4853 #define TSI_GENCS_EXTCHRG_SHIFT (16U)
4854 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
4855 #define TSI_GENCS_DVOLT_MASK (0x180000U)
4856 #define TSI_GENCS_DVOLT_SHIFT (19U)
4857 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
4858 #define TSI_GENCS_REFCHRG_MASK (0xE00000U)
4859 #define TSI_GENCS_REFCHRG_SHIFT (21U)
4860 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
4861 #define TSI_GENCS_MODE_MASK (0xF000000U)
4862 #define TSI_GENCS_MODE_SHIFT (24U)
4863 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
4864 #define TSI_GENCS_ESOR_MASK (0x10000000U)
4865 #define TSI_GENCS_ESOR_SHIFT (28U)
4866 #define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
4867 #define TSI_GENCS_OUTRGF_MASK (0x80000000U)
4868 #define TSI_GENCS_OUTRGF_SHIFT (31U)
4869 #define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
4871 /*! @name DATA - TSI DATA Register */
4872 #define TSI_DATA_TSICNT_MASK (0xFFFFU)
4873 #define TSI_DATA_TSICNT_SHIFT (0U)
4874 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
4875 #define TSI_DATA_SWTS_MASK (0x400000U)
4876 #define TSI_DATA_SWTS_SHIFT (22U)
4877 #define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
4878 #define TSI_DATA_DMAEN_MASK (0x800000U)
4879 #define TSI_DATA_DMAEN_SHIFT (23U)
4880 #define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
4881 #define TSI_DATA_TSICH_MASK (0xF0000000U)
4882 #define TSI_DATA_TSICH_SHIFT (28U)
4883 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
4885 /*! @name TSHD - TSI Threshold Register */
4886 #define TSI_TSHD_THRESL_MASK (0xFFFFU)
4887 #define TSI_TSHD_THRESL_SHIFT (0U)
4888 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
4889 #define TSI_TSHD_THRESH_MASK (0xFFFF0000U)
4890 #define TSI_TSHD_THRESH_SHIFT (16U)
4891 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
4896 */ /* end of group TSI_Register_Masks */
4899 /* TSI - Peripheral instance base addresses */
4900 /** Peripheral TSI0 base address */
4901 #define TSI0_BASE (0x40045000u)
4902 /** Peripheral TSI0 base pointer */
4903 #define TSI0 ((TSI_Type *)TSI0_BASE)
4904 /** Array initializer of TSI peripheral base addresses */
4905 #define TSI_BASE_ADDRS { TSI0_BASE }
4906 /** Array initializer of TSI peripheral base pointers */
4907 #define TSI_BASE_PTRS { TSI0 }
4908 /** Interrupt vectors for the TSI peripheral type */
4909 #define TSI_IRQS { TSI0_IRQn }
4913 */ /* end of group TSI_Peripheral_Access_Layer */
4916 /* ----------------------------------------------------------------------------
4917 -- UART Peripheral Access Layer
4918 ---------------------------------------------------------------------------- */
4921 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
4925 /** UART - Register Layout Typedef */
4927 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
4928 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
4929 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
4930 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
4931 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
4932 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
4933 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
4934 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
4935 __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
4938 /* ----------------------------------------------------------------------------
4939 -- UART Register Masks
4940 ---------------------------------------------------------------------------- */
4943 * @addtogroup UART_Register_Masks UART Register Masks
4947 /*! @name BDH - UART Baud Rate Register: High */
4948 #define UART_BDH_SBR_MASK (0x1FU)
4949 #define UART_BDH_SBR_SHIFT (0U)
4950 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
4951 #define UART_BDH_SBNS_MASK (0x20U)
4952 #define UART_BDH_SBNS_SHIFT (5U)
4953 #define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK)
4954 #define UART_BDH_RXEDGIE_MASK (0x40U)
4955 #define UART_BDH_RXEDGIE_SHIFT (6U)
4956 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
4957 #define UART_BDH_LBKDIE_MASK (0x80U)
4958 #define UART_BDH_LBKDIE_SHIFT (7U)
4959 #define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
4961 /*! @name BDL - UART Baud Rate Register: Low */
4962 #define UART_BDL_SBR_MASK (0xFFU)
4963 #define UART_BDL_SBR_SHIFT (0U)
4964 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
4966 /*! @name C1 - UART Control Register 1 */
4967 #define UART_C1_PT_MASK (0x1U)
4968 #define UART_C1_PT_SHIFT (0U)
4969 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
4970 #define UART_C1_PE_MASK (0x2U)
4971 #define UART_C1_PE_SHIFT (1U)
4972 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
4973 #define UART_C1_ILT_MASK (0x4U)
4974 #define UART_C1_ILT_SHIFT (2U)
4975 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
4976 #define UART_C1_WAKE_MASK (0x8U)
4977 #define UART_C1_WAKE_SHIFT (3U)
4978 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
4979 #define UART_C1_M_MASK (0x10U)
4980 #define UART_C1_M_SHIFT (4U)
4981 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
4982 #define UART_C1_RSRC_MASK (0x20U)
4983 #define UART_C1_RSRC_SHIFT (5U)
4984 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
4985 #define UART_C1_UARTSWAI_MASK (0x40U)
4986 #define UART_C1_UARTSWAI_SHIFT (6U)
4987 #define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
4988 #define UART_C1_LOOPS_MASK (0x80U)
4989 #define UART_C1_LOOPS_SHIFT (7U)
4990 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
4992 /*! @name C2 - UART Control Register 2 */
4993 #define UART_C2_SBK_MASK (0x1U)
4994 #define UART_C2_SBK_SHIFT (0U)
4995 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
4996 #define UART_C2_RWU_MASK (0x2U)
4997 #define UART_C2_RWU_SHIFT (1U)
4998 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
4999 #define UART_C2_RE_MASK (0x4U)
5000 #define UART_C2_RE_SHIFT (2U)
5001 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
5002 #define UART_C2_TE_MASK (0x8U)
5003 #define UART_C2_TE_SHIFT (3U)
5004 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
5005 #define UART_C2_ILIE_MASK (0x10U)
5006 #define UART_C2_ILIE_SHIFT (4U)
5007 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
5008 #define UART_C2_RIE_MASK (0x20U)
5009 #define UART_C2_RIE_SHIFT (5U)
5010 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
5011 #define UART_C2_TCIE_MASK (0x40U)
5012 #define UART_C2_TCIE_SHIFT (6U)
5013 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
5014 #define UART_C2_TIE_MASK (0x80U)
5015 #define UART_C2_TIE_SHIFT (7U)
5016 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
5018 /*! @name S1 - UART Status Register 1 */
5019 #define UART_S1_PF_MASK (0x1U)
5020 #define UART_S1_PF_SHIFT (0U)
5021 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
5022 #define UART_S1_FE_MASK (0x2U)
5023 #define UART_S1_FE_SHIFT (1U)
5024 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
5025 #define UART_S1_NF_MASK (0x4U)
5026 #define UART_S1_NF_SHIFT (2U)
5027 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
5028 #define UART_S1_OR_MASK (0x8U)
5029 #define UART_S1_OR_SHIFT (3U)
5030 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
5031 #define UART_S1_IDLE_MASK (0x10U)
5032 #define UART_S1_IDLE_SHIFT (4U)
5033 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
5034 #define UART_S1_RDRF_MASK (0x20U)
5035 #define UART_S1_RDRF_SHIFT (5U)
5036 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
5037 #define UART_S1_TC_MASK (0x40U)
5038 #define UART_S1_TC_SHIFT (6U)
5039 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
5040 #define UART_S1_TDRE_MASK (0x80U)
5041 #define UART_S1_TDRE_SHIFT (7U)
5042 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
5044 /*! @name S2 - UART Status Register 2 */
5045 #define UART_S2_RAF_MASK (0x1U)
5046 #define UART_S2_RAF_SHIFT (0U)
5047 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
5048 #define UART_S2_LBKDE_MASK (0x2U)
5049 #define UART_S2_LBKDE_SHIFT (1U)
5050 #define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
5051 #define UART_S2_BRK13_MASK (0x4U)
5052 #define UART_S2_BRK13_SHIFT (2U)
5053 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
5054 #define UART_S2_RWUID_MASK (0x8U)
5055 #define UART_S2_RWUID_SHIFT (3U)
5056 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
5057 #define UART_S2_RXINV_MASK (0x10U)
5058 #define UART_S2_RXINV_SHIFT (4U)
5059 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
5060 #define UART_S2_RXEDGIF_MASK (0x40U)
5061 #define UART_S2_RXEDGIF_SHIFT (6U)
5062 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
5063 #define UART_S2_LBKDIF_MASK (0x80U)
5064 #define UART_S2_LBKDIF_SHIFT (7U)
5065 #define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
5067 /*! @name C3 - UART Control Register 3 */
5068 #define UART_C3_PEIE_MASK (0x1U)
5069 #define UART_C3_PEIE_SHIFT (0U)
5070 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
5071 #define UART_C3_FEIE_MASK (0x2U)
5072 #define UART_C3_FEIE_SHIFT (1U)
5073 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
5074 #define UART_C3_NEIE_MASK (0x4U)
5075 #define UART_C3_NEIE_SHIFT (2U)
5076 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
5077 #define UART_C3_ORIE_MASK (0x8U)
5078 #define UART_C3_ORIE_SHIFT (3U)
5079 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
5080 #define UART_C3_TXINV_MASK (0x10U)
5081 #define UART_C3_TXINV_SHIFT (4U)
5082 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
5083 #define UART_C3_TXDIR_MASK (0x20U)
5084 #define UART_C3_TXDIR_SHIFT (5U)
5085 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
5086 #define UART_C3_T8_MASK (0x40U)
5087 #define UART_C3_T8_SHIFT (6U)
5088 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
5089 #define UART_C3_R8_MASK (0x80U)
5090 #define UART_C3_R8_SHIFT (7U)
5091 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
5093 /*! @name D - UART Data Register */
5094 #define UART_D_R0T0_MASK (0x1U)
5095 #define UART_D_R0T0_SHIFT (0U)
5096 #define UART_D_R0T0(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R0T0_SHIFT)) & UART_D_R0T0_MASK)
5097 #define UART_D_R1T1_MASK (0x2U)
5098 #define UART_D_R1T1_SHIFT (1U)
5099 #define UART_D_R1T1(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R1T1_SHIFT)) & UART_D_R1T1_MASK)
5100 #define UART_D_R2T2_MASK (0x4U)
5101 #define UART_D_R2T2_SHIFT (2U)
5102 #define UART_D_R2T2(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R2T2_SHIFT)) & UART_D_R2T2_MASK)
5103 #define UART_D_R3T3_MASK (0x8U)
5104 #define UART_D_R3T3_SHIFT (3U)
5105 #define UART_D_R3T3(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R3T3_SHIFT)) & UART_D_R3T3_MASK)
5106 #define UART_D_R4T4_MASK (0x10U)
5107 #define UART_D_R4T4_SHIFT (4U)
5108 #define UART_D_R4T4(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R4T4_SHIFT)) & UART_D_R4T4_MASK)
5109 #define UART_D_R5T5_MASK (0x20U)
5110 #define UART_D_R5T5_SHIFT (5U)
5111 #define UART_D_R5T5(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R5T5_SHIFT)) & UART_D_R5T5_MASK)
5112 #define UART_D_R6T6_MASK (0x40U)
5113 #define UART_D_R6T6_SHIFT (6U)
5114 #define UART_D_R6T6(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R6T6_SHIFT)) & UART_D_R6T6_MASK)
5115 #define UART_D_R7T7_MASK (0x80U)
5116 #define UART_D_R7T7_SHIFT (7U)
5117 #define UART_D_R7T7(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R7T7_SHIFT)) & UART_D_R7T7_MASK)
5119 /*! @name C4 - UART Control Register 4 */
5120 #define UART_C4_RDMAS_MASK (0x20U)
5121 #define UART_C4_RDMAS_SHIFT (5U)
5122 #define UART_C4_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_RDMAS_SHIFT)) & UART_C4_RDMAS_MASK)
5123 #define UART_C4_TDMAS_MASK (0x80U)
5124 #define UART_C4_TDMAS_SHIFT (7U)
5125 #define UART_C4_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_TDMAS_SHIFT)) & UART_C4_TDMAS_MASK)
5130 */ /* end of group UART_Register_Masks */
5133 /* UART - Peripheral instance base addresses */
5134 /** Peripheral UART1 base address */
5135 #define UART1_BASE (0x4006B000u)
5136 /** Peripheral UART1 base pointer */
5137 #define UART1 ((UART_Type *)UART1_BASE)
5138 /** Peripheral UART2 base address */
5139 #define UART2_BASE (0x4006C000u)
5140 /** Peripheral UART2 base pointer */
5141 #define UART2 ((UART_Type *)UART2_BASE)
5142 /** Array initializer of UART peripheral base addresses */
5143 #define UART_BASE_ADDRS { 0u, UART1_BASE, UART2_BASE }
5144 /** Array initializer of UART peripheral base pointers */
5145 #define UART_BASE_PTRS { (UART_Type *)0u, UART1, UART2 }
5146 /** Interrupt vectors for the UART peripheral type */
5147 #define UART_RX_TX_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn }
5148 #define UART_ERR_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn }
5152 */ /* end of group UART_Peripheral_Access_Layer */
5155 /* ----------------------------------------------------------------------------
5156 -- UART0 Peripheral Access Layer
5157 ---------------------------------------------------------------------------- */
5160 * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
5164 /** UART0 - Register Layout Typedef */
5166 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
5167 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
5168 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
5169 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
5170 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
5171 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
5172 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
5173 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
5174 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
5175 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
5176 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
5177 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
5180 /* ----------------------------------------------------------------------------
5181 -- UART0 Register Masks
5182 ---------------------------------------------------------------------------- */
5185 * @addtogroup UART0_Register_Masks UART0 Register Masks
5189 /*! @name BDH - UART Baud Rate Register High */
5190 #define UART0_BDH_SBR_MASK (0x1FU)
5191 #define UART0_BDH_SBR_SHIFT (0U)
5192 #define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_SBR_SHIFT)) & UART0_BDH_SBR_MASK)
5193 #define UART0_BDH_SBNS_MASK (0x20U)
5194 #define UART0_BDH_SBNS_SHIFT (5U)
5195 #define UART0_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_SBNS_SHIFT)) & UART0_BDH_SBNS_MASK)
5196 #define UART0_BDH_RXEDGIE_MASK (0x40U)
5197 #define UART0_BDH_RXEDGIE_SHIFT (6U)
5198 #define UART0_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_RXEDGIE_SHIFT)) & UART0_BDH_RXEDGIE_MASK)
5199 #define UART0_BDH_LBKDIE_MASK (0x80U)
5200 #define UART0_BDH_LBKDIE_SHIFT (7U)
5201 #define UART0_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_LBKDIE_SHIFT)) & UART0_BDH_LBKDIE_MASK)
5203 /*! @name BDL - UART Baud Rate Register Low */
5204 #define UART0_BDL_SBR_MASK (0xFFU)
5205 #define UART0_BDL_SBR_SHIFT (0U)
5206 #define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDL_SBR_SHIFT)) & UART0_BDL_SBR_MASK)
5208 /*! @name C1 - UART Control Register 1 */
5209 #define UART0_C1_PT_MASK (0x1U)
5210 #define UART0_C1_PT_SHIFT (0U)
5211 #define UART0_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_PT_SHIFT)) & UART0_C1_PT_MASK)
5212 #define UART0_C1_PE_MASK (0x2U)
5213 #define UART0_C1_PE_SHIFT (1U)
5214 #define UART0_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_PE_SHIFT)) & UART0_C1_PE_MASK)
5215 #define UART0_C1_ILT_MASK (0x4U)
5216 #define UART0_C1_ILT_SHIFT (2U)
5217 #define UART0_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_ILT_SHIFT)) & UART0_C1_ILT_MASK)
5218 #define UART0_C1_WAKE_MASK (0x8U)
5219 #define UART0_C1_WAKE_SHIFT (3U)
5220 #define UART0_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_WAKE_SHIFT)) & UART0_C1_WAKE_MASK)
5221 #define UART0_C1_M_MASK (0x10U)
5222 #define UART0_C1_M_SHIFT (4U)
5223 #define UART0_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_M_SHIFT)) & UART0_C1_M_MASK)
5224 #define UART0_C1_RSRC_MASK (0x20U)
5225 #define UART0_C1_RSRC_SHIFT (5U)
5226 #define UART0_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_RSRC_SHIFT)) & UART0_C1_RSRC_MASK)
5227 #define UART0_C1_DOZEEN_MASK (0x40U)
5228 #define UART0_C1_DOZEEN_SHIFT (6U)
5229 #define UART0_C1_DOZEEN(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_DOZEEN_SHIFT)) & UART0_C1_DOZEEN_MASK)
5230 #define UART0_C1_LOOPS_MASK (0x80U)
5231 #define UART0_C1_LOOPS_SHIFT (7U)
5232 #define UART0_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_LOOPS_SHIFT)) & UART0_C1_LOOPS_MASK)
5234 /*! @name C2 - UART Control Register 2 */
5235 #define UART0_C2_SBK_MASK (0x1U)
5236 #define UART0_C2_SBK_SHIFT (0U)
5237 #define UART0_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_SBK_SHIFT)) & UART0_C2_SBK_MASK)
5238 #define UART0_C2_RWU_MASK (0x2U)
5239 #define UART0_C2_RWU_SHIFT (1U)
5240 #define UART0_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RWU_SHIFT)) & UART0_C2_RWU_MASK)
5241 #define UART0_C2_RE_MASK (0x4U)
5242 #define UART0_C2_RE_SHIFT (2U)
5243 #define UART0_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RE_SHIFT)) & UART0_C2_RE_MASK)
5244 #define UART0_C2_TE_MASK (0x8U)
5245 #define UART0_C2_TE_SHIFT (3U)
5246 #define UART0_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TE_SHIFT)) & UART0_C2_TE_MASK)
5247 #define UART0_C2_ILIE_MASK (0x10U)
5248 #define UART0_C2_ILIE_SHIFT (4U)
5249 #define UART0_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_ILIE_SHIFT)) & UART0_C2_ILIE_MASK)
5250 #define UART0_C2_RIE_MASK (0x20U)
5251 #define UART0_C2_RIE_SHIFT (5U)
5252 #define UART0_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RIE_SHIFT)) & UART0_C2_RIE_MASK)
5253 #define UART0_C2_TCIE_MASK (0x40U)
5254 #define UART0_C2_TCIE_SHIFT (6U)
5255 #define UART0_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TCIE_SHIFT)) & UART0_C2_TCIE_MASK)
5256 #define UART0_C2_TIE_MASK (0x80U)
5257 #define UART0_C2_TIE_SHIFT (7U)
5258 #define UART0_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TIE_SHIFT)) & UART0_C2_TIE_MASK)
5260 /*! @name S1 - UART Status Register 1 */
5261 #define UART0_S1_PF_MASK (0x1U)
5262 #define UART0_S1_PF_SHIFT (0U)
5263 #define UART0_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_PF_SHIFT)) & UART0_S1_PF_MASK)
5264 #define UART0_S1_FE_MASK (0x2U)
5265 #define UART0_S1_FE_SHIFT (1U)
5266 #define UART0_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_FE_SHIFT)) & UART0_S1_FE_MASK)
5267 #define UART0_S1_NF_MASK (0x4U)
5268 #define UART0_S1_NF_SHIFT (2U)
5269 #define UART0_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_NF_SHIFT)) & UART0_S1_NF_MASK)
5270 #define UART0_S1_OR_MASK (0x8U)
5271 #define UART0_S1_OR_SHIFT (3U)
5272 #define UART0_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_OR_SHIFT)) & UART0_S1_OR_MASK)
5273 #define UART0_S1_IDLE_MASK (0x10U)
5274 #define UART0_S1_IDLE_SHIFT (4U)
5275 #define UART0_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_IDLE_SHIFT)) & UART0_S1_IDLE_MASK)
5276 #define UART0_S1_RDRF_MASK (0x20U)
5277 #define UART0_S1_RDRF_SHIFT (5U)
5278 #define UART0_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_RDRF_SHIFT)) & UART0_S1_RDRF_MASK)
5279 #define UART0_S1_TC_MASK (0x40U)
5280 #define UART0_S1_TC_SHIFT (6U)
5281 #define UART0_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_TC_SHIFT)) & UART0_S1_TC_MASK)
5282 #define UART0_S1_TDRE_MASK (0x80U)
5283 #define UART0_S1_TDRE_SHIFT (7U)
5284 #define UART0_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_TDRE_SHIFT)) & UART0_S1_TDRE_MASK)
5286 /*! @name S2 - UART Status Register 2 */
5287 #define UART0_S2_RAF_MASK (0x1U)
5288 #define UART0_S2_RAF_SHIFT (0U)
5289 #define UART0_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RAF_SHIFT)) & UART0_S2_RAF_MASK)
5290 #define UART0_S2_LBKDE_MASK (0x2U)
5291 #define UART0_S2_LBKDE_SHIFT (1U)
5292 #define UART0_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_LBKDE_SHIFT)) & UART0_S2_LBKDE_MASK)
5293 #define UART0_S2_BRK13_MASK (0x4U)
5294 #define UART0_S2_BRK13_SHIFT (2U)
5295 #define UART0_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_BRK13_SHIFT)) & UART0_S2_BRK13_MASK)
5296 #define UART0_S2_RWUID_MASK (0x8U)
5297 #define UART0_S2_RWUID_SHIFT (3U)
5298 #define UART0_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RWUID_SHIFT)) & UART0_S2_RWUID_MASK)
5299 #define UART0_S2_RXINV_MASK (0x10U)
5300 #define UART0_S2_RXINV_SHIFT (4U)
5301 #define UART0_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RXINV_SHIFT)) & UART0_S2_RXINV_MASK)
5302 #define UART0_S2_MSBF_MASK (0x20U)
5303 #define UART0_S2_MSBF_SHIFT (5U)
5304 #define UART0_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_MSBF_SHIFT)) & UART0_S2_MSBF_MASK)
5305 #define UART0_S2_RXEDGIF_MASK (0x40U)
5306 #define UART0_S2_RXEDGIF_SHIFT (6U)
5307 #define UART0_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RXEDGIF_SHIFT)) & UART0_S2_RXEDGIF_MASK)
5308 #define UART0_S2_LBKDIF_MASK (0x80U)
5309 #define UART0_S2_LBKDIF_SHIFT (7U)
5310 #define UART0_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_LBKDIF_SHIFT)) & UART0_S2_LBKDIF_MASK)
5312 /*! @name C3 - UART Control Register 3 */
5313 #define UART0_C3_PEIE_MASK (0x1U)
5314 #define UART0_C3_PEIE_SHIFT (0U)
5315 #define UART0_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_PEIE_SHIFT)) & UART0_C3_PEIE_MASK)
5316 #define UART0_C3_FEIE_MASK (0x2U)
5317 #define UART0_C3_FEIE_SHIFT (1U)
5318 #define UART0_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_FEIE_SHIFT)) & UART0_C3_FEIE_MASK)
5319 #define UART0_C3_NEIE_MASK (0x4U)
5320 #define UART0_C3_NEIE_SHIFT (2U)
5321 #define UART0_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_NEIE_SHIFT)) & UART0_C3_NEIE_MASK)
5322 #define UART0_C3_ORIE_MASK (0x8U)
5323 #define UART0_C3_ORIE_SHIFT (3U)
5324 #define UART0_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_ORIE_SHIFT)) & UART0_C3_ORIE_MASK)
5325 #define UART0_C3_TXINV_MASK (0x10U)
5326 #define UART0_C3_TXINV_SHIFT (4U)
5327 #define UART0_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_TXINV_SHIFT)) & UART0_C3_TXINV_MASK)
5328 #define UART0_C3_TXDIR_MASK (0x20U)
5329 #define UART0_C3_TXDIR_SHIFT (5U)
5330 #define UART0_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_TXDIR_SHIFT)) & UART0_C3_TXDIR_MASK)
5331 #define UART0_C3_R9T8_MASK (0x40U)
5332 #define UART0_C3_R9T8_SHIFT (6U)
5333 #define UART0_C3_R9T8(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_R9T8_SHIFT)) & UART0_C3_R9T8_MASK)
5334 #define UART0_C3_R8T9_MASK (0x80U)
5335 #define UART0_C3_R8T9_SHIFT (7U)
5336 #define UART0_C3_R8T9(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_R8T9_SHIFT)) & UART0_C3_R8T9_MASK)
5338 /*! @name D - UART Data Register */
5339 #define UART0_D_R0T0_MASK (0x1U)
5340 #define UART0_D_R0T0_SHIFT (0U)
5341 #define UART0_D_R0T0(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R0T0_SHIFT)) & UART0_D_R0T0_MASK)
5342 #define UART0_D_R1T1_MASK (0x2U)
5343 #define UART0_D_R1T1_SHIFT (1U)
5344 #define UART0_D_R1T1(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R1T1_SHIFT)) & UART0_D_R1T1_MASK)
5345 #define UART0_D_R2T2_MASK (0x4U)
5346 #define UART0_D_R2T2_SHIFT (2U)
5347 #define UART0_D_R2T2(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R2T2_SHIFT)) & UART0_D_R2T2_MASK)
5348 #define UART0_D_R3T3_MASK (0x8U)
5349 #define UART0_D_R3T3_SHIFT (3U)
5350 #define UART0_D_R3T3(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R3T3_SHIFT)) & UART0_D_R3T3_MASK)
5351 #define UART0_D_R4T4_MASK (0x10U)
5352 #define UART0_D_R4T4_SHIFT (4U)
5353 #define UART0_D_R4T4(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R4T4_SHIFT)) & UART0_D_R4T4_MASK)
5354 #define UART0_D_R5T5_MASK (0x20U)
5355 #define UART0_D_R5T5_SHIFT (5U)
5356 #define UART0_D_R5T5(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R5T5_SHIFT)) & UART0_D_R5T5_MASK)
5357 #define UART0_D_R6T6_MASK (0x40U)
5358 #define UART0_D_R6T6_SHIFT (6U)
5359 #define UART0_D_R6T6(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R6T6_SHIFT)) & UART0_D_R6T6_MASK)
5360 #define UART0_D_R7T7_MASK (0x80U)
5361 #define UART0_D_R7T7_SHIFT (7U)
5362 #define UART0_D_R7T7(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R7T7_SHIFT)) & UART0_D_R7T7_MASK)
5364 /*! @name MA1 - UART Match Address Registers 1 */
5365 #define UART0_MA1_MA_MASK (0xFFU)
5366 #define UART0_MA1_MA_SHIFT (0U)
5367 #define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART0_MA1_MA_SHIFT)) & UART0_MA1_MA_MASK)
5369 /*! @name MA2 - UART Match Address Registers 2 */
5370 #define UART0_MA2_MA_MASK (0xFFU)
5371 #define UART0_MA2_MA_SHIFT (0U)
5372 #define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART0_MA2_MA_SHIFT)) & UART0_MA2_MA_MASK)
5374 /*! @name C4 - UART Control Register 4 */
5375 #define UART0_C4_OSR_MASK (0x1FU)
5376 #define UART0_C4_OSR_SHIFT (0U)
5377 #define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_OSR_SHIFT)) & UART0_C4_OSR_MASK)
5378 #define UART0_C4_M10_MASK (0x20U)
5379 #define UART0_C4_M10_SHIFT (5U)
5380 #define UART0_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_M10_SHIFT)) & UART0_C4_M10_MASK)
5381 #define UART0_C4_MAEN2_MASK (0x40U)
5382 #define UART0_C4_MAEN2_SHIFT (6U)
5383 #define UART0_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_MAEN2_SHIFT)) & UART0_C4_MAEN2_MASK)
5384 #define UART0_C4_MAEN1_MASK (0x80U)
5385 #define UART0_C4_MAEN1_SHIFT (7U)
5386 #define UART0_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_MAEN1_SHIFT)) & UART0_C4_MAEN1_MASK)
5388 /*! @name C5 - UART Control Register 5 */
5389 #define UART0_C5_RESYNCDIS_MASK (0x1U)
5390 #define UART0_C5_RESYNCDIS_SHIFT (0U)
5391 #define UART0_C5_RESYNCDIS(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_RESYNCDIS_SHIFT)) & UART0_C5_RESYNCDIS_MASK)
5392 #define UART0_C5_BOTHEDGE_MASK (0x2U)
5393 #define UART0_C5_BOTHEDGE_SHIFT (1U)
5394 #define UART0_C5_BOTHEDGE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_BOTHEDGE_SHIFT)) & UART0_C5_BOTHEDGE_MASK)
5395 #define UART0_C5_RDMAE_MASK (0x20U)
5396 #define UART0_C5_RDMAE_SHIFT (5U)
5397 #define UART0_C5_RDMAE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_RDMAE_SHIFT)) & UART0_C5_RDMAE_MASK)
5398 #define UART0_C5_TDMAE_MASK (0x80U)
5399 #define UART0_C5_TDMAE_SHIFT (7U)
5400 #define UART0_C5_TDMAE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_TDMAE_SHIFT)) & UART0_C5_TDMAE_MASK)
5405 */ /* end of group UART0_Register_Masks */
5408 /* UART0 - Peripheral instance base addresses */
5409 /** Peripheral UART0 base address */
5410 #define UART0_BASE (0x4006A000u)
5411 /** Peripheral UART0 base pointer */
5412 #define UART0 ((UART0_Type *)UART0_BASE)
5413 /** Array initializer of UART0 peripheral base addresses */
5414 #define UART0_BASE_ADDRS { UART0_BASE }
5415 /** Array initializer of UART0 peripheral base pointers */
5416 #define UART0_BASE_PTRS { UART0 }
5417 /** Interrupt vectors for the UART0 peripheral type */
5418 #define UART0_RX_TX_IRQS { UART0_IRQn }
5419 #define UART0_ERR_IRQS { UART0_IRQn }
5423 */ /* end of group UART0_Peripheral_Access_Layer */
5426 /* ----------------------------------------------------------------------------
5427 -- USB Peripheral Access Layer
5428 ---------------------------------------------------------------------------- */
5431 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
5435 /** USB - Register Layout Typedef */
5437 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
5438 uint8_t RESERVED_0[3];
5439 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
5440 uint8_t RESERVED_1[3];
5441 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
5442 uint8_t RESERVED_2[3];
5443 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
5444 uint8_t RESERVED_3[3];
5445 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
5446 uint8_t RESERVED_4[3];
5447 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
5448 uint8_t RESERVED_5[3];
5449 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
5450 uint8_t RESERVED_6[3];
5451 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
5452 uint8_t RESERVED_7[99];
5453 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
5454 uint8_t RESERVED_8[3];
5455 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
5456 uint8_t RESERVED_9[3];
5457 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
5458 uint8_t RESERVED_10[3];
5459 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
5460 uint8_t RESERVED_11[3];
5461 __I uint8_t STAT; /**< Status register, offset: 0x90 */
5462 uint8_t RESERVED_12[3];
5463 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
5464 uint8_t RESERVED_13[3];
5465 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
5466 uint8_t RESERVED_14[3];
5467 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
5468 uint8_t RESERVED_15[3];
5469 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
5470 uint8_t RESERVED_16[3];
5471 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
5472 uint8_t RESERVED_17[3];
5473 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
5474 uint8_t RESERVED_18[3];
5475 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
5476 uint8_t RESERVED_19[3];
5477 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
5478 uint8_t RESERVED_20[3];
5479 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
5480 uint8_t RESERVED_21[11];
5481 struct { /* offset: 0xC0, array step: 0x4 */
5482 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
5483 uint8_t RESERVED_0[3];
5485 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
5486 uint8_t RESERVED_22[3];
5487 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
5488 uint8_t RESERVED_23[3];
5489 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
5490 uint8_t RESERVED_24[3];
5491 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
5492 uint8_t RESERVED_25[7];
5493 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
5496 /* ----------------------------------------------------------------------------
5497 -- USB Register Masks
5498 ---------------------------------------------------------------------------- */
5501 * @addtogroup USB_Register_Masks USB Register Masks
5505 /*! @name PERID - Peripheral ID register */
5506 #define USB_PERID_ID_MASK (0x3FU)
5507 #define USB_PERID_ID_SHIFT (0U)
5508 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
5510 /*! @name IDCOMP - Peripheral ID Complement register */
5511 #define USB_IDCOMP_NID_MASK (0x3FU)
5512 #define USB_IDCOMP_NID_SHIFT (0U)
5513 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
5515 /*! @name REV - Peripheral Revision register */
5516 #define USB_REV_REV_MASK (0xFFU)
5517 #define USB_REV_REV_SHIFT (0U)
5518 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
5520 /*! @name ADDINFO - Peripheral Additional Info register */
5521 #define USB_ADDINFO_IEHOST_MASK (0x1U)
5522 #define USB_ADDINFO_IEHOST_SHIFT (0U)
5523 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
5524 #define USB_ADDINFO_IRQNUM_MASK (0xF8U)
5525 #define USB_ADDINFO_IRQNUM_SHIFT (3U)
5526 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK)
5528 /*! @name OTGISTAT - OTG Interrupt Status register */
5529 #define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
5530 #define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
5531 #define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
5532 #define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
5533 #define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
5534 #define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
5535 #define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
5536 #define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
5537 #define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
5538 #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
5539 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
5540 #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
5541 #define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
5542 #define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
5543 #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
5544 #define USB_OTGISTAT_IDCHG_MASK (0x80U)
5545 #define USB_OTGISTAT_IDCHG_SHIFT (7U)
5546 #define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
5548 /*! @name OTGICR - OTG Interrupt Control register */
5549 #define USB_OTGICR_AVBUSEN_MASK (0x1U)
5550 #define USB_OTGICR_AVBUSEN_SHIFT (0U)
5551 #define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
5552 #define USB_OTGICR_BSESSEN_MASK (0x4U)
5553 #define USB_OTGICR_BSESSEN_SHIFT (2U)
5554 #define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
5555 #define USB_OTGICR_SESSVLDEN_MASK (0x8U)
5556 #define USB_OTGICR_SESSVLDEN_SHIFT (3U)
5557 #define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
5558 #define USB_OTGICR_LINESTATEEN_MASK (0x20U)
5559 #define USB_OTGICR_LINESTATEEN_SHIFT (5U)
5560 #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
5561 #define USB_OTGICR_ONEMSECEN_MASK (0x40U)
5562 #define USB_OTGICR_ONEMSECEN_SHIFT (6U)
5563 #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
5564 #define USB_OTGICR_IDEN_MASK (0x80U)
5565 #define USB_OTGICR_IDEN_SHIFT (7U)
5566 #define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
5568 /*! @name OTGSTAT - OTG Status register */
5569 #define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
5570 #define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
5571 #define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
5572 #define USB_OTGSTAT_BSESSEND_MASK (0x4U)
5573 #define USB_OTGSTAT_BSESSEND_SHIFT (2U)
5574 #define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
5575 #define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
5576 #define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
5577 #define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
5578 #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
5579 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
5580 #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
5581 #define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
5582 #define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
5583 #define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
5584 #define USB_OTGSTAT_ID_MASK (0x80U)
5585 #define USB_OTGSTAT_ID_SHIFT (7U)
5586 #define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
5588 /*! @name OTGCTL - OTG Control register */
5589 #define USB_OTGCTL_OTGEN_MASK (0x4U)
5590 #define USB_OTGCTL_OTGEN_SHIFT (2U)
5591 #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
5592 #define USB_OTGCTL_DMLOW_MASK (0x10U)
5593 #define USB_OTGCTL_DMLOW_SHIFT (4U)
5594 #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
5595 #define USB_OTGCTL_DPLOW_MASK (0x20U)
5596 #define USB_OTGCTL_DPLOW_SHIFT (5U)
5597 #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
5598 #define USB_OTGCTL_DPHIGH_MASK (0x80U)
5599 #define USB_OTGCTL_DPHIGH_SHIFT (7U)
5600 #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
5602 /*! @name ISTAT - Interrupt Status register */
5603 #define USB_ISTAT_USBRST_MASK (0x1U)
5604 #define USB_ISTAT_USBRST_SHIFT (0U)
5605 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
5606 #define USB_ISTAT_ERROR_MASK (0x2U)
5607 #define USB_ISTAT_ERROR_SHIFT (1U)
5608 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
5609 #define USB_ISTAT_SOFTOK_MASK (0x4U)
5610 #define USB_ISTAT_SOFTOK_SHIFT (2U)
5611 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
5612 #define USB_ISTAT_TOKDNE_MASK (0x8U)
5613 #define USB_ISTAT_TOKDNE_SHIFT (3U)
5614 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
5615 #define USB_ISTAT_SLEEP_MASK (0x10U)
5616 #define USB_ISTAT_SLEEP_SHIFT (4U)
5617 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
5618 #define USB_ISTAT_RESUME_MASK (0x20U)
5619 #define USB_ISTAT_RESUME_SHIFT (5U)
5620 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
5621 #define USB_ISTAT_ATTACH_MASK (0x40U)
5622 #define USB_ISTAT_ATTACH_SHIFT (6U)
5623 #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
5624 #define USB_ISTAT_STALL_MASK (0x80U)
5625 #define USB_ISTAT_STALL_SHIFT (7U)
5626 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
5628 /*! @name INTEN - Interrupt Enable register */
5629 #define USB_INTEN_USBRSTEN_MASK (0x1U)
5630 #define USB_INTEN_USBRSTEN_SHIFT (0U)
5631 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
5632 #define USB_INTEN_ERROREN_MASK (0x2U)
5633 #define USB_INTEN_ERROREN_SHIFT (1U)
5634 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
5635 #define USB_INTEN_SOFTOKEN_MASK (0x4U)
5636 #define USB_INTEN_SOFTOKEN_SHIFT (2U)
5637 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
5638 #define USB_INTEN_TOKDNEEN_MASK (0x8U)
5639 #define USB_INTEN_TOKDNEEN_SHIFT (3U)
5640 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
5641 #define USB_INTEN_SLEEPEN_MASK (0x10U)
5642 #define USB_INTEN_SLEEPEN_SHIFT (4U)
5643 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
5644 #define USB_INTEN_RESUMEEN_MASK (0x20U)
5645 #define USB_INTEN_RESUMEEN_SHIFT (5U)
5646 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
5647 #define USB_INTEN_ATTACHEN_MASK (0x40U)
5648 #define USB_INTEN_ATTACHEN_SHIFT (6U)
5649 #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
5650 #define USB_INTEN_STALLEN_MASK (0x80U)
5651 #define USB_INTEN_STALLEN_SHIFT (7U)
5652 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
5654 /*! @name ERRSTAT - Error Interrupt Status register */
5655 #define USB_ERRSTAT_PIDERR_MASK (0x1U)
5656 #define USB_ERRSTAT_PIDERR_SHIFT (0U)
5657 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
5658 #define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
5659 #define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
5660 #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
5661 #define USB_ERRSTAT_CRC16_MASK (0x4U)
5662 #define USB_ERRSTAT_CRC16_SHIFT (2U)
5663 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
5664 #define USB_ERRSTAT_DFN8_MASK (0x8U)
5665 #define USB_ERRSTAT_DFN8_SHIFT (3U)
5666 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
5667 #define USB_ERRSTAT_BTOERR_MASK (0x10U)
5668 #define USB_ERRSTAT_BTOERR_SHIFT (4U)
5669 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
5670 #define USB_ERRSTAT_DMAERR_MASK (0x20U)
5671 #define USB_ERRSTAT_DMAERR_SHIFT (5U)
5672 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
5673 #define USB_ERRSTAT_BTSERR_MASK (0x80U)
5674 #define USB_ERRSTAT_BTSERR_SHIFT (7U)
5675 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
5677 /*! @name ERREN - Error Interrupt Enable register */
5678 #define USB_ERREN_PIDERREN_MASK (0x1U)
5679 #define USB_ERREN_PIDERREN_SHIFT (0U)
5680 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
5681 #define USB_ERREN_CRC5EOFEN_MASK (0x2U)
5682 #define USB_ERREN_CRC5EOFEN_SHIFT (1U)
5683 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
5684 #define USB_ERREN_CRC16EN_MASK (0x4U)
5685 #define USB_ERREN_CRC16EN_SHIFT (2U)
5686 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
5687 #define USB_ERREN_DFN8EN_MASK (0x8U)
5688 #define USB_ERREN_DFN8EN_SHIFT (3U)
5689 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
5690 #define USB_ERREN_BTOERREN_MASK (0x10U)
5691 #define USB_ERREN_BTOERREN_SHIFT (4U)
5692 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
5693 #define USB_ERREN_DMAERREN_MASK (0x20U)
5694 #define USB_ERREN_DMAERREN_SHIFT (5U)
5695 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
5696 #define USB_ERREN_BTSERREN_MASK (0x80U)
5697 #define USB_ERREN_BTSERREN_SHIFT (7U)
5698 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
5700 /*! @name STAT - Status register */
5701 #define USB_STAT_ODD_MASK (0x4U)
5702 #define USB_STAT_ODD_SHIFT (2U)
5703 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
5704 #define USB_STAT_TX_MASK (0x8U)
5705 #define USB_STAT_TX_SHIFT (3U)
5706 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
5707 #define USB_STAT_ENDP_MASK (0xF0U)
5708 #define USB_STAT_ENDP_SHIFT (4U)
5709 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
5711 /*! @name CTL - Control register */
5712 #define USB_CTL_USBENSOFEN_MASK (0x1U)
5713 #define USB_CTL_USBENSOFEN_SHIFT (0U)
5714 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
5715 #define USB_CTL_ODDRST_MASK (0x2U)
5716 #define USB_CTL_ODDRST_SHIFT (1U)
5717 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
5718 #define USB_CTL_RESUME_MASK (0x4U)
5719 #define USB_CTL_RESUME_SHIFT (2U)
5720 #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
5721 #define USB_CTL_HOSTMODEEN_MASK (0x8U)
5722 #define USB_CTL_HOSTMODEEN_SHIFT (3U)
5723 #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
5724 #define USB_CTL_RESET_MASK (0x10U)
5725 #define USB_CTL_RESET_SHIFT (4U)
5726 #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
5727 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
5728 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
5729 #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
5730 #define USB_CTL_SE0_MASK (0x40U)
5731 #define USB_CTL_SE0_SHIFT (6U)
5732 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
5733 #define USB_CTL_JSTATE_MASK (0x80U)
5734 #define USB_CTL_JSTATE_SHIFT (7U)
5735 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
5737 /*! @name ADDR - Address register */
5738 #define USB_ADDR_ADDR_MASK (0x7FU)
5739 #define USB_ADDR_ADDR_SHIFT (0U)
5740 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
5741 #define USB_ADDR_LSEN_MASK (0x80U)
5742 #define USB_ADDR_LSEN_SHIFT (7U)
5743 #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
5745 /*! @name BDTPAGE1 - BDT Page register 1 */
5746 #define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
5747 #define USB_BDTPAGE1_BDTBA_SHIFT (1U)
5748 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
5750 /*! @name FRMNUML - Frame Number register Low */
5751 #define USB_FRMNUML_FRM_MASK (0xFFU)
5752 #define USB_FRMNUML_FRM_SHIFT (0U)
5753 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
5755 /*! @name FRMNUMH - Frame Number register High */
5756 #define USB_FRMNUMH_FRM_MASK (0x7U)
5757 #define USB_FRMNUMH_FRM_SHIFT (0U)
5758 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
5760 /*! @name TOKEN - Token register */
5761 #define USB_TOKEN_TOKENENDPT_MASK (0xFU)
5762 #define USB_TOKEN_TOKENENDPT_SHIFT (0U)
5763 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
5764 #define USB_TOKEN_TOKENPID_MASK (0xF0U)
5765 #define USB_TOKEN_TOKENPID_SHIFT (4U)
5766 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
5768 /*! @name SOFTHLD - SOF Threshold register */
5769 #define USB_SOFTHLD_CNT_MASK (0xFFU)
5770 #define USB_SOFTHLD_CNT_SHIFT (0U)
5771 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
5773 /*! @name BDTPAGE2 - BDT Page Register 2 */
5774 #define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
5775 #define USB_BDTPAGE2_BDTBA_SHIFT (0U)
5776 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
5778 /*! @name BDTPAGE3 - BDT Page Register 3 */
5779 #define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
5780 #define USB_BDTPAGE3_BDTBA_SHIFT (0U)
5781 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
5783 /*! @name ENDPT - Endpoint Control register */
5784 #define USB_ENDPT_EPHSHK_MASK (0x1U)
5785 #define USB_ENDPT_EPHSHK_SHIFT (0U)
5786 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
5787 #define USB_ENDPT_EPSTALL_MASK (0x2U)
5788 #define USB_ENDPT_EPSTALL_SHIFT (1U)
5789 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
5790 #define USB_ENDPT_EPTXEN_MASK (0x4U)
5791 #define USB_ENDPT_EPTXEN_SHIFT (2U)
5792 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
5793 #define USB_ENDPT_EPRXEN_MASK (0x8U)
5794 #define USB_ENDPT_EPRXEN_SHIFT (3U)
5795 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
5796 #define USB_ENDPT_EPCTLDIS_MASK (0x10U)
5797 #define USB_ENDPT_EPCTLDIS_SHIFT (4U)
5798 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
5799 #define USB_ENDPT_RETRYDIS_MASK (0x40U)
5800 #define USB_ENDPT_RETRYDIS_SHIFT (6U)
5801 #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
5802 #define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
5803 #define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
5804 #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
5806 /* The count of USB_ENDPT */
5807 #define USB_ENDPT_COUNT (16U)
5809 /*! @name USBCTRL - USB Control register */
5810 #define USB_USBCTRL_PDE_MASK (0x40U)
5811 #define USB_USBCTRL_PDE_SHIFT (6U)
5812 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
5813 #define USB_USBCTRL_SUSP_MASK (0x80U)
5814 #define USB_USBCTRL_SUSP_SHIFT (7U)
5815 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
5817 /*! @name OBSERVE - USB OTG Observe register */
5818 #define USB_OBSERVE_DMPD_MASK (0x10U)
5819 #define USB_OBSERVE_DMPD_SHIFT (4U)
5820 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
5821 #define USB_OBSERVE_DPPD_MASK (0x40U)
5822 #define USB_OBSERVE_DPPD_SHIFT (6U)
5823 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
5824 #define USB_OBSERVE_DPPU_MASK (0x80U)
5825 #define USB_OBSERVE_DPPU_SHIFT (7U)
5826 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
5828 /*! @name CONTROL - USB OTG Control register */
5829 #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
5830 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
5831 #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
5833 /*! @name USBTRC0 - USB Transceiver Control register 0 */
5834 #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
5835 #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
5836 #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
5837 #define USB_USBTRC0_SYNC_DET_MASK (0x2U)
5838 #define USB_USBTRC0_SYNC_DET_SHIFT (1U)
5839 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
5840 #define USB_USBTRC0_USBRESMEN_MASK (0x20U)
5841 #define USB_USBTRC0_USBRESMEN_SHIFT (5U)
5842 #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
5843 #define USB_USBTRC0_USBRESET_MASK (0x80U)
5844 #define USB_USBTRC0_USBRESET_SHIFT (7U)
5845 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
5847 /*! @name USBFRMADJUST - Frame Adjust Register */
5848 #define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
5849 #define USB_USBFRMADJUST_ADJ_SHIFT (0U)
5850 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
5855 */ /* end of group USB_Register_Masks */
5858 /* USB - Peripheral instance base addresses */
5859 /** Peripheral USB0 base address */
5860 #define USB0_BASE (0x40072000u)
5861 /** Peripheral USB0 base pointer */
5862 #define USB0 ((USB_Type *)USB0_BASE)
5863 /** Array initializer of USB peripheral base addresses */
5864 #define USB_BASE_ADDRS { USB0_BASE }
5865 /** Array initializer of USB peripheral base pointers */
5866 #define USB_BASE_PTRS { USB0 }
5867 /** Interrupt vectors for the USB peripheral type */
5868 #define USB_IRQS { USB0_IRQn }
5872 */ /* end of group USB_Peripheral_Access_Layer */
5876 ** End of section using anonymous unions
5879 #if defined(__ARMCC_VERSION)
5880 #if (__ARMCC_VERSION >= 6010050)
5881 #pragma clang diagnostic pop
5885 #elif defined(__CWCC__)
5887 #elif defined(__GNUC__)
5888 /* leave anonymous unions enabled */
5889 #elif defined(__IAR_SYSTEMS_ICC__)
5890 #pragma language=default
5892 #error Not supported compiler type
5897 */ /* end of group Peripheral_access_layer */
5900 /* ----------------------------------------------------------------------------
5901 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
5902 ---------------------------------------------------------------------------- */
5905 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
5909 #if defined(__ARMCC_VERSION)
5910 #if (__ARMCC_VERSION >= 6010050)
5911 #pragma clang system_header
5913 #elif defined(__IAR_SYSTEMS_ICC__)
5914 #pragma system_include
5918 * @brief Mask and left-shift a bit field value for use in a register bit range.
5919 * @param field Name of the register bit field.
5920 * @param value Value of the bit field.
5921 * @return Masked and shifted value.
5923 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
5925 * @brief Mask and right-shift a register value to extract a bit field value.
5926 * @param field Name of the register bit field.
5927 * @param value Value of the register.
5928 * @return Masked and shifted bit field value.
5930 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
5934 */ /* end of group Bit_Field_Generic_Macros */
5937 /* ----------------------------------------------------------------------------
5938 -- SDK Compatibility
5939 ---------------------------------------------------------------------------- */
5942 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
5946 #define FPTA_BASE FGPIOA_BASE
5948 #define FPTB_BASE FGPIOB_BASE
5950 #define FPTC_BASE FGPIOC_BASE
5952 #define FPTD_BASE FGPIOD_BASE
5954 #define FPTE_BASE FGPIOE_BASE
5956 #define PTA_BASE GPIOA_BASE
5958 #define PTB_BASE GPIOB_BASE
5960 #define PTC_BASE GPIOC_BASE
5962 #define PTD_BASE GPIOD_BASE
5964 #define PTE_BASE GPIOE_BASE
5966 #define I2C_FLT_STOPIE_MASK This_symbol_has_been_deprecated
5967 #define I2C_FLT_STOPIE_SHIFT This_symbol_has_been_deprecated
5968 #define I2S_RCR2_CLKMODE_MASK I2S_RCR2_MSEL_MASK
5969 #define I2S_RCR2_CLKMODE_SHIFT I2S_RCR2_MSEL_SHIFT
5970 #define I2S_RCR2_CLKMODE(x) I2S_RCR2_MSEL(x)
5971 #define I2S_TCR2_CLKMODE_MASK I2S_TCR2_MSEL_MASK
5972 #define I2S_TCR2_CLKMODE_SHIFT I2S_TCR2_MSEL_SHIFT
5973 #define I2S_TCR2_CLKMODE(x) I2S_TCR2_MSEL(x)
5974 #define MCG_S_LOLS_MASK MCG_S_LOLS0_MASK
5975 #define MCG_S_LOLS_SHIFT MCG_S_LOLS0_SHIFT
5976 #define NVIC_ISPR_SETPEND(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ISPR_SETPEND_SHIFT))&NVIC_ISPR_SETPEND_MASK)
5977 #define LPTimer_IRQn LPTMR0_IRQn
5978 #define LPTimer_IRQHandler LPTMR0_IRQHandler
5979 #define LLW_IRQn LLWU_IRQn
5980 #define LLW_IRQHandler LLWU_IRQHandler
5984 */ /* end of group SDK_Compatibility_Symbols */
5987 #endif /* _MKL26Z4_H_ */