+++ /dev/null
-Submitted By: Jim Gifford (jim at cross-lfs dot org)
-Date: 07-07-2009
-Initial Package Version: 2.19.1
-Origin: Upstream
-Upstream Status: Applied
-Description: This is a branch update for binutils-2.19.1, and should be
- rechecked periodically.
-
-This patch was created on 20090707
-
-diff -Naur binutils-2.19.1.orig/bfd/ChangeLog binutils-2.19.1/bfd/ChangeLog
---- binutils-2.19.1.orig/bfd/ChangeLog 2009-02-02 02:44:39.000000000 -0800
-+++ binutils-2.19.1/bfd/ChangeLog 2009-03-02 05:55:19.000000000 -0800
-@@ -1,3 +1,108 @@
-+2009-03-02 Alan Modra <amodra@bigpond.net.au>
-+
-+ 2009-02-15 Alan Modra <amodra@bigpond.net.au>
-+ * elf64-ppc.c (struct _ppc64_elf_section_data): Delete t_symndx,
-+ add toc.symndx and toc.add.
-+ (ppc64_elf_check_relocs): Don't set htab->tls_get_addr here.
-+ Set up toc.add.
-+ (get_tls_mask): Add toc_addend param, set from toc.add. Adjust all
-+ callers.
-+ (ppc64_elf_tls_setup): Set htab->tls_get_addr and tls_get_addr_fd.
-+ (branch_reloc_hash_match): New function, extracted from..
-+ (ppc64_elf_tls_optimize): ..here.
-+ (ppc64_elf_relocate_section): Properly set addends when optimizing
-+ tls sequences. Avoid unnecessary reading and writing of insns.
-+ Only redo reloc when symbol changed. Bypass symbol checks when
-+ using tlsld_got.
-+ * elf32-ppc.c (ppc_elf_tls_setup): Correct comment.
-+ (branch_reloc_hash_match): New function, extracted from..
-+ (ppc_elf_tls_optimize): ..here.
-+ (ppc_elf_relocate_section): Avoid unnecessary reading of insns.
-+ Don't clear addend on zapped __tls_get_addr reloc.
-+
-+ 2009-02-01 Jan Kratochvil <jan.kratochvil@redhat.com>
-+ * elf-eh-frame.c (REQUIRE_CLEARED_RELOCS) Remove.
-+ (_bfd_elf_parse_eh_frame): Do not check relocations for removed FDEs.
-+
-+ 2009-01-26 Nathan Sidwell <nathan@codesourcery.com>
-+ * elf32-ppc.c (ppc_elf_relax_section): Add space for relocs
-+ describing the trampolines.
-+ (ppc_elf_relocate_section): Update relocs to describe the
-+ trampolines.
-+
-+ 2009-01-22 Alan Modra <amodra@bigpond.net.au>
-+ PR 6832
-+ * dwarf2.c (find_line): Don't update stash->sec_info_ptr until
-+ after comp_unit_find_line call.
-+
-+ 2009-01-14 Alan Modra <amodra@bigpond.net.au>
-+ PR 9735
-+ * syms.c (_bfd_stab_section_find_nearest_line): Don't free
-+ saved filename, use bfd_alloc rather than bfd_malloc for it.
-+
-+ 2009-01-11 Jan Kratochvil <jan.kratochvil@redhat.com>
-+ * elflink.c (_bfd_elf_section_already_linked): Handle g++-3.4
-+ relocations in `.gnu.linkonce.r.*' referencing its `.gnu.linkonce.t.*'.
-+
-+ 2008-12-11 Alan Modra <amodra@bigpond.net.au>
-+ PR 7041
-+ * elf64-ppc.c (func_desc_adjust): Correct logic making fake function
-+ descriptors. Similarly correct making function descriptors dynamic.
-+
-+ 2008-11-14 Nathan Sidwell <nathan@codesourcery.com>
-+ * elf.c (assign_file_positions_for_load_sections): Use header_size
-+ to avoid moving the load address of file headers.
-+ (assign_file_positions_for_load_sections): Set header_size for
-+ segments containing the file header.
-+
-+ 2008-11-13 Hans-Peter Nilsson <hp@axis.com>
-+ PR ld/7028
-+ * elf.c (assign_file_positions_for_load_sections): Allocate phrds
-+ with bfd_zalloc2 instead of bfd_alloc2. For the amount, use
-+ the possibly-preset header-size, not the computed one.
-+
-+ 2008-11-13 Alan Modra <amodra@bigpond.net.au>
-+ PR 7023
-+ * elf.c (bfd_section_from_shdr <SHT_SYMTAB>): Fail on invalid sh_info.
-+
-+ 2008-11-11 Alan Modra <amodra@bigpond.net.au>
-+ PR 7012
-+ * dwarf2.c (find_line): Don't keep stale pointers into realloc'd
-+ memory. Return on errors. Fix memory leak.
-+ (_bfd_dwarf2_cleanup_debug_info): Free dwarf_str_buffer.
-+
-+ 2008-10-10 Nathan Froyd <froydnj@codesourcery.com>
-+ * elf32-ppc.c (ppc_elf_merge_obj_attributes): Merge
-+ Tag_GNU_Power_ABI_Struct_Return.
-+
-+ 2008-10-03 Alan Modra <amodra@bigpond.net.au>
-+ * elf.c (bfd_elf_set_group_contents): Assign sh_info for ld -r when
-+ the signature symbol is global.
-+ * elflink.c (elf_link_input_bfd): Ensure group signature symbol
-+ is output when ld -r. Set group sh_info when local.
-+ * linker.c (default_indirect_link_order): Handle group sections
-+ specially.
-+
-+ 2008-09-28 Alan Modra <amodra@bigpond.net.au>
-+ * elf.c (_bfd_elf_init_private_section_data): Tweak union copy.
-+ (bfd_section_from_shdr): Don't change SHT_GROUP section name.
-+ * elflink.c (section_signature): New function.
-+ (_bfd_elf_section_already_linked): Use it.
-+
-+2009-02-15 Bjoern Haase <bjoern.m.haase@web.de>
-+
-+ PR 9841
-+ * elf32-avr.c: Handle case where no local symbos exist correctly.
-+
-+2009-02-04 Eric B. Weddington <eric.weddington@atmel.com>
-+
-+ * elf32-avr.c (avr_final_link_relocate): Allow avr25 to wraparound.
-+
-+2009-02-03 Tristan Gingold <gingold@adacore.com>
-+
-+ * Makefile.am (RELEASE): Unset.
-+ * Makefile.in: Regenerated.
-+
- 2009-02-02 Tristan Gingold <gingold@adacore.com>
-
- * configure.in: Bump version to 2.19.1
-diff -Naur binutils-2.19.1.orig/bfd/dwarf2.c binutils-2.19.1/bfd/dwarf2.c
---- binutils-2.19.1.orig/bfd/dwarf2.c 2008-10-02 01:07:16.000000000 -0700
-+++ binutils-2.19.1/bfd/dwarf2.c 2009-03-02 05:50:55.000000000 -0800
-@@ -1,6 +1,6 @@
- /* DWARF 2 support.
- Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-- 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
-+ 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
-
- Adapted from gdb/dwarf2read.c by Gavin Koch of Cygnus Solutions
- (gavin@cygnus.com).
-@@ -2989,8 +2989,6 @@
- symbols, 0,
- &stash->info_ptr_memory, &total_size))
- goto done;
-- stash->info_ptr = stash->info_ptr_memory;
-- stash->info_ptr_end = stash->info_ptr + total_size;
- }
- else
- {
-@@ -3008,63 +3006,64 @@
- if (stash->info_ptr_memory == NULL)
- goto done;
-
-- stash->info_ptr = stash->info_ptr_memory;
-- stash->info_ptr_end = stash->info_ptr;
--
-+ total_size = 0;
- for (msec = find_debug_info (debug_bfd, NULL);
- msec;
- msec = find_debug_info (debug_bfd, msec))
- {
- bfd_size_type size;
-- bfd_size_type start;
-
- size = msec->size;
- if (size == 0)
- continue;
-
-- start = stash->info_ptr_end - stash->info_ptr;
--
-- if ((bfd_simple_get_relocated_section_contents
-- (debug_bfd, msec, stash->info_ptr + start, symbols))
-- == NULL)
-- continue;
-+ if (!(bfd_simple_get_relocated_section_contents
-+ (debug_bfd, msec, stash->info_ptr_memory + total_size,
-+ symbols)))
-+ goto done;
-
-- stash->info_ptr_end = stash->info_ptr + start + size;
-+ total_size += size;
- }
--
-- BFD_ASSERT (stash->info_ptr_end == stash->info_ptr + total_size);
- }
- else
- {
- /* Case 3: multiple sections, some or all compressed. */
-- stash->info_ptr_memory = bfd_malloc (1);
-- stash->info_ptr = stash->info_ptr_memory;
-- stash->info_ptr_end = stash->info_ptr;
-+ stash->info_ptr_memory = NULL;
-+ total_size = 0;
- for (msec = find_debug_info (debug_bfd, NULL);
- msec;
- msec = find_debug_info (debug_bfd, msec))
- {
- bfd_size_type size = msec->size;
-- bfd_byte* buffer
-- = (bfd_simple_get_relocated_section_contents
-- (debug_bfd, msec, NULL, symbols));
-- if (! buffer)
-+ bfd_byte* buffer;
-+
-+ if (size == 0)
- continue;
-+
-+ buffer = (bfd_simple_get_relocated_section_contents
-+ (debug_bfd, msec, NULL, symbols));
-+ if (! buffer)
-+ goto done;
-+
- if (strcmp (msec->name, DWARF2_COMPRESSED_DEBUG_INFO) == 0)
- {
- if (! bfd_uncompress_section_contents (&buffer, &size))
-- continue;
-+ {
-+ free (buffer);
-+ goto done;
-+ }
- }
-- stash->info_ptr = bfd_realloc (stash->info_ptr,
-- stash->info_ptr_end
-- - stash->info_ptr + size);
-- memcpy (stash->info_ptr_end, buffer, size);
-+ stash->info_ptr_memory = bfd_realloc (stash->info_ptr_memory,
-+ total_size + size);
-+ memcpy (stash->info_ptr_memory + total_size, buffer, size);
- free (buffer);
-- stash->info_ptr_end += size;
-+ total_size += size;
- }
- }
- }
-
-+ stash->info_ptr = stash->info_ptr_memory;
-+ stash->info_ptr_end = stash->info_ptr + total_size;
- stash->sec = find_debug_info (debug_bfd, NULL);
- stash->sec_info_ptr = stash->info_ptr;
- stash->syms = symbols;
-@@ -3187,13 +3186,6 @@
- break;
- stash->info_ptr += length;
-
-- if ((bfd_vma) (stash->info_ptr - stash->sec_info_ptr)
-- == stash->sec->size)
-- {
-- stash->sec = find_debug_info (stash->bfd, stash->sec);
-- stash->sec_info_ptr = stash->info_ptr;
-- }
--
- if (stash->all_comp_units)
- stash->all_comp_units->prev_unit = each;
- else
-@@ -3223,6 +3215,14 @@
- functionname_ptr,
- linenumber_ptr,
- stash));
-+
-+ if ((bfd_vma) (stash->info_ptr - stash->sec_info_ptr)
-+ == stash->sec->size)
-+ {
-+ stash->sec = find_debug_info (stash->bfd, stash->sec);
-+ stash->sec_info_ptr = stash->info_ptr;
-+ }
-+
- if (found)
- goto done;
- }
-@@ -3364,8 +3364,14 @@
- }
- }
-
-- free (stash->dwarf_abbrev_buffer);
-- free (stash->dwarf_line_buffer);
-- free (stash->dwarf_ranges_buffer);
-- free (stash->info_ptr_memory);
-+ if (stash->dwarf_abbrev_buffer)
-+ free (stash->dwarf_abbrev_buffer);
-+ if (stash->dwarf_line_buffer)
-+ free (stash->dwarf_line_buffer);
-+ if (stash->dwarf_str_buffer)
-+ free (stash->dwarf_str_buffer);
-+ if (stash->dwarf_ranges_buffer)
-+ free (stash->dwarf_ranges_buffer);
-+ if (stash->info_ptr_memory)
-+ free (stash->info_ptr_memory);
- }
-diff -Naur binutils-2.19.1.orig/bfd/elf32-avr.c binutils-2.19.1/bfd/elf32-avr.c
---- binutils-2.19.1.orig/bfd/elf32-avr.c 2008-12-23 05:54:49.000000000 -0800
-+++ binutils-2.19.1/bfd/elf32-avr.c 2009-02-19 09:53:10.000000000 -0800
-@@ -854,10 +854,11 @@
- {
- /* Relative distance is too large. */
-
-- /* Always apply WRAPAROUND for avr2 and avr4. */
-+ /* Always apply WRAPAROUND for avr2, avr25, and avr4. */
- switch (bfd_get_mach (input_bfd))
- {
- case bfd_mach_avr2:
-+ case bfd_mach_avr25:
- case bfd_mach_avr4:
- break;
-
-@@ -1553,7 +1554,8 @@
- /* Adjust the local symbols defined in this section. */
- isym = (Elf_Internal_Sym *) symtab_hdr->contents;
- isymend = isym + symtab_hdr->sh_info;
-- for (; isym < isymend; isym++)
-+ /* Fix PR 9841, there may be no local symbols. */
-+ for (; isym != NULL && isym < isymend; isym++)
- {
- if (isym->st_shndx == sec_shndx
- && isym->st_value > addr
-diff -Naur binutils-2.19.1.orig/bfd/elf32-ppc.c binutils-2.19.1/bfd/elf32-ppc.c
---- binutils-2.19.1.orig/bfd/elf32-ppc.c 2008-12-23 05:54:49.000000000 -0800
-+++ binutils-2.19.1/bfd/elf32-ppc.c 2009-03-02 05:55:19.000000000 -0800
-@@ -1,6 +1,6 @@
- /* PowerPC-specific support for 32-bit ELF
- Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-- 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
-+ 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
- Written by Ian Lance Taylor, Cygnus Support.
-
- This file is part of BFD, the Binary File Descriptor library.
-@@ -3964,6 +3964,33 @@
- ibfd, obfd, in_abi, out_abi);
- }
-
-+ /* Check for conflicting Tag_GNU_Power_ABI_Struct_Return attributes
-+ and merge non-conflicting ones. */
-+ in_attr = &in_attrs[Tag_GNU_Power_ABI_Struct_Return];
-+ out_attr = &out_attrs[Tag_GNU_Power_ABI_Struct_Return];
-+ if (in_attr->i != out_attr->i)
-+ {
-+ out_attr->type = 1;
-+ if (out_attr->i == 0)
-+ out_attr->i = in_attr->i;
-+ else if (in_attr->i == 0)
-+ ;
-+ else if (out_attr->i == 1 && in_attr->i == 2)
-+ _bfd_error_handler
-+ (_("Warning: %B uses r3/r4 for small structure returns, %B uses memory"), obfd, ibfd);
-+ else if (out_attr->i == 2 && in_attr->i == 1)
-+ _bfd_error_handler
-+ (_("Warning: %B uses r3/r4 for small structure returns, %B uses memory"), ibfd, obfd);
-+ else if (in_attr->i > 2)
-+ _bfd_error_handler
-+ (_("Warning: %B uses unknown small structure return convention %d"), ibfd,
-+ in_attr->i);
-+ else
-+ _bfd_error_handler
-+ (_("Warning: %B uses unknown small structure return convention %d"), obfd,
-+ out_attr->i);
-+ }
-+
- /* Merge Tag_compatibility attributes and any common GNU ones. */
- _bfd_elf_merge_object_attributes (ibfd, obfd);
-
-@@ -4298,7 +4325,8 @@
- return TRUE;
- }
- \f
--/* Set htab->tls_get_addr and call the generic ELF tls_setup function. */
-+/* Set plt output section type, htab->tls_get_addr, and call the
-+ generic ELF tls_setup function. */
-
- asection *
- ppc_elf_tls_setup (bfd *obfd, struct bfd_link_info *info)
-@@ -4319,6 +4347,43 @@
- return _bfd_elf_tls_setup (obfd, info);
- }
-
-+/* Return TRUE iff REL is a branch reloc with a global symbol matching
-+ HASH. */
-+
-+static bfd_boolean
-+branch_reloc_hash_match (const bfd *ibfd,
-+ const Elf_Internal_Rela *rel,
-+ const struct elf_link_hash_entry *hash)
-+{
-+ Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (ibfd);
-+ enum elf_ppc_reloc_type r_type = ELF32_R_TYPE (rel->r_info);
-+ unsigned int r_symndx = ELF32_R_SYM (rel->r_info);
-+
-+ if (r_symndx >= symtab_hdr->sh_info
-+ && (r_type == R_PPC_PLTREL24
-+ || r_type == R_PPC_LOCAL24PC
-+ || r_type == R_PPC_REL14
-+ || r_type == R_PPC_REL14_BRTAKEN
-+ || r_type == R_PPC_REL14_BRNTAKEN
-+ || r_type == R_PPC_REL24
-+ || r_type == R_PPC_ADDR24
-+ || r_type == R_PPC_ADDR14
-+ || r_type == R_PPC_ADDR14_BRTAKEN
-+ || r_type == R_PPC_ADDR14_BRNTAKEN))
-+ {
-+ struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (ibfd);
-+ struct elf_link_hash_entry *h;
-+
-+ h = sym_hashes[r_symndx - symtab_hdr->sh_info];
-+ while (h->root.type == bfd_link_hash_indirect
-+ || h->root.type == bfd_link_hash_warning)
-+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
-+ if (h == hash)
-+ return TRUE;
-+ }
-+ return FALSE;
-+}
-+
- /* Run through all the TLS relocs looking for optimization
- opportunities. */
-
-@@ -4446,35 +4511,10 @@
- if (!expecting_tls_get_addr)
- continue;
-
-- if (rel + 1 < relend)
-- {
-- enum elf_ppc_reloc_type r_type2;
-- unsigned long r_symndx2;
-- struct elf_link_hash_entry *h2;
--
-- /* The next instruction should be a call to
-- __tls_get_addr. Peek at the reloc to be sure. */
-- r_type2 = ELF32_R_TYPE (rel[1].r_info);
-- r_symndx2 = ELF32_R_SYM (rel[1].r_info);
-- if (r_symndx2 >= symtab_hdr->sh_info
-- && (r_type2 == R_PPC_REL14
-- || r_type2 == R_PPC_REL14_BRTAKEN
-- || r_type2 == R_PPC_REL14_BRNTAKEN
-- || r_type2 == R_PPC_REL24
-- || r_type2 == R_PPC_PLTREL24))
-- {
-- struct elf_link_hash_entry **sym_hashes;
--
-- sym_hashes = elf_sym_hashes (ibfd);
-- h2 = sym_hashes[r_symndx2 - symtab_hdr->sh_info];
-- while (h2->root.type == bfd_link_hash_indirect
-- || h2->root.type == bfd_link_hash_warning)
-- h2 = ((struct elf_link_hash_entry *)
-- h2->root.u.i.link);
-- if (h2 == htab->tls_get_addr)
-- continue;
-- }
-- }
-+ if (rel + 1 < relend
-+ && branch_reloc_hash_match (ibfd, rel + 1,
-+ htab->tls_get_addr))
-+ continue;
-
- /* Uh oh, we didn't find the expected call. We
- could just mark this symbol to exclude it
-@@ -5573,7 +5613,7 @@
- Elf_Internal_Rela *internal_relocs = NULL;
- Elf_Internal_Rela *irel, *irelend;
- struct one_fixup *fixups = NULL;
-- bfd_boolean changed;
-+ unsigned changes = 0;
- struct ppc_elf_link_hash_table *htab;
- bfd_size_type trampoff;
- asection *got2;
-@@ -5820,6 +5860,7 @@
- fixups = f;
-
- trampoff += size;
-+ changes++;
- }
- else
- {
-@@ -5870,7 +5911,6 @@
- }
-
- /* Write out the trampolines. */
-- changed = fixups != NULL;
- if (fixups != NULL)
- {
- const int *stub;
-@@ -5936,7 +5976,7 @@
- if (contents != NULL
- && elf_section_data (isec)->this_hdr.contents != contents)
- {
-- if (!changed && !link_info->keep_memory)
-+ if (!changes && !link_info->keep_memory)
- free (contents);
- else
- {
-@@ -5945,15 +5985,35 @@
- }
- }
-
-- if (elf_section_data (isec)->relocs != internal_relocs)
-+ if (changes != 0)
- {
-- if (!changed)
-+ /* Append sufficient NOP relocs so we can write out relocation
-+ information for the trampolines. */
-+ Elf_Internal_Rela *new_relocs = bfd_malloc ((changes + isec->reloc_count)
-+ * sizeof (*new_relocs));
-+ unsigned ix;
-+
-+ if (!new_relocs)
-+ goto error_return;
-+ memcpy (new_relocs, internal_relocs,
-+ isec->reloc_count * sizeof (*new_relocs));
-+ for (ix = changes; ix--;)
-+ {
-+ irel = new_relocs + ix + isec->reloc_count;
-+
-+ irel->r_info = ELF32_R_INFO (0, R_PPC_NONE);
-+ }
-+ if (internal_relocs != elf_section_data (isec)->relocs)
- free (internal_relocs);
-- else
-- elf_section_data (isec)->relocs = internal_relocs;
-+ elf_section_data (isec)->relocs = new_relocs;
-+ isec->reloc_count += changes;
-+ elf_section_data (isec)->rel_hdr.sh_size
-+ += changes * elf_section_data (isec)->rel_hdr.sh_entsize;
- }
-+ else if (elf_section_data (isec)->relocs != internal_relocs)
-+ free (internal_relocs);
-
-- *again = changed;
-+ *again = changes != 0;
- return TRUE;
-
- error_return:
-@@ -6321,22 +6381,21 @@
- case R_PPC_GOT_TLSLD16_LO:
- if (tls_mask != 0 && (tls_mask & TLS_LD) == 0)
- {
-- bfd_vma insn1, insn2;
-+ unsigned int insn1, insn2;
- bfd_vma offset;
-
- tls_ldgd_opt:
- offset = rel[1].r_offset;
-- insn1 = bfd_get_32 (output_bfd,
-- contents + rel->r_offset - d_offset);
- if ((tls_mask & tls_gd) != 0)
- {
- /* IE */
-+ insn1 = bfd_get_32 (output_bfd,
-+ contents + rel->r_offset - d_offset);
- insn1 &= (1 << 26) - 1;
- insn1 |= 32 << 26; /* lwz */
- insn2 = 0x7c631214; /* add 3,3,2 */
- rel[1].r_info
- = ELF32_R_INFO (ELF32_R_SYM (rel[1].r_info), R_PPC_NONE);
-- rel[1].r_addend = 0;
- r_type = (((r_type - (R_PPC_GOT_TLSGD16 & 3)) & 3)
- + R_PPC_GOT_TPREL16);
- rel->r_info = ELF32_R_INFO (r_symndx, r_type);
-@@ -6959,6 +7018,17 @@
-
- bfd_put_32 (output_bfd, t0, contents + rel->r_offset);
- bfd_put_32 (output_bfd, t1, contents + rel->r_offset + 4);
-+
-+ /* Rewrite the reloc and convert one of the trailing nop
-+ relocs to describe this relocation. */
-+ BFD_ASSERT (ELF32_R_TYPE (relend[-1].r_info) == R_PPC_NONE);
-+ /* The relocs are at the bottom 2 bytes */
-+ rel[0].r_offset += 2;
-+ memmove (rel + 1, rel, (relend - rel - 1) * sizeof (*rel));
-+ rel[0].r_info = ELF32_R_INFO (r_symndx, R_PPC_ADDR16_HA);
-+ rel[1].r_offset += 4;
-+ rel[1].r_info = ELF32_R_INFO (r_symndx, R_PPC_ADDR16_LO);
-+ rel++;
- }
- continue;
-
-diff -Naur binutils-2.19.1.orig/bfd/elf64-ppc.c binutils-2.19.1/bfd/elf64-ppc.c
---- binutils-2.19.1.orig/bfd/elf64-ppc.c 2008-10-09 05:18:24.000000000 -0700
-+++ binutils-2.19.1/bfd/elf64-ppc.c 2009-03-02 05:55:19.000000000 -0800
-@@ -1,6 +1,6 @@
- /* PowerPC64-specific support for 64-bit ELF.
-- Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
-- Free Software Foundation, Inc.
-+ Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
-+ 2009 Free Software Foundation, Inc.
- Written by Linus Nordberg, Swox AB <info@swox.com>,
- based on elf32-ppc.c by Ian Lance Taylor.
- Largely rewritten by Alan Modra <amodra@bigpond.net.au>
-@@ -2608,9 +2608,15 @@
- long *adjust;
- } opd;
-
-- /* An array for toc sections, indexed by offset/8.
-- Specifies the relocation symbol index used at a given toc offset. */
-- unsigned *t_symndx;
-+ /* An array for toc sections, indexed by offset/8. */
-+ struct _toc_sec_data
-+ {
-+ /* Specifies the relocation symbol index used at a given toc offset. */
-+ unsigned *symndx;
-+
-+ /* And the relocation addend. */
-+ bfd_vma *add;
-+ } toc;
- } u;
-
- enum _ppc64_sec_type sec_type:2;
-@@ -4578,6 +4584,7 @@
- const Elf_Internal_Rela *rel_end;
- asection *sreloc;
- asection **opd_sym_map;
-+ struct elf_link_hash_entry *tga, *dottga;
-
- if (info->relocatable)
- return TRUE;
-@@ -4594,6 +4601,10 @@
- BFD_ASSERT (is_ppc64_elf (abfd));
-
- htab = ppc_hash_table (info);
-+ tga = elf_link_hash_lookup (&htab->elf, "__tls_get_addr",
-+ FALSE, FALSE, TRUE);
-+ dottga = elf_link_hash_lookup (&htab->elf, ".__tls_get_addr",
-+ FALSE, FALSE, TRUE);
- symtab_hdr = &elf_symtab_hdr (abfd);
-
- sym_hashes = elf_sym_hashes (abfd);
-@@ -4829,25 +4840,8 @@
- if (!update_plt_info (abfd, (struct ppc_link_hash_entry *) h,
- rel->r_addend))
- return FALSE;
-- if (h == &htab->tls_get_addr->elf
-- || h == &htab->tls_get_addr_fd->elf)
-+ if (h == tga || h == dottga)
- sec->has_tls_reloc = 1;
-- else if (htab->tls_get_addr == NULL
-- && CONST_STRNEQ (h->root.root.string, ".__tls_get_addr")
-- && (h->root.root.string[15] == 0
-- || h->root.root.string[15] == '@'))
-- {
-- htab->tls_get_addr = (struct ppc_link_hash_entry *) h;
-- sec->has_tls_reloc = 1;
-- }
-- else if (htab->tls_get_addr_fd == NULL
-- && CONST_STRNEQ (h->root.root.string, "__tls_get_addr")
-- && (h->root.root.string[14] == 0
-- || h->root.root.string[14] == '@'))
-- {
-- htab->tls_get_addr_fd = (struct ppc_link_hash_entry *) h;
-- sec->has_tls_reloc = 1;
-- }
- }
- break;
-
-@@ -4891,23 +4885,30 @@
- ppc64_sec = ppc64_elf_section_data (sec);
- if (ppc64_sec->sec_type != sec_toc)
- {
-+ bfd_size_type amt;
-+
- /* One extra to simplify get_tls_mask. */
-- bfd_size_type amt = sec->size * sizeof (unsigned) / 8 + 1;
-- ppc64_sec->u.t_symndx = bfd_zalloc (abfd, amt);
-- if (ppc64_sec->u.t_symndx == NULL)
-+ amt = sec->size * sizeof (unsigned) / 8 + sizeof (unsigned);
-+ ppc64_sec->u.toc.symndx = bfd_zalloc (abfd, amt);
-+ if (ppc64_sec->u.toc.symndx == NULL)
-+ return FALSE;
-+ amt = sec->size * sizeof (bfd_vma) / 8;
-+ ppc64_sec->u.toc.add = bfd_zalloc (abfd, amt);
-+ if (ppc64_sec->u.toc.add == NULL)
- return FALSE;
- BFD_ASSERT (ppc64_sec->sec_type == sec_normal);
- ppc64_sec->sec_type = sec_toc;
- }
- BFD_ASSERT (rel->r_offset % 8 == 0);
-- ppc64_sec->u.t_symndx[rel->r_offset / 8] = r_symndx;
-+ ppc64_sec->u.toc.symndx[rel->r_offset / 8] = r_symndx;
-+ ppc64_sec->u.toc.add[rel->r_offset / 8] = rel->r_addend;
-
- /* Mark the second slot of a GD or LD entry.
- -1 to indicate GD and -2 to indicate LD. */
- if (tls_type == (TLS_EXPLICIT | TLS_TLS | TLS_GD))
-- ppc64_sec->u.t_symndx[rel->r_offset / 8 + 1] = -1;
-+ ppc64_sec->u.toc.symndx[rel->r_offset / 8 + 1] = -1;
- else if (tls_type == (TLS_EXPLICIT | TLS_TLS | TLS_LD))
-- ppc64_sec->u.t_symndx[rel->r_offset / 8 + 1] = -2;
-+ ppc64_sec->u.toc.symndx[rel->r_offset / 8 + 1] = -2;
- goto dodyn;
-
- case R_PPC64_TPREL16:
-@@ -5847,7 +5848,7 @@
- fdh = (struct ppc_link_hash_entry *) fdh->elf.root.u.i.link;
-
- if (fdh == NULL
-- && info->shared
-+ && !info->executable
- && (fh->elf.root.type == bfd_link_hash_undefined
- || fh->elf.root.type == bfd_link_hash_undefweak))
- {
-@@ -5880,7 +5881,7 @@
-
- if (fdh != NULL
- && !fdh->elf.forced_local
-- && (info->shared
-+ && (!info->executable
- || fdh->elf.def_dynamic
- || fdh->elf.ref_dynamic
- || (fdh->elf.root.type == bfd_link_hash_undefweak
-@@ -6258,9 +6259,12 @@
- type suitable for optimization, and 1 otherwise. */
-
- static int
--get_tls_mask (char **tls_maskp, unsigned long *toc_symndx,
-+get_tls_mask (char **tls_maskp,
-+ unsigned long *toc_symndx,
-+ bfd_vma *toc_addend,
- Elf_Internal_Sym **locsymsp,
-- const Elf_Internal_Rela *rel, bfd *ibfd)
-+ const Elf_Internal_Rela *rel,
-+ bfd *ibfd)
- {
- unsigned long r_symndx;
- int next_r;
-@@ -6288,12 +6292,14 @@
- off = sym->st_value;
- off += rel->r_addend;
- BFD_ASSERT (off % 8 == 0);
-- r_symndx = ppc64_elf_section_data (sec)->u.t_symndx[off / 8];
-- next_r = ppc64_elf_section_data (sec)->u.t_symndx[off / 8 + 1];
-- if (!get_sym_h (&h, &sym, &sec, tls_maskp, locsymsp, r_symndx, ibfd))
-- return 0;
-+ r_symndx = ppc64_elf_section_data (sec)->u.toc.symndx[off / 8];
-+ next_r = ppc64_elf_section_data (sec)->u.toc.symndx[off / 8 + 1];
- if (toc_symndx != NULL)
- *toc_symndx = r_symndx;
-+ if (toc_addend != NULL)
-+ *toc_addend = ppc64_elf_section_data (sec)->u.toc.add[off / 8];
-+ if (!get_sym_h (&h, &sym, &sec, tls_maskp, locsymsp, r_symndx, ibfd))
-+ return 0;
- if ((h == NULL
- || ((h->root.type == bfd_link_hash_defined
- || h->root.type == bfd_link_hash_defweak)
-@@ -6898,36 +6904,49 @@
- struct ppc_link_hash_table *htab;
-
- htab = ppc_hash_table (info);
-- if (htab->tls_get_addr != NULL)
-- {
-- struct ppc_link_hash_entry *h = htab->tls_get_addr;
--
-- while (h->elf.root.type == bfd_link_hash_indirect
-- || h->elf.root.type == bfd_link_hash_warning)
-- h = (struct ppc_link_hash_entry *) h->elf.root.u.i.link;
-+ htab->tls_get_addr = ((struct ppc_link_hash_entry *)
-+ elf_link_hash_lookup (&htab->elf, ".__tls_get_addr",
-+ FALSE, FALSE, TRUE));
-+ htab->tls_get_addr_fd = ((struct ppc_link_hash_entry *)
-+ elf_link_hash_lookup (&htab->elf, "__tls_get_addr",
-+ FALSE, FALSE, TRUE));
-+ return _bfd_elf_tls_setup (obfd, info);
-+}
-
-- htab->tls_get_addr = h;
-+/* Return TRUE iff REL is a branch reloc with a global symbol matching
-+ HASH1 or HASH2. */
-
-- if (htab->tls_get_addr_fd == NULL
-- && h->oh != NULL
-- && h->oh->is_func_descriptor
-- && (h->oh->elf.root.type == bfd_link_hash_defined
-- || h->oh->elf.root.type == bfd_link_hash_defweak))
-- htab->tls_get_addr_fd = h->oh;
-- }
-+static bfd_boolean
-+branch_reloc_hash_match (const bfd *ibfd,
-+ const Elf_Internal_Rela *rel,
-+ const struct ppc_link_hash_entry *hash1,
-+ const struct ppc_link_hash_entry *hash2)
-+{
-+ Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (ibfd);
-+ enum elf_ppc64_reloc_type r_type = ELF64_R_TYPE (rel->r_info);
-+ unsigned int r_symndx = ELF64_R_SYM (rel->r_info);
-
-- if (htab->tls_get_addr_fd != NULL)
-+ if (r_symndx >= symtab_hdr->sh_info
-+ && (r_type == R_PPC64_REL24
-+ || r_type == R_PPC64_REL14
-+ || r_type == R_PPC64_REL14_BRTAKEN
-+ || r_type == R_PPC64_REL14_BRNTAKEN
-+ || r_type == R_PPC64_ADDR24
-+ || r_type == R_PPC64_ADDR14
-+ || r_type == R_PPC64_ADDR14_BRTAKEN
-+ || r_type == R_PPC64_ADDR14_BRNTAKEN))
- {
-- struct ppc_link_hash_entry *h = htab->tls_get_addr_fd;
--
-- while (h->elf.root.type == bfd_link_hash_indirect
-- || h->elf.root.type == bfd_link_hash_warning)
-- h = (struct ppc_link_hash_entry *) h->elf.root.u.i.link;
-+ struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (ibfd);
-+ struct elf_link_hash_entry *h;
-
-- htab->tls_get_addr_fd = h;
-+ h = sym_hashes[r_symndx - symtab_hdr->sh_info];
-+ while (h->root.type == bfd_link_hash_indirect
-+ || h->root.type == bfd_link_hash_warning)
-+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
-+ if (h == &hash1->elf || h == &hash2->elf)
-+ return TRUE;
- }
--
-- return _bfd_elf_tls_setup (obfd, info);
-+ return FALSE;
- }
-
- /* Run through all the TLS relocs looking for optimization
-@@ -7173,55 +7192,26 @@
- if (!expecting_tls_get_addr)
- continue;
-
-- if (rel + 1 < relend)
-+ if (rel + 1 < relend
-+ && branch_reloc_hash_match (ibfd, rel + 1,
-+ htab->tls_get_addr,
-+ htab->tls_get_addr_fd))
- {
-- Elf_Internal_Shdr *symtab_hdr;
-- enum elf_ppc64_reloc_type r_type2;
-- unsigned long r_symndx2;
-- struct elf_link_hash_entry *h2;
--
-- symtab_hdr = &elf_symtab_hdr (ibfd);
--
-- /* The next instruction should be a call to
-- __tls_get_addr. Peek at the reloc to be sure. */
-- r_type2 = ELF64_R_TYPE (rel[1].r_info);
-- r_symndx2 = ELF64_R_SYM (rel[1].r_info);
-- if (r_symndx2 >= symtab_hdr->sh_info
-- && (r_type2 == R_PPC64_REL14
-- || r_type2 == R_PPC64_REL14_BRTAKEN
-- || r_type2 == R_PPC64_REL14_BRNTAKEN
-- || r_type2 == R_PPC64_REL24))
-+ if (expecting_tls_get_addr == 2)
- {
-- struct elf_link_hash_entry **sym_hashes;
--
-- sym_hashes = elf_sym_hashes (ibfd);
--
-- h2 = sym_hashes[r_symndx2 - symtab_hdr->sh_info];
-- while (h2->root.type == bfd_link_hash_indirect
-- || h2->root.type == bfd_link_hash_warning)
-- h2 = ((struct elf_link_hash_entry *)
-- h2->root.u.i.link);
-- if (h2 != NULL
-- && (h2 == &htab->tls_get_addr->elf
-- || h2 == &htab->tls_get_addr_fd->elf))
-- {
-- if (expecting_tls_get_addr == 2)
-- {
-- /* Check for toc tls entries. */
-- char *toc_tls;
-- int retval;
--
-- retval = get_tls_mask (&toc_tls, NULL,
-- &locsyms,
-- rel, ibfd);
-- if (retval == 0)
-- goto err_free_rel;
-- if (retval > 1 && toc_tls != NULL)
-- toc_ref[toc_ref_index] = 1;
-- }
-- continue;
-- }
-+ /* Check for toc tls entries. */
-+ char *toc_tls;
-+ int retval;
-+
-+ retval = get_tls_mask (&toc_tls, NULL, NULL,
-+ &locsyms,
-+ rel, ibfd);
-+ if (retval == 0)
-+ goto err_free_rel;
-+ if (retval > 1 && toc_tls != NULL)
-+ toc_ref[toc_ref_index] = 1;
- }
-+ continue;
- }
-
- if (expecting_tls_get_addr != 1)
-@@ -9744,7 +9734,7 @@
- /* Get tls info. */
- char *tls_mask;
-
-- if (!get_tls_mask (&tls_mask, NULL, &local_syms,
-+ if (!get_tls_mask (&tls_mask, NULL, NULL, &local_syms,
- irela - 1, input_bfd))
- goto error_ret_free_internal;
- if (*tls_mask != 0)
-@@ -10236,6 +10226,7 @@
- struct ppc_link_hash_entry *fdh;
- const char *sym_name;
- unsigned long r_symndx, toc_symndx;
-+ bfd_vma toc_addend;
- char tls_mask, tls_gd, tls_type;
- char sym_type;
- bfd_vma relocation;
-@@ -10344,8 +10335,8 @@
- /* Check for toc tls entries. */
- char *toc_tls;
-
-- if (!get_tls_mask (&toc_tls, &toc_symndx, &local_syms,
-- rel, input_bfd))
-+ if (!get_tls_mask (&toc_tls, &toc_symndx, &toc_addend,
-+ &local_syms, rel, input_bfd))
- return FALSE;
-
- if (toc_tls)
-@@ -10407,8 +10398,8 @@
- char *toc_tls;
- int retval;
-
-- retval = get_tls_mask (&toc_tls, &toc_symndx, &local_syms,
-- rel, input_bfd);
-+ retval = get_tls_mask (&toc_tls, &toc_symndx, &toc_addend,
-+ &local_syms, rel, input_bfd);
- if (retval == 0)
- return FALSE;
-
-@@ -10456,6 +10447,7 @@
- if (toc_symndx != 0)
- {
- rel->r_info = ELF64_R_INFO (toc_symndx, r_type);
-+ rel->r_addend = toc_addend;
- /* We changed the symbol. Start over in order to
- get h, sym, sec etc. right. */
- rel--;
-@@ -10509,6 +10501,7 @@
- if (toc_symndx != 0)
- {
- rel->r_info = ELF64_R_INFO (toc_symndx, r_type);
-+ rel->r_addend = toc_addend;
- /* We changed the symbol. Start over in order to
- get h, sym, sec etc. right. */
- rel--;
-@@ -10555,20 +10548,18 @@
- case R_PPC64_GOT_TLSLD16_LO:
- if (tls_mask != 0 && (tls_mask & TLS_LD) == 0)
- {
-- bfd_vma insn1, insn2, insn3;
-+ unsigned int insn1, insn2, insn3;
- bfd_vma offset;
-
- tls_ldgd_opt:
- /* We know that the next reloc is on a tls_get_addr
- call, since ppc64_elf_tls_optimize checks this. */
- offset = rel[1].r_offset;
-- insn1 = bfd_get_32 (output_bfd,
-- contents + rel->r_offset - d_offset);
-- insn3 = bfd_get_32 (output_bfd,
-- contents + offset + 4);
- if ((tls_mask & tls_gd) != 0)
- {
- /* IE */
-+ insn1 = bfd_get_32 (output_bfd,
-+ contents + rel->r_offset - d_offset);
- insn1 &= (1 << 26) - (1 << 2);
- insn1 |= 58 << 26; /* ld */
- insn2 = 0x7c636a14; /* add 3,3,13 */
-@@ -10603,28 +10594,33 @@
- rel->r_addend -= (local_syms[r_symndx].st_value
- + sec->output_offset
- + sec->output_section->vma);
-- rel[1].r_addend = rel->r_addend;
- }
- else if (toc_symndx != 0)
-- r_symndx = toc_symndx;
-+ {
-+ r_symndx = toc_symndx;
-+ rel->r_addend = toc_addend;
-+ }
- r_type = R_PPC64_TPREL16_HA;
- rel->r_info = ELF64_R_INFO (r_symndx, r_type);
- rel[1].r_info = ELF64_R_INFO (r_symndx,
- R_PPC64_TPREL16_LO);
- rel[1].r_offset += d_offset;
-+ rel[1].r_addend = rel->r_addend;
- }
-+ bfd_put_32 (output_bfd, insn1,
-+ contents + rel->r_offset - d_offset);
-+ insn3 = bfd_get_32 (output_bfd,
-+ contents + offset + 4);
- if (insn3 == NOP
- || insn3 == CROR_151515 || insn3 == CROR_313131)
- {
-- insn3 = insn2;
-- insn2 = NOP;
- rel[1].r_offset += 4;
-+ bfd_put_32 (output_bfd, insn2, contents + offset + 4);
-+ insn2 = NOP;
- }
-- bfd_put_32 (output_bfd, insn1,
-- contents + rel->r_offset - d_offset);
- bfd_put_32 (output_bfd, insn2, contents + offset);
-- bfd_put_32 (output_bfd, insn3, contents + offset + 4);
-- if (tls_gd == 0 || toc_symndx != 0)
-+ if ((tls_mask & tls_gd) == 0
-+ && (tls_gd == 0 || toc_symndx != 0))
- {
- /* We changed the symbol. Start over in order
- to get h, sym, sec etc. right. */
-@@ -11001,7 +10997,8 @@
-
- *offp = off | 1;
- if ((info->shared || indx != 0)
-- && (h == NULL
-+ && (offp == &ppc64_tlsld_got (input_bfd)->offset
-+ || h == NULL
- || ELF_ST_VISIBILITY (h->elf.other) == STV_DEFAULT
- || h->elf.root.type != bfd_link_hash_undefweak))
- {
-diff -Naur binutils-2.19.1.orig/bfd/elf.c binutils-2.19.1/bfd/elf.c
---- binutils-2.19.1.orig/bfd/elf.c 2008-12-23 05:54:48.000000000 -0800
-+++ binutils-2.19.1/bfd/elf.c 2009-03-02 05:41:07.000000000 -0800
-@@ -1608,6 +1608,8 @@
-
- if (hdr->sh_entsize != bed->s->sizeof_sym)
- return FALSE;
-+ if (hdr->sh_info * hdr->sh_entsize > hdr->sh_size)
-+ return FALSE;
- BFD_ASSERT (elf_onesymtab (abfd) == 0);
- elf_onesymtab (abfd) = shindex;
- elf_tdata (abfd)->symtab_hdr = *hdr;
-@@ -1863,14 +1865,8 @@
- return TRUE;
-
- case SHT_GROUP:
-- /* We need a BFD section for objcopy and relocatable linking,
-- and it's handy to have the signature available as the section
-- name. */
- if (! IS_VALID_GROUP_SECTION_HEADER (hdr))
- return FALSE;
-- name = group_signature (abfd, hdr);
-- if (name == NULL)
-- return FALSE;
- if (!_bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
- return FALSE;
- if (hdr->contents != NULL)
-@@ -2687,13 +2683,15 @@
- *failedptr = TRUE;
- }
-
--/* Fill in the contents of a SHT_GROUP section. */
-+/* Fill in the contents of a SHT_GROUP section. Called from
-+ _bfd_elf_compute_section_file_positions for gas, objcopy, and
-+ when ELF targets use the generic linker, ld. Called for ld -r
-+ from bfd_elf_final_link. */
-
- void
- bfd_elf_set_group_contents (bfd *abfd, asection *sec, void *failedptrarg)
- {
- bfd_boolean *failedptr = failedptrarg;
-- unsigned long symindx;
- asection *elt, *first;
- unsigned char *loc;
- bfd_boolean gas;
-@@ -2704,20 +2702,49 @@
- || *failedptr)
- return;
-
-- symindx = 0;
-- if (elf_group_id (sec) != NULL)
-- symindx = elf_group_id (sec)->udata.i;
--
-- if (symindx == 0)
-- {
-- /* If called from the assembler, swap_out_syms will have set up
-- elf_section_syms; If called for "ld -r", use target_index. */
-- if (elf_section_syms (abfd) != NULL)
-- symindx = elf_section_syms (abfd)[sec->index]->udata.i;
-- else
-- symindx = sec->target_index;
-+ if (elf_section_data (sec)->this_hdr.sh_info == 0)
-+ {
-+ unsigned long symindx = 0;
-+
-+ /* elf_group_id will have been set up by objcopy and the
-+ generic linker. */
-+ if (elf_group_id (sec) != NULL)
-+ symindx = elf_group_id (sec)->udata.i;
-+
-+ if (symindx == 0)
-+ {
-+ /* If called from the assembler, swap_out_syms will have set up
-+ elf_section_syms. */
-+ BFD_ASSERT (elf_section_syms (abfd) != NULL);
-+ symindx = elf_section_syms (abfd)[sec->index]->udata.i;
-+ }
-+ elf_section_data (sec)->this_hdr.sh_info = symindx;
-+ }
-+ else if (elf_section_data (sec)->this_hdr.sh_info == (unsigned int) -2)
-+ {
-+ /* The ELF backend linker sets sh_info to -2 when the group
-+ signature symbol is global, and thus the index can't be
-+ set until all local symbols are output. */
-+ asection *igroup = elf_sec_group (elf_next_in_group (sec));
-+ struct bfd_elf_section_data *sec_data = elf_section_data (igroup);
-+ unsigned long symndx = sec_data->this_hdr.sh_info;
-+ unsigned long extsymoff = 0;
-+ struct elf_link_hash_entry *h;
-+
-+ if (!elf_bad_symtab (igroup->owner))
-+ {
-+ Elf_Internal_Shdr *symtab_hdr;
-+
-+ symtab_hdr = &elf_tdata (igroup->owner)->symtab_hdr;
-+ extsymoff = symtab_hdr->sh_info;
-+ }
-+ h = elf_sym_hashes (igroup->owner)[symndx - extsymoff];
-+ while (h->root.type == bfd_link_hash_indirect
-+ || h->root.type == bfd_link_hash_warning)
-+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
-+
-+ elf_section_data (sec)->this_hdr.sh_info = h->indx;
- }
-- elf_section_data (sec)->this_hdr.sh_info = symindx;
-
- /* The contents won't be allocated for "ld -r" or objcopy. */
- gas = TRUE;
-@@ -4131,6 +4158,7 @@
- bfd_size_type maxpagesize;
- unsigned int alloc;
- unsigned int i, j;
-+ bfd_vma header_pad = 0;
-
- if (link_info == NULL
- && !_bfd_elf_map_sections_to_segments (abfd, link_info))
-@@ -4138,7 +4166,11 @@
-
- alloc = 0;
- for (m = elf_tdata (abfd)->segment_map; m != NULL; m = m->next)
-- ++alloc;
-+ {
-+ ++alloc;
-+ if (m->header_size)
-+ header_pad = m->header_size;
-+ }
-
- elf_elfheader (abfd)->e_phoff = bed->s->sizeof_ehdr;
- elf_elfheader (abfd)->e_phentsize = bed->s->sizeof_phdr;
-@@ -4156,7 +4188,21 @@
- return TRUE;
- }
-
-- phdrs = bfd_alloc2 (abfd, alloc, sizeof (Elf_Internal_Phdr));
-+ /* We're writing the size in elf_tdata (abfd)->program_header_size,
-+ see assign_file_positions_except_relocs, so make sure we have
-+ that amount allocated, with trailing space cleared.
-+ The variable alloc contains the computed need, while elf_tdata
-+ (abfd)->program_header_size contains the size used for the
-+ layout.
-+ See ld/emultempl/elf-generic.em:gld${EMULATION_NAME}_map_segments
-+ where the layout is forced to according to a larger size in the
-+ last iterations for the testcase ld-elf/header. */
-+ BFD_ASSERT (elf_tdata (abfd)->program_header_size % bed->s->sizeof_phdr
-+ == 0);
-+ phdrs = bfd_zalloc2 (abfd,
-+ (elf_tdata (abfd)->program_header_size
-+ / bed->s->sizeof_phdr),
-+ sizeof (Elf_Internal_Phdr));
- elf_tdata (abfd)->phdr = phdrs;
- if (phdrs == NULL)
- return FALSE;
-@@ -4167,6 +4213,11 @@
-
- off = bed->s->sizeof_ehdr;
- off += alloc * bed->s->sizeof_phdr;
-+ if (header_pad < (bfd_vma) off)
-+ header_pad = 0;
-+ else
-+ header_pad -= off;
-+ off += header_pad;
-
- for (m = elf_tdata (abfd)->segment_map, p = phdrs, j = 0;
- m != NULL;
-@@ -4354,6 +4405,11 @@
-
- p->p_filesz += alloc * bed->s->sizeof_phdr;
- p->p_memsz += alloc * bed->s->sizeof_phdr;
-+ if (m->count)
-+ {
-+ p->p_filesz += header_pad;
-+ p->p_memsz += header_pad;
-+ }
- }
-
- if (p->p_type == PT_LOAD
-@@ -5836,6 +5892,10 @@
- phdr_included = TRUE;
- }
-
-+ if (map->includes_filehdr && first_section)
-+ /* We need to keep the space used by the headers fixed. */
-+ map->header_size = first_section->vma - segment->p_vaddr;
-+
- if (!map->includes_phdrs
- && !map->includes_filehdr
- && map->p_paddr_valid)
-@@ -6004,7 +6064,7 @@
- if (elf_section_flags (isec) & SHF_GROUP)
- elf_section_flags (osec) |= SHF_GROUP;
- elf_next_in_group (osec) = elf_next_in_group (isec);
-- elf_group_name (osec) = elf_group_name (isec);
-+ elf_section_data (osec)->group = elf_section_data (isec)->group;
- }
- }
-
-diff -Naur binutils-2.19.1.orig/bfd/elf-eh-frame.c binutils-2.19.1/bfd/elf-eh-frame.c
---- binutils-2.19.1.orig/bfd/elf-eh-frame.c 2008-09-17 02:00:44.000000000 -0700
-+++ binutils-2.19.1/bfd/elf-eh-frame.c 2009-03-02 05:53:31.000000000 -0800
-@@ -549,16 +549,6 @@
- < (bfd_size_type) ((buf) - ehbuf))) \
- cookie->rel++
-
--#define REQUIRE_CLEARED_RELOCS(buf) \
-- while (cookie->rel < cookie->relend \
-- && (cookie->rel->r_offset \
-- < (bfd_size_type) ((buf) - ehbuf))) \
-- { \
-- REQUIRE (cookie->rel->r_info == 0); \
-- REQUIRE (cookie->rel->r_addend == 0); \
-- cookie->rel++; \
-- }
--
- #define GET_RELOC(buf) \
- ((cookie->rel < cookie->relend \
- && (cookie->rel->r_offset \
-@@ -817,16 +807,16 @@
-
- buf = last_fde + 4 + hdr_length;
-
-- /* Cleared FDE? The instructions will not be cleared but verify all
-- the relocation entries for them are cleared. */
-- if (rsec == NULL)
-- {
-- REQUIRE_CLEARED_RELOCS (buf);
-- }
-- else
-- {
-- SKIP_RELOCS (buf);
-- }
-+ /* For NULL RSEC (cleared FDE belonging to a discarded section)
-+ the relocations are commonly cleared. We do not sanity check if
-+ all these relocations are cleared as (1) relocations to
-+ .gcc_except_table will remain uncleared (they will get dropped
-+ with the drop of this unused FDE) and (2) BFD already safely drops
-+ relocations of any type to .eh_frame by
-+ elf_section_ignore_discarded_relocs.
-+ TODO: The .gcc_except_table entries should be also filtered as
-+ .eh_frame entries; or GCC could rather use COMDAT for them. */
-+ SKIP_RELOCS (buf);
- }
-
- /* Try to interpret the CFA instructions and find the first
-diff -Naur binutils-2.19.1.orig/bfd/elflink.c binutils-2.19.1/bfd/elflink.c
---- binutils-2.19.1.orig/bfd/elflink.c 2008-08-22 01:32:39.000000000 -0700
-+++ binutils-2.19.1/bfd/elflink.c 2009-03-02 05:48:42.000000000 -0800
-@@ -9046,6 +9046,63 @@
- continue;
- }
-
-+ if (finfo->info->relocatable
-+ && (o->flags & (SEC_LINKER_CREATED | SEC_GROUP)) == SEC_GROUP)
-+ {
-+ /* Deal with the group signature symbol. */
-+ struct bfd_elf_section_data *sec_data = elf_section_data (o);
-+ unsigned long symndx = sec_data->this_hdr.sh_info;
-+ asection *osec = o->output_section;
-+
-+ if (symndx >= locsymcount
-+ || (elf_bad_symtab (input_bfd)
-+ && finfo->sections[symndx] == NULL))
-+ {
-+ struct elf_link_hash_entry *h = sym_hashes[symndx - extsymoff];
-+ while (h->root.type == bfd_link_hash_indirect
-+ || h->root.type == bfd_link_hash_warning)
-+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
-+ /* Arrange for symbol to be output. */
-+ h->indx = -2;
-+ elf_section_data (osec)->this_hdr.sh_info = -2;
-+ }
-+ else if (ELF_ST_TYPE (isymbuf[symndx].st_info) == STT_SECTION)
-+ {
-+ /* We'll use the output section target_index. */
-+ asection *sec = finfo->sections[symndx]->output_section;
-+ elf_section_data (osec)->this_hdr.sh_info = sec->target_index;
-+ }
-+ else
-+ {
-+ if (finfo->indices[symndx] == -1)
-+ {
-+ /* Otherwise output the local symbol now. */
-+ Elf_Internal_Sym sym = isymbuf[symndx];
-+ asection *sec = finfo->sections[symndx]->output_section;
-+ const char *name;
-+
-+ name = bfd_elf_string_from_elf_section (input_bfd,
-+ symtab_hdr->sh_link,
-+ sym.st_name);
-+ if (name == NULL)
-+ return FALSE;
-+
-+ sym.st_shndx = _bfd_elf_section_from_bfd_section (output_bfd,
-+ sec);
-+ if (sym.st_shndx == SHN_BAD)
-+ return FALSE;
-+
-+ sym.st_value += o->output_offset;
-+
-+ finfo->indices[symndx] = bfd_get_symcount (output_bfd);
-+ if (! elf_link_output_sym (finfo, name, &sym, o, NULL))
-+ return FALSE;
-+ }
-+ elf_section_data (osec)->this_hdr.sh_info
-+ = finfo->indices[symndx];
-+ }
-+ }
-+
- if ((o->flags & SEC_HAS_CONTENTS) == 0
- || (o->size == 0 && (o->flags & SEC_RELOC) == 0))
- continue;
-@@ -11982,8 +12039,21 @@
- return ret;
- }
-
-+/* For a SHT_GROUP section, return the group signature. For other
-+ sections, return the normal section name. */
-+
-+static const char *
-+section_signature (asection *sec)
-+{
-+ if ((sec->flags & SEC_GROUP) != 0
-+ && elf_next_in_group (sec) != NULL
-+ && elf_group_name (elf_next_in_group (sec)) != NULL)
-+ return elf_group_name (elf_next_in_group (sec));
-+ return sec->name;
-+}
-+
- void
--_bfd_elf_section_already_linked (bfd *abfd, struct bfd_section *sec,
-+_bfd_elf_section_already_linked (bfd *abfd, asection *sec,
- struct bfd_link_info *info)
- {
- flagword flags;
-@@ -12023,7 +12093,7 @@
- causes trouble for MIPS ELF, which relies on link once semantics
- to handle the .reginfo section correctly. */
-
-- name = bfd_get_section_name (abfd, sec);
-+ name = section_signature (sec);
-
- if (CONST_STRNEQ (name, ".gnu.linkonce.")
- && (p = strchr (name + sizeof (".gnu.linkonce.") - 1, '.')) != NULL)
-@@ -12038,7 +12108,7 @@
- /* We may have 2 different types of sections on the list: group
- sections and linkonce sections. Match like sections. */
- if ((flags & SEC_GROUP) == (l->sec->flags & SEC_GROUP)
-- && strcmp (name, l->sec->name) == 0
-+ && strcmp (name, section_signature (l->sec)) == 0
- && bfd_coff_get_comdat_section (l->sec->owner, l->sec) == NULL)
- {
- /* The section has already been linked. See if we should
-@@ -12161,6 +12231,28 @@
- }
- }
-
-+ /* Do not complain on unresolved relocations in `.gnu.linkonce.r.F'
-+ referencing its discarded `.gnu.linkonce.t.F' counterpart - g++-3.4
-+ specific as g++-4.x is using COMDAT groups (without the `.gnu.linkonce'
-+ prefix) instead. `.gnu.linkonce.r.*' were the `.rodata' part of its
-+ matching `.gnu.linkonce.t.*'. If `.gnu.linkonce.r.F' is not discarded
-+ but its `.gnu.linkonce.t.F' is discarded means we chose one-only
-+ `.gnu.linkonce.t.F' section from a different bfd not requiring any
-+ `.gnu.linkonce.r.F'. Thus `.gnu.linkonce.r.F' should be discarded.
-+ The reverse order cannot happen as there is never a bfd with only the
-+ `.gnu.linkonce.r.F' section. The order of sections in a bfd does not
-+ matter as here were are looking only for cross-bfd sections. */
-+
-+ if ((flags & SEC_GROUP) == 0 && CONST_STRNEQ (name, ".gnu.linkonce.r."))
-+ for (l = already_linked_list->entry; l != NULL; l = l->next)
-+ if ((l->sec->flags & SEC_GROUP) == 0
-+ && CONST_STRNEQ (l->sec->name, ".gnu.linkonce.t."))
-+ {
-+ if (abfd != l->sec->owner)
-+ sec->output_section = bfd_abs_section_ptr;
-+ break;
-+ }
-+
- /* This is the first section with this name. Record it. */
- if (! bfd_section_already_linked_table_insert (already_linked_list, sec))
- info->callbacks->einfo (_("%F%P: already_linked_table: %E"));
-diff -Naur binutils-2.19.1.orig/bfd/linker.c binutils-2.19.1/bfd/linker.c
---- binutils-2.19.1.orig/bfd/linker.c 2008-08-16 20:12:49.000000000 -0700
-+++ binutils-2.19.1/bfd/linker.c 2009-03-02 05:32:54.000000000 -0800
-@@ -2796,18 +2796,36 @@
- }
- }
-
-- /* Get and relocate the section contents. */
-- sec_size = (input_section->rawsize > input_section->size
-- ? input_section->rawsize
-- : input_section->size);
-- contents = bfd_malloc (sec_size);
-- if (contents == NULL && sec_size != 0)
-- goto error_return;
-- new_contents = (bfd_get_relocated_section_contents
-- (output_bfd, info, link_order, contents, info->relocatable,
-- _bfd_generic_link_get_symbols (input_bfd)));
-- if (!new_contents)
-- goto error_return;
-+ if ((output_section->flags & (SEC_GROUP | SEC_LINKER_CREATED)) == SEC_GROUP
-+ && input_section->size != 0)
-+ {
-+ /* Group section contents are set by bfd_elf_set_group_contents. */
-+ if (!output_bfd->output_has_begun)
-+ {
-+ /* FIXME: This hack ensures bfd_elf_set_group_contents is called. */
-+ if (!bfd_set_section_contents (output_bfd, output_section, "", 0, 1))
-+ goto error_return;
-+ }
-+ new_contents = output_section->contents;
-+ BFD_ASSERT (new_contents != NULL);
-+ BFD_ASSERT (input_section->output_offset == 0);
-+ }
-+ else
-+ {
-+ /* Get and relocate the section contents. */
-+ sec_size = (input_section->rawsize > input_section->size
-+ ? input_section->rawsize
-+ : input_section->size);
-+ contents = bfd_malloc (sec_size);
-+ if (contents == NULL && sec_size != 0)
-+ goto error_return;
-+ new_contents = (bfd_get_relocated_section_contents
-+ (output_bfd, info, link_order, contents,
-+ info->relocatable,
-+ _bfd_generic_link_get_symbols (input_bfd)));
-+ if (!new_contents)
-+ goto error_return;
-+ }
-
- /* Output the section contents. */
- loc = input_section->output_offset * bfd_octets_per_byte (output_bfd);
-diff -Naur binutils-2.19.1.orig/bfd/Makefile.in binutils-2.19.1/bfd/Makefile.in
---- binutils-2.19.1.orig/bfd/Makefile.in 2009-02-02 02:44:39.000000000 -0800
-+++ binutils-2.19.1/bfd/Makefile.in 2009-07-07 08:52:14.000000000 -0700
-@@ -190,7 +190,7 @@
- PACKAGE_TARNAME = @PACKAGE_TARNAME@
- PACKAGE_VERSION = @PACKAGE_VERSION@
- PATH_SEPARATOR = @PATH_SEPARATOR@
--PKGVERSION = @PKGVERSION@
-+PKGVERSION = (GNU Binutils for Cross-LFS - Retrieved on 20090707)
- POSUB = @POSUB@
- RANLIB = @RANLIB@
- REPORT_BUGS_TEXI = @REPORT_BUGS_TEXI@
-@@ -271,7 +271,7 @@
- ACLOCAL_AMFLAGS = -I . -I .. -I ../config
-
- # Uncomment the following line when doing a release.
--RELEASE = y
-+RELEASE=y
- INCDIR = $(srcdir)/../include
- CSEARCH = -I. -I$(srcdir) -I$(INCDIR)
- MKDEP = gcc -MM
-diff -Naur binutils-2.19.1.orig/bfd/syms.c binutils-2.19.1/bfd/syms.c
---- binutils-2.19.1.orig/bfd/syms.c 2008-06-30 13:51:58.000000000 -0700
-+++ binutils-2.19.1/bfd/syms.c 2009-03-02 05:49:22.000000000 -0800
-@@ -1,6 +1,6 @@
- /* Generic symbol-table support for the BFD library.
- Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-- 2000, 2001, 2002, 2003, 2004, 2007
-+ 2000, 2001, 2002, 2003, 2004, 2007, 2008, 2009
- Free Software Foundation, Inc.
- Written by Cygnus Support.
-
-@@ -1379,10 +1379,11 @@
- {
- size_t len;
-
-- if (info->filename != NULL)
-- free (info->filename);
-+ /* Don't free info->filename here. objdump and other
-+ apps keep a copy of a previously returned file name
-+ pointer. */
- len = strlen (file_name) + 1;
-- info->filename = bfd_malloc (dirlen + len);
-+ info->filename = bfd_alloc (abfd, dirlen + len);
- if (info->filename == NULL)
- return FALSE;
- memcpy (info->filename, directory_name, dirlen);
-diff -Naur binutils-2.19.1.orig/bfd/version.h binutils-2.19.1/bfd/version.h
---- binutils-2.19.1.orig/bfd/version.h 2009-02-02 02:09:26.000000000 -0800
-+++ binutils-2.19.1/bfd/version.h 2009-07-06 17:00:10.000000000 -0700
-@@ -1,4 +1,4 @@
--#define BFD_VERSION_DATE 20090202
-+#define BFD_VERSION_DATE 20090707
- #define BFD_VERSION @bfd_version@
- #define BFD_VERSION_STRING @bfd_version_package@ @bfd_version_string@
- #define REPORT_BUGS_TO @report_bugs_to@
-diff -Naur binutils-2.19.1.orig/binutils/ChangeLog binutils-2.19.1/binutils/ChangeLog
---- binutils-2.19.1.orig/binutils/ChangeLog 2008-12-23 05:54:49.000000000 -0800
-+++ binutils-2.19.1/binutils/ChangeLog 2009-03-02 05:43:13.000000000 -0800
-@@ -1,3 +1,16 @@
-+2009-03-02 Alan Modra <amodra@bigpond.net.au>
-+
-+ 2008-12-04 Ben Elliston <bje@au.ibm.com>
-+ * doc/binutils.texi (objdump): Update booke documentation.
-+ * NEWS: Document user-visible changes to command line options.
-+
-+ 2008-10-10 Nathan Froyd <froydnj@codesourcery.com>
-+ * readelf.c (display_power_gnu_attribute): Decode
-+ Tag_GNU_Power_ABI_Struct_Return.
-+
-+ 2008-09-28 Alan Modra <amodra@bigpond.net.au>
-+ * objcopy.c (setup_section): Set elf_group_id.
-+
- 2008-12-23 Nick Clifton <nickc@redhat.com>
-
- * windmc.c (main): Use correct type for file length.
-diff -Naur binutils-2.19.1.orig/binutils/doc/binutils.texi binutils-2.19.1/binutils/doc/binutils.texi
---- binutils-2.19.1.orig/binutils/doc/binutils.texi 2008-08-05 17:42:17.000000000 -0700
-+++ binutils-2.19.1/binutils/doc/binutils.texi 2009-03-02 05:43:13.000000000 -0800
-@@ -1843,12 +1843,12 @@
- instructs the disassembler to print a mnemonic suffix even when the
- suffix could be inferred by the operands.
-
--For PPC, @option{booke}, @option{booke32} and @option{booke64} select
--disassembly of BookE instructions. @option{32} and @option{64} select
--PowerPC and PowerPC64 disassembly, respectively. @option{e300}
--selects disassembly for the e300 family. @option{440} selects
--disassembly for the PowerPC 440. @option{ppcps} selects disassembly
--for the paired single instructions of the PPC750CL.
-+For PowerPC, @option{booke} controls the disassembly of BookE
-+instructions. @option{32} and @option{64} select PowerPC and
-+PowerPC64 disassembly, respectively. @option{e300} selects
-+disassembly for the e300 family. @option{440} selects disassembly for
-+the PowerPC 440. @option{ppcps} selects disassembly for the paired
-+single instructions of the PPC750CL.
-
- For MIPS, this option controls the printing of instruction mnemonic
- names and register names in disassembled instructions. Multiple
-diff -Naur binutils-2.19.1.orig/binutils/NEWS binutils-2.19.1/binutils/NEWS
---- binutils-2.19.1.orig/binutils/NEWS 2008-09-08 01:56:56.000000000 -0700
-+++ binutils-2.19.1/binutils/NEWS 2009-03-02 05:43:13.000000000 -0800
-@@ -1,5 +1,9 @@
- -*- text -*-
-
-+* Support for PowerPC booke64 instructions has been removed. The assembler no
-+ longer accepts -mbooke32 or -mbooke64 and the disassembler no longer accepts
-+ -Mbooke32 or -Mbooke64. Instead, -mbooke and -Mbooke should be used.
-+
- Changes in 2.19:
-
- * Added -wL switch to dump decoded contents of .debug_line.
-diff -Naur binutils-2.19.1.orig/binutils/objcopy.c binutils-2.19.1/binutils/objcopy.c
---- binutils-2.19.1.orig/binutils/objcopy.c 2008-08-05 17:42:17.000000000 -0700
-+++ binutils-2.19.1/binutils/objcopy.c 2009-03-02 05:31:14.000000000 -0800
-@@ -2344,6 +2344,18 @@
- if (extract_symbol)
- return;
-
-+ if ((isection->flags & SEC_GROUP) != 0)
-+ {
-+ asymbol *gsym = group_signature (isection);
-+
-+ if (gsym != NULL)
-+ {
-+ gsym->flags |= BSF_KEEP;
-+ if (ibfd->xvec->flavour == bfd_target_elf_flavour)
-+ elf_group_id (isection) = gsym;
-+ }
-+ }
-+
- /* Allow the BFD backend to copy any private data it understands
- from the input section to the output section. */
- if (!bfd_copy_private_section_data (ibfd, isection, obfd, osection))
-@@ -2351,13 +2363,6 @@
- err = _("failed to copy private data");
- goto loser;
- }
-- else if ((isection->flags & SEC_GROUP) != 0)
-- {
-- asymbol *gsym = group_signature (isection);
--
-- if (gsym != NULL)
-- gsym->flags |= BSF_KEEP;
-- }
-
- /* All went well. */
- return;
-diff -Naur binutils-2.19.1.orig/binutils/readelf.c binutils-2.19.1/binutils/readelf.c
---- binutils-2.19.1.orig/binutils/readelf.c 2008-09-17 02:00:44.000000000 -0700
-+++ binutils-2.19.1/binutils/readelf.c 2009-03-02 05:35:24.000000000 -0800
-@@ -9062,6 +9062,29 @@
- return p;
- }
-
-+ if (tag == Tag_GNU_Power_ABI_Struct_Return)
-+ {
-+ val = read_uleb128 (p, &len);
-+ p += len;
-+ printf (" Tag_GNU_Power_ABI_Struct_Return: ");
-+ switch (val)
-+ {
-+ case 0:
-+ printf ("Any\n");
-+ break;
-+ case 1:
-+ printf ("r3/r4\n");
-+ break;
-+ case 2:
-+ printf ("Memory\n");
-+ break;
-+ default:
-+ printf ("??? (%d)\n", val);
-+ break;
-+ }
-+ return p;
-+ }
-+
- if (tag & 1)
- type = 1; /* String. */
- else
-diff -Naur binutils-2.19.1.orig/configure.ac binutils-2.19.1/configure.ac
---- binutils-2.19.1.orig/configure.ac 2009-02-02 03:54:49.000000000 -0800
-+++ binutils-2.19.1/configure.ac 2008-09-03 19:18:16.000000000 -0700
-@@ -166,7 +166,7 @@
- # binutils, gas and ld appear in that order because it makes sense to run
- # "make check" in that particular order.
- # If --enable-gold is used, "gold" will replace "ld".
--host_tools="byacc flex bison binutils gas ld fixincludes gcc sid sim gdb make patch prms send-pr gprof etc expect dejagnu ash bash bzip2 m4 autoconf automake libtool diff rcs fileutils shellutils time textutils wdiff find uudecode hello tar gzip indent recode release sed utils guile perl gawk findutils gettext zip fastjar gnattools"
-+host_tools="texinfo byacc flex bison binutils gas ld fixincludes gcc sid sim gdb make patch prms send-pr gprof etc expect dejagnu ash bash bzip2 m4 autoconf automake libtool diff rcs fileutils shellutils time textutils wdiff find uudecode hello tar gzip indent recode release sed utils guile perl gawk findutils gettext zip fastjar gnattools"
-
- # libgcj represents the runtime libraries only used by gcj.
- libgcj="target-libffi \
-diff -Naur binutils-2.19.1.orig/gas/ChangeLog binutils-2.19.1/gas/ChangeLog
---- binutils-2.19.1.orig/gas/ChangeLog 2009-01-14 00:51:14.000000000 -0800
-+++ binutils-2.19.1/gas/ChangeLog 2009-04-01 08:47:36.000000000 -0700
-@@ -1,3 +1,39 @@
-+2009-04-01 Nick Clifton <nickc@redhat.com>
-+
-+ * Import this patch:
-+
-+ 2008-11-14 Peter Jansen <pwjansen@yahoo.com>
-+
-+ PR 7026
-+ * config/tc-arm.c: Ensure that all uses of as_bad have a
-+ formatting string.
-+
-+2009-03-04 Alan Modra <amodra@bigpond.net.au>
-+
-+ * config/tc-ppc.c (md_assemble): APUinfo only for e500.
-+
-+2009-03-02 Alan Modra <amodra@bigpond.net.au>
-+
-+ 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
-+ * config/tc-ppc.c (pre_defined_registers): Add "f32" to "f63",
-+ "f.32" to "f.63", "vs0" to "vs63" and "vs.0" to "vs.63".
-+ (parse_cpu): Extend -mpower7 to accept power7 and isel instructions.
-+
-+ 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
-+ * config/tc-ppc.c (ppc_setup_opcodes): Remove PPC_OPCODE_NOPOWER4 test.
-+ Test the new "deprecated" opcode field.
-+
-+ 2008-12-04 Ben Elliston <bje@au.ibm.com>
-+ * config/tc-ppc.c (parse_cpu): Remove booke64 support. Update
-+ usage strings.
-+ (ppc_setup_opcodes): Likewise, remove booke64 support.
-+ * doc/c-ppc.texi (PowerPC-Opts): Remove -mbooke32 and -mbooke64.
-+ * doc/as.texinfo (Overview): Likewise.
-+
-+ 2008-09-09 Peter Bergner <bergner@vnet.ibm.com>
-+ * config/tc-ppc.c (ppc_setup_opcodes): Simplify POWER4/NOPOWER4 test.
-+ Remove POWER5 and POWER6 tests.
-+
- 2009-01-14 Jakub Jelinek <jakub@redhat.com>
-
- * Makefile.am (ehopt.o): Add struc-symbol.h.
-@@ -132,7 +168,7 @@
- targets.
- * doc/c-i386.texi (i386-Directives): New node. Used to document
- the .lcomm directive.
--
-+
- 2008-08-30 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
-
- * config/tc-hppa.h: Don't define DWARF2_EH_FRAME_READ_ONLY on Linux
-diff -Naur binutils-2.19.1.orig/gas/config/tc-arm.c binutils-2.19.1/gas/config/tc-arm.c
---- binutils-2.19.1.orig/gas/config/tc-arm.c 2008-08-12 16:39:30.000000000 -0700
-+++ binutils-2.19.1/gas/config/tc-arm.c 2009-04-01 08:47:37.000000000 -0700
-@@ -3456,7 +3456,7 @@
-
- if (reg == FAIL)
- {
-- as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
-+ as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
- goto error;
- }
-
-@@ -3470,7 +3470,7 @@
- hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
- if (hi_reg == FAIL)
- {
-- as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
-+ as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
- goto error;
- }
- else if (reg >= hi_reg)
-@@ -3588,7 +3588,7 @@
-
- if (reg == FAIL)
- {
-- as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
-+ as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
- goto error;
- }
-
-@@ -3603,7 +3603,7 @@
- hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
- if (hi_reg == FAIL)
- {
-- as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
-+ as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
- goto error;
- }
- else if (reg >= hi_reg)
-@@ -3709,7 +3709,7 @@
- reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
- if (reg == FAIL)
- {
-- as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
-+ as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
- ignore_rest_of_line ();
- return;
- }
-diff -Naur binutils-2.19.1.orig/gas/config/tc-ppc.c binutils-2.19.1/gas/config/tc-ppc.c
---- binutils-2.19.1.orig/gas/config/tc-ppc.c 2008-08-01 21:38:50.000000000 -0700
-+++ binutils-2.19.1/gas/config/tc-ppc.c 2009-03-03 15:16:02.000000000 -0800
-@@ -1,6 +1,6 @@
- /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000)
- Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-- 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
-+ 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
- Written by Ian Lance Taylor, Cygnus Support.
-
- This file is part of GAS, the GNU Assembler.
-@@ -358,9 +358,42 @@
- { "f.3", 3 },
- { "f.30", 30 },
- { "f.31", 31 },
-+
-+ { "f.32", 32 }, /* Extended floating point scalar registers (ISA 2.06). */
-+ { "f.33", 33 },
-+ { "f.34", 34 },
-+ { "f.35", 35 },
-+ { "f.36", 36 },
-+ { "f.37", 37 },
-+ { "f.38", 38 },
-+ { "f.39", 39 },
- { "f.4", 4 },
-+ { "f.40", 40 },
-+ { "f.41", 41 },
-+ { "f.42", 42 },
-+ { "f.43", 43 },
-+ { "f.44", 44 },
-+ { "f.45", 45 },
-+ { "f.46", 46 },
-+ { "f.47", 47 },
-+ { "f.48", 48 },
-+ { "f.49", 49 },
- { "f.5", 5 },
-+ { "f.50", 50 },
-+ { "f.51", 51 },
-+ { "f.52", 52 },
-+ { "f.53", 53 },
-+ { "f.54", 54 },
-+ { "f.55", 55 },
-+ { "f.56", 56 },
-+ { "f.57", 57 },
-+ { "f.58", 58 },
-+ { "f.59", 59 },
- { "f.6", 6 },
-+ { "f.60", 60 },
-+ { "f.61", 61 },
-+ { "f.62", 62 },
-+ { "f.63", 63 },
- { "f.7", 7 },
- { "f.8", 8 },
- { "f.9", 9 },
-@@ -391,9 +424,42 @@
- { "f3", 3 },
- { "f30", 30 },
- { "f31", 31 },
-+
-+ { "f32", 32 }, /* Extended floating point scalar registers (ISA 2.06). */
-+ { "f33", 33 },
-+ { "f34", 34 },
-+ { "f35", 35 },
-+ { "f36", 36 },
-+ { "f37", 37 },
-+ { "f38", 38 },
-+ { "f39", 39 },
- { "f4", 4 },
-+ { "f40", 40 },
-+ { "f41", 41 },
-+ { "f42", 42 },
-+ { "f43", 43 },
-+ { "f44", 44 },
-+ { "f45", 45 },
-+ { "f46", 46 },
-+ { "f47", 47 },
-+ { "f48", 48 },
-+ { "f49", 49 },
- { "f5", 5 },
-+ { "f50", 50 },
-+ { "f51", 51 },
-+ { "f52", 52 },
-+ { "f53", 53 },
-+ { "f54", 54 },
-+ { "f55", 55 },
-+ { "f56", 56 },
-+ { "f57", 57 },
-+ { "f58", 58 },
-+ { "f59", 59 },
- { "f6", 6 },
-+ { "f60", 60 },
-+ { "f61", 61 },
-+ { "f62", 62 },
-+ { "f63", 63 },
- { "f7", 7 },
- { "f8", 8 },
- { "f9", 9 },
-@@ -501,7 +567,7 @@
- { "srr0", 26 }, /* Machine Status Save/Restore Register 0 */
- { "srr1", 27 }, /* Machine Status Save/Restore Register 1 */
-
-- { "v.0", 0 }, /* Vector registers */
-+ { "v.0", 0 }, /* Vector (Altivec/VMX) registers */
- { "v.1", 1 },
- { "v.10", 10 },
- { "v.11", 11 },
-@@ -567,6 +633,136 @@
- { "v8", 8 },
- { "v9", 9 },
-
-+ { "vs.0", 0 }, /* Vector Scalar (VSX) registers (ISA 2.06). */
-+ { "vs.1", 1 },
-+ { "vs.10", 10 },
-+ { "vs.11", 11 },
-+ { "vs.12", 12 },
-+ { "vs.13", 13 },
-+ { "vs.14", 14 },
-+ { "vs.15", 15 },
-+ { "vs.16", 16 },
-+ { "vs.17", 17 },
-+ { "vs.18", 18 },
-+ { "vs.19", 19 },
-+ { "vs.2", 2 },
-+ { "vs.20", 20 },
-+ { "vs.21", 21 },
-+ { "vs.22", 22 },
-+ { "vs.23", 23 },
-+ { "vs.24", 24 },
-+ { "vs.25", 25 },
-+ { "vs.26", 26 },
-+ { "vs.27", 27 },
-+ { "vs.28", 28 },
-+ { "vs.29", 29 },
-+ { "vs.3", 3 },
-+ { "vs.30", 30 },
-+ { "vs.31", 31 },
-+ { "vs.32", 32 },
-+ { "vs.33", 33 },
-+ { "vs.34", 34 },
-+ { "vs.35", 35 },
-+ { "vs.36", 36 },
-+ { "vs.37", 37 },
-+ { "vs.38", 38 },
-+ { "vs.39", 39 },
-+ { "vs.4", 4 },
-+ { "vs.40", 40 },
-+ { "vs.41", 41 },
-+ { "vs.42", 42 },
-+ { "vs.43", 43 },
-+ { "vs.44", 44 },
-+ { "vs.45", 45 },
-+ { "vs.46", 46 },
-+ { "vs.47", 47 },
-+ { "vs.48", 48 },
-+ { "vs.49", 49 },
-+ { "vs.5", 5 },
-+ { "vs.50", 50 },
-+ { "vs.51", 51 },
-+ { "vs.52", 52 },
-+ { "vs.53", 53 },
-+ { "vs.54", 54 },
-+ { "vs.55", 55 },
-+ { "vs.56", 56 },
-+ { "vs.57", 57 },
-+ { "vs.58", 58 },
-+ { "vs.59", 59 },
-+ { "vs.6", 6 },
-+ { "vs.60", 60 },
-+ { "vs.61", 61 },
-+ { "vs.62", 62 },
-+ { "vs.63", 63 },
-+ { "vs.7", 7 },
-+ { "vs.8", 8 },
-+ { "vs.9", 9 },
-+
-+ { "vs0", 0 },
-+ { "vs1", 1 },
-+ { "vs10", 10 },
-+ { "vs11", 11 },
-+ { "vs12", 12 },
-+ { "vs13", 13 },
-+ { "vs14", 14 },
-+ { "vs15", 15 },
-+ { "vs16", 16 },
-+ { "vs17", 17 },
-+ { "vs18", 18 },
-+ { "vs19", 19 },
-+ { "vs2", 2 },
-+ { "vs20", 20 },
-+ { "vs21", 21 },
-+ { "vs22", 22 },
-+ { "vs23", 23 },
-+ { "vs24", 24 },
-+ { "vs25", 25 },
-+ { "vs26", 26 },
-+ { "vs27", 27 },
-+ { "vs28", 28 },
-+ { "vs29", 29 },
-+ { "vs3", 3 },
-+ { "vs30", 30 },
-+ { "vs31", 31 },
-+ { "vs32", 32 },
-+ { "vs33", 33 },
-+ { "vs34", 34 },
-+ { "vs35", 35 },
-+ { "vs36", 36 },
-+ { "vs37", 37 },
-+ { "vs38", 38 },
-+ { "vs39", 39 },
-+ { "vs4", 4 },
-+ { "vs40", 40 },
-+ { "vs41", 41 },
-+ { "vs42", 42 },
-+ { "vs43", 43 },
-+ { "vs44", 44 },
-+ { "vs45", 45 },
-+ { "vs46", 46 },
-+ { "vs47", 47 },
-+ { "vs48", 48 },
-+ { "vs49", 49 },
-+ { "vs5", 5 },
-+ { "vs50", 50 },
-+ { "vs51", 51 },
-+ { "vs52", 52 },
-+ { "vs53", 53 },
-+ { "vs54", 54 },
-+ { "vs55", 55 },
-+ { "vs56", 56 },
-+ { "vs57", 57 },
-+ { "vs58", 58 },
-+ { "vs59", 59 },
-+ { "vs6", 6 },
-+ { "vs60", 60 },
-+ { "vs61", 61 },
-+ { "vs62", 62 },
-+ { "vs63", 63 },
-+ { "vs7", 7 },
-+ { "vs8", 8 },
-+ { "vs9", 9 },
-+
- { "xer", 1 },
-
- };
-@@ -919,12 +1115,6 @@
- {
- ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32;
- }
-- /* -mbooke64 means enable 64-bit BookE support. */
-- else if (strcmp (arg, "booke64") == 0)
-- {
-- ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE
-- | PPC_OPCODE_BOOKE64 | PPC_OPCODE_64);
-- }
- else if (strcmp (arg, "power4") == 0)
- {
- ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
-@@ -946,8 +1136,9 @@
- else if (strcmp (arg, "power7") == 0)
- {
- ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
-- | PPC_OPCODE_64 | PPC_OPCODE_POWER4
-- | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
-+ | PPC_OPCODE_ISEL | PPC_OPCODE_64
-+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5
-+ | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7
- | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX);
- }
- else if (strcmp (arg, "cell") == 0)
-@@ -1149,8 +1340,7 @@
- fprintf (stream, _("\
- -mppc64, -m620 generate code for PowerPC 620/625/630\n\
- -mppc64bridge generate code for PowerPC 64, including bridge insns\n\
---mbooke64 generate code for 64-bit PowerPC BookE\n\
---mbooke, mbooke32 generate code for 32-bit PowerPC BookE\n\
-+-mbooke generate code for 32-bit PowerPC BookE\n\
- -mpower4 generate code for Power4 architecture\n\
- -mpower5 generate code for Power5 architecture\n\
- -mpower6 generate code for Power6 architecture\n\
-@@ -1359,8 +1549,7 @@
-
- There are also cases where the table needs to be out
- of order to disassemble the correct instruction for
-- processor variants. eg. "lhae" booke64 insn must be
-- found before "ld" ppc64 insn. */
-+ processor variants. */
- else if (0)
- {
- unsigned long t1 = op[0].opcode;
-@@ -1420,23 +1609,7 @@
- || ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64))
- == (ppc_cpu & (PPC_OPCODE_32 | PPC_OPCODE_64)))
- || (ppc_cpu & PPC_OPCODE_64_BRIDGE) != 0)
-- /* Certain instructions (eg: extsw) do not exist in the
-- 32-bit BookE instruction set, but they do exist in the
-- 64-bit BookE instruction set, and other PPC instruction
-- sets. Check to see if the opcode has the BOOKE64 flag set.
-- If it does make sure that the target CPU is not the BookE32. */
-- && ((op->flags & PPC_OPCODE_BOOKE64) == 0
-- || (ppc_cpu & PPC_OPCODE_BOOKE64) == PPC_OPCODE_BOOKE64
-- || (ppc_cpu & PPC_OPCODE_BOOKE) == 0)
-- && ((op->flags & (PPC_OPCODE_POWER4 | PPC_OPCODE_NOPOWER4)) == 0
-- || ((op->flags & PPC_OPCODE_POWER4)
-- == (ppc_cpu & PPC_OPCODE_POWER4)))
-- && ((op->flags & PPC_OPCODE_POWER5) == 0
-- || ((op->flags & PPC_OPCODE_POWER5)
-- == (ppc_cpu & PPC_OPCODE_POWER5)))
-- && ((op->flags & PPC_OPCODE_POWER6) == 0
-- || ((op->flags & PPC_OPCODE_POWER6)
-- == (ppc_cpu & PPC_OPCODE_POWER6))))
-+ && !(ppc_cpu & op->deprecated))
- {
- const char *retval;
-
-@@ -2792,10 +2965,7 @@
-
- #ifdef OBJ_ELF
- /* Do we need/want a APUinfo section? */
-- if (ppc_cpu & (PPC_OPCODE_SPE
-- | PPC_OPCODE_ISEL | PPC_OPCODE_EFS
-- | PPC_OPCODE_BRLOCK | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
-- | PPC_OPCODE_RFMCI))
-+ if ((ppc_cpu & PPC_OPCODE_E500MC) != 0)
- {
- /* These are all version "1". */
- if (opcode->flags & PPC_OPCODE_SPE)
-diff -Naur binutils-2.19.1.orig/gas/doc/as.texinfo binutils-2.19.1/gas/doc/as.texinfo
---- binutils-2.19.1.orig/gas/doc/as.texinfo 2008-10-02 01:07:17.000000000 -0700
-+++ binutils-2.19.1/gas/doc/as.texinfo 2009-03-02 05:43:14.000000000 -0800
-@@ -409,8 +409,7 @@
-
- @emph{Target PowerPC options:}
- [@b{-mpwrx}|@b{-mpwr2}|@b{-mpwr}|@b{-m601}|@b{-mppc}|@b{-mppc32}|@b{-m603}|@b{-m604}|
-- @b{-m403}|@b{-m405}|@b{-mppc64}|@b{-m620}|@b{-mppc64bridge}|@b{-mbooke}|
-- @b{-mbooke32}|@b{-mbooke64}]
-+ @b{-m403}|@b{-m405}|@b{-mppc64}|@b{-m620}|@b{-mppc64bridge}|@b{-mbooke}]
- [@b{-mcom}|@b{-many}|@b{-maltivec}|@b{-mvsx}] [@b{-memb}]
- [@b{-mregnames}|@b{-mno-regnames}]
- [@b{-mrelocatable}|@b{-mrelocatable-lib}]
-diff -Naur binutils-2.19.1.orig/gas/doc/c-ppc.texi binutils-2.19.1/gas/doc/c-ppc.texi
---- binutils-2.19.1.orig/gas/doc/c-ppc.texi 2008-08-01 21:38:50.000000000 -0700
-+++ binutils-2.19.1/gas/doc/c-ppc.texi 2009-03-02 05:43:14.000000000 -0800
-@@ -70,10 +70,7 @@
- @item -mppc64bridge
- Generate code for PowerPC 64, including bridge insns.
-
--@item -mbooke64
--Generate code for 64-bit BookE.
--
--@item -mbooke, mbooke32
-+@item -mbooke
- Generate code for 32-bit BookE.
-
- @item -me300
-diff -Naur binutils-2.19.1.orig/gas/testsuite/ChangeLog binutils-2.19.1/gas/testsuite/ChangeLog
---- binutils-2.19.1.orig/gas/testsuite/ChangeLog 2009-01-14 00:49:59.000000000 -0800
-+++ binutils-2.19.1/gas/testsuite/ChangeLog 2009-03-02 05:59:36.000000000 -0800
-@@ -1,3 +1,56 @@
-+2009-03-02 Alan Modra <amodra@bigpond.net.au>
-+
-+ 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
-+ * gas/ppc/e500mc.d ("wait", "waitsrv", "waitimpl"): Add tests.
-+ * gas/ppc/e500mc.s: Likewise.
-+ * gas/ppc/power6.d ("cdtbcd", "cbcdtd", "addg6s"): Add tests.
-+ * gas/ppc/power6.s: Likewise.
-+ * gas/ppc/power7.d ("lfdpx", "mffgpr", "mftgpr"): Remove invalid tests.
-+ ("wait", "waitsrv", "waitimpl", "divwe", "divwe.", "divweo", "divweo.",
-+ "divweu", "divweu.", "divweuo", "divweuo.", "bpermd", "popcntw",
-+ "popcntd", "ldbrx", "stdbrx", "lfiwzx", "lfiwzx", "fcfids", "fcfids.",
-+ "fcfidus", "fcfidus.", "fctiwu", "fctiwu.", "fctiwuz", "fctiwuz.",
-+ "fctidu", "fctidu.", "fctiduz", "fctiduz.", "fcfidu", "fcfidu.",
-+ "ftdiv", "ftdiv", "ftsqrt", "ftsqrt", "dcbtt", "dcbtstt", "dcffix",
-+ "dcffix.", "lbarx", "lbarx", "lbarx", "lharx", "lharx", "lharx",
-+ "stbcx.", "sthcx.", "fre", "fre.", "fres", "fres.", "frsqrte",
-+ "frsqrte.", "frsqrtes", "frsqrtes.", "isel"): Add tests.
-+ * gas/ppc/power7.s: Likewise.
-+ * gas/ppc/vsx.d: New test.
-+ * gas/ppc/vsx.s: Likewise.
-+ * gas/ppc/ppc.exp: Run it.
-+
-+ 2009-02-19 Peter Bergner <bergner@vnet.ibm.com>
-+ * gas/ppc/e500mc.d ("lfdepx", "stfdepx"): Fix tests to expect a
-+ floating point register.
-+
-+ 2009-02-05 Peter Bergner <bergner@vnet.ibm.com>
-+ * gas/ppc/booke.s ("dcbt", "dcbtst"): New tests.
-+ * gas/ppc/booke.d: Likewise.
-+ * gas/ppc/power4_32.s: Likewise.
-+ * gas/ppc/power4_32.d: Likewise.
-+
-+ 2009-01-14 Peter Bergner <bergner@vnet.ibm.com>
-+ * gas/ppc/power6.s ("mtfsf", "mtfsf.", "mtfsfi", "mtfsfi."): Add tests.
-+ * gas/ppc/power6.d: Likewise.
-+
-+ 2008-12-04 Ben Elliston <bje@au.ibm.com>
-+ * gas/ppc/booke.s: Remove booke64 instructions.
-+ * gas/ppc/booke.d: Update expected disassembly output.
-+ * gas/ppc/booke_xcoff.s: Use -mbooke/-Mbooke.
-+ * gas/ppc/booke_xcoff.d: Likewise.
-+ * gas/ppc/booke_xcoff64.d: Likewise.
-+ * gas/ppc/booke_xcoff64.s: Likewise.
-+
-+ 2008-09-09 Peter Bergner <bergner@vnet.ibm.com>
-+ * gas/ppc/common.s: New test.
-+ * gas/ppc/common.d: Likewise.
-+ * gas/ppc/power4_32.s: Likewise.
-+ * gas/ppc/power4_32.d: Likewise.
-+ * gas/ppc/power6.s: Add attn, mtcr, mtcrf, mfcr, dcbz.
-+ * gas/ppc/power6.d: Likewise.
-+ * gas/ppc/ppc.exp: Run power4_32 test.
-+
- 2009-01-08 Adam Nemet <anemet@caviumnetworks.com>
-
- * gas/mips/mips1-fp.s, gas/mips/mips1-fp.d, gas/mips/mips1-fp.l:
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke.d binutils-2.19.1/gas/testsuite/gas/ppc/booke.d
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke.d 2007-04-18 16:58:12.000000000 -0700
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/booke.d 2009-03-02 05:54:22.000000000 -0800
-@@ -1,4 +1,4 @@
--#as: -mbooke64
-+#as: -mbooke
- #objdump: -dr -Mbooke
- #name: BookE tests
-
-@@ -6,151 +6,38 @@
-
- Disassembly of section \.text:
-
--0+0000000 <start>:
-- 0: 24 25 00 30 bce 1,4\*cr1\+gt,30 <branch_target_1>
-- 4: 24 46 00 3d bcel 2,4\*cr1\+eq,40 <branch_target_2>
-- 8: 24 67 00 52 bcea 3,4\*cr1\+so,50 <branch_target_3>
-- 8: R_PPC(64)?_ADDR14 \.text\+0x50
-- c: 24 88 00 73 bcela 4,4\*cr2\+lt,70 <branch_target_4>
-- c: R_PPC(64)?_ADDR14 \.text\+0x70
-- 10: 4c a9 00 22 bclre 5,4\*cr2\+gt
-- 14: 4c aa 00 23 bclrel 5,4\*cr2\+eq
-- 18: 4d 0b 04 22 bcctre 8,4\*cr2\+so
-- 1c: 4d 0c 04 23 bcctrel 8,4\*cr3\+lt
-- 20: 58 00 00 74 be 94 <branch_target_5>
-- 24: 58 00 00 89 bel ac <branch_target_6>
-- 28: 58 00 00 f6 bea f4 <branch_target_7>
-- 28: R_PPC(64)?_ADDR24 \.text\+0xf4
-- 2c: 58 00 01 2b bela 128 <branch_target_8>
-- 2c: R_PPC(64)?_ADDR24 \.text\+0x128
--
--0+0000030 <branch_target_1>:
-- 30: e9 09 00 80 lbze r8,8\(r9\)
-- 34: e9 8f 00 41 lbzue r12,4\(r15\)
-- 38: 7c 86 40 fe lbzuxe r4,r6,r8
-- 3c: 7c 65 38 be lbzxe r3,r5,r7
--
--0+0000040 <branch_target_2>:
-- 40: f8 a6 06 40 lde r5,400\(r6\)
-- 44: f8 c7 07 11 ldue r6,452\(r7\)
-- 48: 7c e8 4e 3e ldxe r7,r8,r9
-- 4c: 7d 4b 66 7e lduxe r10,r11,r12
--
--0+0000050 <branch_target_3>:
-- 50: f9 81 02 06 lfde f12,128\(r1\)
-- 54: f8 25 00 47 lfdue f1,16\(r5\)
-- 58: 7c a1 1c be lfdxe f5,r1,r3
-- 5c: 7c c2 24 fe lfduxe f6,r2,r4
-- 60: f9 09 00 c4 lfse f8,48\(r9\)
-- 64: f9 2a 01 15 lfsue f9,68\(r10\)
-- 68: 7d 44 44 7e lfsuxe f10,r4,r8
-- 6c: 7d 23 3c 3e lfsxe f9,r3,r7
--
--0+0000070 <branch_target_4>:
-- 70: e9 45 03 24 lhae r10,50\(r5\)
-- 74: e8 23 00 55 lhaue r1,5\(r3\)
-- 78: 7c a1 1a fe lhauxe r5,r1,r3
-- 7c: 7f be fa be lhaxe r29,r30,r31
-- 80: 7c 22 1e 3c lhbrxe r1,r2,r3
-- 84: e8 83 01 22 lhze r4,18\(r3\)
-- 88: e8 c9 01 43 lhzue r6,20\(r9\)
-- 8c: 7c a7 4a 7e lhzuxe r5,r7,r9
-- 90: 7d 27 2a 3e lhzxe r9,r7,r5
--
--0+0000094 <branch_target_5>:
-- 94: 7d 4f a0 fc lwarxe r10,r15,r20
-- 98: 7c aa 94 3c lwbrxe r5,r10,r18
-- 9c: eb 9d 00 46 lwze r28,4\(r29\)
-- a0: e9 0a 02 87 lwzue r8,40\(r10\)
-- a4: 7c 66 48 7e lwzuxe r3,r6,r9
-- a8: 7f dd e0 3e lwzxe r30,r29,r28
--
--0+00000ac <branch_target_6>:
-- ac: 7c 06 3d fc dcbae r6,r7
-- b0: 7c 08 48 bc dcbfe r8,r9
-- b4: 7c 0a 5b bc dcbie r10,r11
-- b8: 7c 08 f0 7c dcbste r8,r30
-- bc: 7c c3 0a 3c dcbte 6,r3,r1
-- c0: 7c a4 11 fa dcbtste 5,r4,r2
-- c4: 7c 0f 77 fc dcbze r15,r14
-- c8: 7c 03 27 bc icbie r3,r4
-- cc: 7c a8 48 2c icbt 5,r8,r9
-- d0: 7c ca 78 3c icbte 6,r10,r15
-- d4: 7c a6 02 26 mfapidi r5,r6
-- d8: 7c 07 46 24 tlbivax r7,r8
-- dc: 7c 09 56 26 tlbivaxe r9,r10
-- e0: 7c 0b 67 24 tlbsx r11,r12
-- e4: 7c 0d 77 26 tlbsxe r13,r14
-- e8: 7c 00 07 a4 tlbwe
-- ec: 7c 00 07 a4 tlbwe
-- f0: 7c 21 0f a4 tlbwe r1,r1,1
--
--0+00000f4 <branch_target_7>:
-- f4: 7c 22 1b 14 adde64 r1,r2,r3
-- f8: 7c 85 37 14 adde64o r4,r5,r6
-- fc: 7c e8 03 d4 addme64 r7,r8
-- 100: 7d 2a 07 d4 addme64o r9,r10
-- 104: 7d 6c 03 94 addze64 r11,r12
-- 108: 7d ae 07 94 addze64o r13,r14
-- 10c: 7e 80 04 40 mcrxr64 cr5
-- 110: 7d f0 8b 10 subfe64 r15,r16,r17
-- 114: 7e 53 a7 10 subfe64o r18,r19,r20
-- 118: 7e b6 03 d0 subfme64 r21,r22
-- 11c: 7e f8 07 d0 subfme64o r23,r24
-- 120: 7f 3a 03 90 subfze64 r25,r26
-- 124: 7f 7c 07 90 subfze64o r27,r28
--
--0+0000128 <branch_target_8>:
-- 128: e8 22 03 28 stbe r1,50\(r2\)
-- 12c: e8 64 02 89 stbue r3,40\(r4\)
-- 130: 7c a6 39 fe stbuxe r5,r6,r7
-- 134: 7d 09 51 be stbxe r8,r9,r10
-- 138: 7d 6c 6b ff stdcxe\. r11,r12,r13
-- 13c: f9 cf 00 78 stde r14,28\(r15\)
-- 140: fa 11 00 59 stdue r16,20\(r17\)
-- 144: 7e 53 a7 3e stdxe r18,r19,r20
-- 148: 7e b6 bf 7e stduxe r21,r22,r23
-- 14c: f8 38 00 3e stfde f1,12\(r24\)
-- 150: f8 59 00 0f stfdue f2,0\(r25\)
-- 154: 7c 7a dd be stfdxe f3,r26,r27
-- 158: 7c 9c ed fe stfduxe f4,r28,r29
-- 15c: 7c be ff be stfiwxe f5,r30,r31
-- 160: f8 de 00 6c stfse f6,24\(r30\)
-- 164: f8 fd 00 5d stfsue f7,20\(r29\)
-- 168: 7d 1c dd 3e stfsxe f8,r28,r27
-- 16c: 7d 3a cd 7e stfsuxe f9,r26,r25
-- 170: 7f 17 b7 3c sthbrxe r24,r23,r22
-- 174: ea b4 01 ea sthe r21,30\(r20\)
-- 178: ea 72 02 8b sthue r19,40\(r18\)
-- 17c: 7e 30 7b 7e sthuxe r17,r16,r15
-- 180: 7d cd 63 3e sthxe r14,r13,r12
-- 184: 7d 6a 4d 3c stwbrxe r11,r10,r9
-- 188: 7d 07 31 3d stwcxe\. r8,r7,r6
-- 18c: e8 a4 03 2e stwe r5,50\(r4\)
-- 190: e8 62 02 8f stwue r3,40\(r2\)
-- 194: 7c 22 19 7e stwuxe r1,r2,r3
-- 198: 7c 85 31 3e stwxe r4,r5,r6
-- 19c: 4c 00 00 66 rfci
-- 1a0: 7c 60 01 06 wrtee r3
-- 1a4: 7c 00 81 46 wrteei 1
-- 1a8: 7c 85 02 06 mfdcrx r4,r5
-- 1ac: 7c aa 3a 86 mfdcr r5,234
-- 1b0: 7c e6 03 06 mtdcrx r6,r7
-- 1b4: 7d 10 6b 86 mtdcr 432,r8
-- 1b8: 7c 00 04 ac msync
-- 1bc: 7c 09 55 ec dcba r9,r10
-- 1c0: 7c 00 06 ac mbar
-- 1c4: 7c 00 06 ac mbar
-- 1c8: 7c 20 06 ac mbar 1
-- 1cc: 7d 8d 77 24 tlbsx r12,r13,r14
-- 1d0: 7d 8d 77 25 tlbsx\. r12,r13,r14
-- 1d4: 7d 8d 77 26 tlbsxe r12,r13,r14
-- 1d8: 7d 8d 77 27 tlbsxe\. r12,r13,r14
-- 1dc: 7c 12 42 a6 mfsprg r0,2
-- 1e0: 7c 12 42 a6 mfsprg r0,2
-- 1e4: 7c 12 43 a6 mtsprg 2,r0
-- 1e8: 7c 12 43 a6 mtsprg 2,r0
-- 1ec: 7c 07 42 a6 mfsprg r0,7
-- 1f0: 7c 07 42 a6 mfsprg r0,7
-- 1f4: 7c 17 43 a6 mtsprg 7,r0
-- 1f8: 7c 17 43 a6 mtsprg 7,r0
-+0+0000000 <branch_target_1>:
-+ 0: 7c a8 48 2c icbt 5,r8,r9
-+ 4: 7c a6 02 26 mfapidi r5,r6
-+ 8: 7c 07 46 24 tlbivax r7,r8
-+ c: 7c 0b 67 24 tlbsx r11,r12
-+ 10: 7c 00 07 a4 tlbwe
-+ 14: 7c 00 07 a4 tlbwe
-+ 18: 7c 21 0f a4 tlbwe r1,r1,1
-+
-+0+000001c <branch_target_2>:
-+ 1c: 4c 00 00 66 rfci
-+ 20: 7c 60 01 06 wrtee r3
-+ 24: 7c 00 81 46 wrteei 1
-+ 28: 7c 85 02 06 mfdcrx r4,r5
-+ 2c: 7c aa 3a 86 mfdcr r5,234
-+ 30: 7c e6 03 06 mtdcrx r6,r7
-+ 34: 7d 10 6b 86 mtdcr 432,r8
-+ 38: 7c 00 04 ac msync
-+ 3c: 7c 09 55 ec dcba r9,r10
-+ 40: 7c 00 06 ac mbar
-+ 44: 7c 00 06 ac mbar
-+ 48: 7c 20 06 ac mbar 1
-+ 4c: 7d 8d 77 24 tlbsx r12,r13,r14
-+ 50: 7d 8d 77 25 tlbsx\. r12,r13,r14
-+ 54: 7c 12 42 a6 mfsprg r0,2
-+ 58: 7c 12 42 a6 mfsprg r0,2
-+ 5c: 7c 12 43 a6 mtsprg 2,r0
-+ 60: 7c 12 43 a6 mtsprg 2,r0
-+ 64: 7c 07 42 a6 mfsprg r0,7
-+ 68: 7c 07 42 a6 mfsprg r0,7
-+ 6c: 7c 17 43 a6 mtsprg 7,r0
-+ 70: 7c 17 43 a6 mtsprg 7,r0
-+ 74: 7c 05 32 2c dcbt r5,r6
-+ 78: 7c 05 32 2c dcbt r5,r6
-+ 7c: 7d 05 32 2c dcbt 8,r5,r6
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke.s binutils-2.19.1/gas/testsuite/gas/ppc/booke.s
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke.s 2007-04-18 16:58:12.000000000 -0700
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/booke.s 2009-03-02 05:54:22.000000000 -0800
-@@ -1,127 +1,17 @@
- # Motorola PowerPC BookE tests
--#as: -mbooke32
-+#as: -mbooke
- .section ".text"
--start:
-- bce 1, 5, branch_target_1
-- bcel 2, 6, branch_target_2
-- bcea 3, 7, branch_target_3
-- bcela 4, 8, branch_target_4
-- bclre 5, 9
-- bclrel 5, 10
-- bcctre 8, 11
-- bcctrel 8, 12
-- be branch_target_5
-- bel branch_target_6
-- bea branch_target_7
-- bela branch_target_8
-
--branch_target_1:
-- lbze 8, 8(9)
-- lbzue 12, 4(15)
-- lbzuxe 4, 6, 8
-- lbzxe 3, 5, 7
--
--branch_target_2:
-- lde 5, 400(6)
-- ldue 6, 452(7)
-- ldxe 7, 8, 9
-- lduxe 10, 11, 12
--
--branch_target_3:
-- lfde 12, 128(1)
-- lfdue 1, 16(5)
-- lfdxe 5, 1, 3
-- lfduxe 6, 2, 4
-- lfse 8, 48(9)
-- lfsue 9, 68(10)
-- lfsuxe 10, 4, 8
-- lfsxe 9, 3, 7
--
--branch_target_4:
-- lhae 10, 50(5)
-- lhaue 1, 5(3)
-- lhauxe 5, 1, 3
-- lhaxe 29, 30, 31
-- lhbrxe 1, 2, 3
-- lhze 4, 18(3)
-- lhzue 6, 20(9)
-- lhzuxe 5, 7, 9
-- lhzxe 9, 7, 5
--
--branch_target_5:
-- lwarxe 10, 15, 20
-- lwbrxe 5, 10, 18
-- lwze 28, 4(29)
-- lwzue 8, 40(10)
-- lwzuxe 3, 6, 9
-- lwzxe 30, 29, 28
--
--branch_target_6:
-- dcbae 6, 7
-- dcbfe 8, 9
-- dcbie 10, 11
-- dcbste 8, 30
-- dcbte 6, 3, 1
-- dcbtste 5, 4, 2
-- dcbze 15, 14
-- icbie 3, 4
-+branch_target_1:
- icbt 5, 8, 9
-- icbte 6, 10, 15
- mfapidi 5, 6
- tlbivax 7, 8
-- tlbivaxe 9, 10
- tlbsx 11, 12
-- tlbsxe 13, 14
- tlbwe
- tlbwe 0,0,0
- tlbwe 1,1,1
-
--branch_target_7:
-- adde64 1, 2, 3
-- adde64o 4, 5, 6
-- addme64 7, 8
-- addme64o 9, 10
-- addze64 11, 12
-- addze64o 13, 14
-- mcrxr64 5
-- subfe64 15, 16, 17
-- subfe64o 18, 19, 20
-- subfme64 21, 22
-- subfme64o 23, 24
-- subfze64 25, 26
-- subfze64o 27, 28
--
--branch_target_8:
-- stbe 1, 50(2)
-- stbue 3, 40(4)
-- stbuxe 5, 6, 7
-- stbxe 8, 9, 10
-- stdcxe. 11, 12, 13
-- stde 14, 28(15)
-- stdue 16, 20(17)
-- stdxe 18, 19, 20
-- stduxe 21, 22, 23
-- stfde 1, 12(24)
-- stfdue 2, 0(25)
-- stfdxe 3, 26, 27
-- stfduxe 4, 28, 29
-- stfiwxe 5, 30, 31
-- stfse 6, 24(30)
-- stfsue 7, 20(29)
-- stfsxe 8, 28, 27
-- stfsuxe 9, 26, 25
-- sthbrxe 24, 23, 22
-- sthe 21, 30(20)
-- sthue 19, 40(18)
-- sthuxe 17, 16, 15
-- sthxe 14, 13, 12
-- stwbrxe 11, 10, 9
-- stwcxe. 8, 7, 6
-- stwe 5, 50(4)
-- stwue 3, 40(2)
-- stwuxe 1, 2, 3
-- stwxe 4, 5, 6
--
-+branch_target_2:
- rfci
- wrtee 3
- wrteei 1
-@@ -137,8 +27,6 @@
-
- tlbsx 12, 13, 14
- tlbsx. 12, 13, 14
-- tlbsxe 12, 13, 14
-- tlbsxe. 12, 13, 14
-
- mfsprg 0, 2
- mfsprg2 0
-@@ -148,3 +36,7 @@
- mfsprg7 0
- mtsprg 7, 0
- mtsprg7 0
-+
-+ dcbt 5,6
-+ dcbt 0,5,6
-+ dcbt 8,5,6
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke_xcoff64.d binutils-2.19.1/gas/testsuite/gas/ppc/booke_xcoff64.d
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke_xcoff64.d 2007-10-01 09:24:40.000000000 -0700
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/booke_xcoff64.d 2009-03-02 05:43:14.000000000 -0800
-@@ -1,5 +1,5 @@
--#as: -a64 -mppc64 -mbooke64
--#objdump: -dr -Mbooke64
-+#as: -a64 -mppc64 -mbooke
-+#objdump: -dr -Mbooke
- #name: xcoff64 BookE tests
-
- .*: file format aix5?coff64-rs6000
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke_xcoff64.s binutils-2.19.1/gas/testsuite/gas/ppc/booke_xcoff64.s
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke_xcoff64.s 2007-10-01 09:24:40.000000000 -0700
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/booke_xcoff64.s 2009-03-02 05:43:15.000000000 -0800
-@@ -1,5 +1,5 @@
- # Motorola PowerPC BookE tests
--#as: -a64 -mppc64 -mbooke64
-+#as: -a64 -mppc64 -mbooke
- .csect .text[PR]
- .csect main[DS]
- main:
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke_xcoff.d binutils-2.19.1/gas/testsuite/gas/ppc/booke_xcoff.d
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke_xcoff.d 2007-10-01 09:24:40.000000000 -0700
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/booke_xcoff.d 2009-03-02 05:43:14.000000000 -0800
-@@ -1,5 +1,5 @@
--#as: -mppc32 -mbooke32
--#objdump: -mpowerpc -dr -Mbooke32
-+#as: -mppc32 -mbooke
-+#objdump: -mpowerpc -dr -Mbooke
- #name: xcoff BookE tests
-
- .*: file format aixcoff-rs6000
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke_xcoff.s binutils-2.19.1/gas/testsuite/gas/ppc/booke_xcoff.s
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke_xcoff.s 2007-10-01 09:24:40.000000000 -0700
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/booke_xcoff.s 2009-03-02 05:43:14.000000000 -0800
-@@ -1,5 +1,5 @@
- # Motorola PowerPC BookE tests
--#as: -mbooke32
-+#as: -mbooke
- .csect .text[PR]
- .csect main[DS]
- main:
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/common.d binutils-2.19.1/gas/testsuite/gas/ppc/common.d
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/common.d 1969-12-31 16:00:00.000000000 -0800
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/common.d 2009-03-02 05:37:44.000000000 -0800
-@@ -0,0 +1,190 @@
-+#objdump: -d -Mcom
-+#as: -a32 -mcom
-+#name: PowerPC COMMON instructions
-+
-+.*: +file format elf32-powerpc.*
-+
-+Disassembly of section \.text:
-+
-+0+00 <start>:
-+
-+ 0: 7c 83 28 39 and. r3,r4,r5
-+ 4: 7c 83 28 38 and r3,r4,r5
-+ 8: 7d cd 78 78 andc r13,r14,r15
-+ c: 7e 30 90 79 andc. r16,r17,r18
-+ 10: 48 00 00 02 ba 0 <start>
-+ 14: 40 01 00 00 bdnzf- gt,14 <start\+0x14>
-+ 18: 40 85 00 02 blea- cr1,0 <start>
-+ 1c: 40 43 00 01 bdzfl- so,1c <start\+0x1c>
-+ 20: 41 47 00 03 bdztla- 4\*cr1\+so,0 <start>
-+ 24: 4e 80 04 20 bctr
-+ 28: 4e 80 04 21 bctrl
-+ 2c: 42 40 00 02 bdza- 0 <start>
-+ 30: 42 40 00 00 bdz- 30 <start\+0x30>
-+ 34: 42 40 00 03 bdzla- 0 <start>
-+ 38: 42 40 00 01 bdzl- 38 <start\+0x38>
-+ 3c: 41 82 00 00 beq- 3c <start\+0x3c>
-+ 40: 41 8a 00 02 beqa- cr2,0 <start>
-+ 44: 41 86 00 01 beql- cr1,44 <start\+0x44>
-+ 48: 41 8e 00 03 beqla- cr3,0 <start>
-+ 4c: 40 80 00 00 bge- 4c <start\+0x4c>
-+ 50: 40 90 00 02 bgea- cr4,0 <start>
-+ 54: 40 88 00 01 bgel- cr2,54 <start\+0x54>
-+ 58: 40 98 00 03 bgela- cr6,0 <start>
-+ 5c: 41 91 00 00 bgt- cr4,5c <start\+0x5c>
-+ 60: 41 99 00 02 bgta- cr6,0 <start>
-+ 64: 41 95 00 01 bgtl- cr5,64 <start\+0x64>
-+ 68: 41 9d 00 03 bgtla- cr7,0 <start>
-+ 6c: 48 00 00 00 b 6c <start\+0x6c>
-+ 70: 48 00 00 03 bla 0 <start>
-+ 74: 40 81 00 00 ble- 74 <start\+0x74>
-+ 78: 40 91 00 02 blea- cr4,0 <start>
-+ 7c: 40 89 00 01 blel- cr2,7c <start\+0x7c>
-+ 80: 40 99 00 03 blela- cr6,0 <start>
-+ 84: 48 00 00 01 bl 84 <start\+0x84>
-+ 88: 41 80 00 00 blt- 88 <start\+0x88>
-+ 8c: 41 88 00 02 blta- cr2,0 <start>
-+ 90: 41 84 00 01 bltl- cr1,90 <start\+0x90>
-+ 94: 41 8c 00 03 bltla- cr3,0 <start>
-+ 98: 40 82 00 00 bne- 98 <start\+0x98>
-+ 9c: 40 8a 00 02 bnea- cr2,0 <start>
-+ a0: 40 86 00 01 bnel- cr1,a0 <start\+0xa0>
-+ a4: 40 8e 00 03 bnela- cr3,0 <start>
-+ a8: 40 85 00 00 ble- cr1,a8 <start\+0xa8>
-+ ac: 40 95 00 02 blea- cr5,0 <start>
-+ b0: 40 8d 00 01 blel- cr3,b0 <start\+0xb0>
-+ b4: 40 9d 00 03 blela- cr7,0 <start>
-+ b8: 40 84 00 00 bge- cr1,b8 <start\+0xb8>
-+ bc: 40 94 00 02 bgea- cr5,0 <start>
-+ c0: 40 8c 00 01 bgel- cr3,c0 <start\+0xc0>
-+ c4: 40 9c 00 03 bgela- cr7,0 <start>
-+ c8: 40 93 00 00 bns- cr4,c8 <start\+0xc8>
-+ cc: 40 9b 00 02 bnsa- cr6,0 <start>
-+ d0: 40 97 00 01 bnsl- cr5,d0 <start\+0xd0>
-+ d4: 40 9f 00 03 bnsla- cr7,0 <start>
-+ d8: 41 93 00 00 bso- cr4,d8 <start\+0xd8>
-+ dc: 41 9b 00 02 bsoa- cr6,0 <start>
-+ e0: 41 97 00 01 bsol- cr5,e0 <start\+0xe0>
-+ e4: 41 9f 00 03 bsola- cr7,0 <start>
-+ e8: 4c 85 32 02 crand 4\*cr1\+lt,4\*cr1\+gt,4\*cr1\+eq
-+ ec: 4c 64 29 02 crandc so,4\*cr1\+lt,4\*cr1\+gt
-+ f0: 4c e0 0a 42 creqv 4\*cr1\+so,lt,gt
-+ f4: 4c 22 19 c2 crnand gt,eq,so
-+ f8: 4c 01 10 42 crnor lt,gt,eq
-+ fc: 4c a6 3b 82 cror 4\*cr1\+gt,4\*cr1\+eq,4\*cr1\+so
-+ 100: 4c 43 23 42 crorc eq,so,4\*cr1\+lt
-+ 104: 4c c7 01 82 crxor 4\*cr1\+eq,4\*cr1\+so,lt
-+ 108: 7d 6a 62 39 eqv. r10,r11,r12
-+ 10c: 7d 6a 62 38 eqv r10,r11,r12
-+ 110: fe a0 fa 11 fabs. f21,f31
-+ 114: fe a0 fa 10 fabs f21,f31
-+ 118: fd 8a 58 40 fcmpo cr3,f10,f11
-+ 11c: fd 84 28 00 fcmpu cr3,f4,f5
-+ 120: fc 60 20 91 fmr. f3,f4
-+ 124: fc 60 20 90 fmr f3,f4
-+ 128: fe 80 f1 11 fnabs. f20,f30
-+ 12c: fe 80 f1 10 fnabs f20,f30
-+ 130: fc 60 20 51 fneg. f3,f4
-+ 134: fc 60 20 50 fneg f3,f4
-+ 138: fc c0 38 18 frsp f6,f7
-+ 13c: fd 00 48 19 frsp. f8,f9
-+ 140: 89 21 00 00 lbz r9,0\(r1\)
-+ 144: 8d 41 00 01 lbzu r10,1\(r1\)
-+ 148: 7e 95 b0 ee lbzux r20,r21,r22
-+ 14c: 7c 64 28 ae lbzx r3,r4,r5
-+ 150: ca a1 00 08 lfd f21,8\(r1\)
-+ 154: ce c1 00 10 lfdu f22,16\(r1\)
-+ 158: 7e 95 b4 ee lfdux f20,r21,r22
-+ 15c: 7d ae 7c ae lfdx f13,r14,r15
-+ 160: c2 61 00 00 lfs f19,0\(r1\)
-+ 164: c6 81 00 04 lfsu f20,4\(r1\)
-+ 168: 7d 4b 64 6e lfsux f10,r11,r12
-+ 16c: 7d 4b 64 2e lfsx f10,r11,r12
-+ 170: a9 e1 00 06 lha r15,6\(r1\)
-+ 174: ae 01 00 08 lhau r16,8\(r1\)
-+ 178: 7d 2a 5a ee lhaux r9,r10,r11
-+ 17c: 7d 2a 5a ae lhax r9,r10,r11
-+ 180: 7c 64 2e 2c lhbrx r3,r4,r5
-+ 184: a1 a1 00 00 lhz r13,0\(r1\)
-+ 188: a5 c1 00 02 lhzu r14,2\(r1\)
-+ 18c: 7e 96 c2 6e lhzux r20,r22,r24
-+ 190: 7e f8 ca 2e lhzx r23,r24,r25
-+ 194: 4c 04 00 00 mcrf cr0,cr1
-+ 198: fd 90 00 80 mcrfs cr3,cr4
-+ 19c: 7d 80 04 00 mcrxr cr3
-+ 1a0: 7c 60 00 26 mfcr r3
-+ 1a4: 7c 69 02 a6 mfctr r3
-+ 1a8: 7c b3 02 a6 mfdar r5
-+ 1ac: 7c 92 02 a6 mfdsisr r4
-+ 1b0: ff c0 04 8e mffs f30
-+ 1b4: ff e0 04 8f mffs. f31
-+ 1b8: 7c 48 02 a6 mflr r2
-+ 1bc: 7e 60 00 a6 mfmsr r19
-+ 1c0: 7c 78 00 26 mfocrf r3,128
-+ 1c4: 7c 25 02 a6 mfrtcl r1
-+ 1c8: 7c 04 02 a6 mfrtcu r0
-+ 1cc: 7c d9 02 a6 mfsdr1 r6
-+ 1d0: 7c 60 22 a6 mfspr r3,128
-+ 1d4: 7c fa 02 a6 mfsrr0 r7
-+ 1d8: 7d 1b 02 a6 mfsrr1 r8
-+ 1dc: 7f c1 02 a6 mfxer r30
-+ 1e0: 7f fe fb 79 mr. r30,r31
-+ 1e4: 7f fe fb 78 mr r30,r31
-+ 1e8: 7c 6f f1 20 mtcr r3
-+ 1ec: 7c 68 01 20 mtcrf 128,r3
-+ 1f0: 7e 69 03 a6 mtctr r19
-+ 1f4: 7e b3 03 a6 mtdar r21
-+ 1f8: 7f 16 03 a6 mtdec r24
-+ 1fc: 7e 92 03 a6 mtdsisr r20
-+ 200: fc 60 00 8d mtfsb0. so
-+ 204: fc 60 00 8c mtfsb0 so
-+ 208: fc 60 00 4d mtfsb1. so
-+ 20c: fc 60 00 4c mtfsb1 so
-+ 210: fc 0c 55 8e mtfsf 6,f10
-+ 214: fc 0c 5d 8f mtfsf. 6,f11
-+ 218: ff 00 01 0c mtfsfi 6,0
-+ 21c: ff 00 f1 0d mtfsfi. 6,15
-+ 220: 7e 48 03 a6 mtlr r18
-+ 224: 7d 40 01 24 mtmsr r10
-+ 228: 7c 78 01 20 mtocrf 128,r3
-+ 22c: 7e f5 03 a6 mtrtcl r23
-+ 230: 7e d4 03 a6 mtrtcu r22
-+ 234: 7f 39 03 a6 mtsdr1 r25
-+ 238: 7c 60 23 a6 mtspr 128,r3
-+ 23c: 7f 5a 03 a6 mtsrr0 r26
-+ 240: 7f 7b 03 a6 mtsrr1 r27
-+ 244: 7e 21 03 a6 mtxer r17
-+ 248: 7f bc f3 b9 nand. r28,r29,r30
-+ 24c: 7f bc f3 b8 nand r28,r29,r30
-+ 250: 7c 64 00 d1 neg. r3,r4
-+ 254: 7c 64 00 d0 neg r3,r4
-+ 258: 7e 11 04 d0 nego r16,r17
-+ 25c: 7e 53 04 d1 nego. r18,r19
-+ 260: 7e b4 b0 f9 nor. r20,r21,r22
-+ 264: 7e b4 b0 f8 nor r20,r21,r22
-+ 268: 7e b4 a8 f9 not. r20,r21
-+ 26c: 7e b4 a8 f8 not r20,r21
-+ 270: 7c 40 23 78 or r0,r2,r4
-+ 274: 7d cc 83 79 or. r12,r14,r16
-+ 278: 7e 0f 8b 38 orc r15,r16,r17
-+ 27c: 7e 72 a3 39 orc. r18,r19,r20
-+ 280: 4c 00 00 64 rfi
-+ 284: 99 61 00 02 stb r11,2\(r1\)
-+ 288: 9d 81 00 03 stbu r12,3\(r1\)
-+ 28c: 7d ae 79 ee stbux r13,r14,r15
-+ 290: 7c 64 29 ae stbx r3,r4,r5
-+ 294: db 21 00 20 stfd f25,32\(r1\)
-+ 298: df 41 00 28 stfdu f26,40\(r1\)
-+ 29c: 7c 01 15 ee stfdux f0,r1,r2
-+ 2a0: 7f be fd ae stfdx f29,r30,r31
-+ 2a4: d2 e1 00 14 stfs f23,20\(r1\)
-+ 2a8: d7 01 00 18 stfsu f24,24\(r1\)
-+ 2ac: 7f 5b e5 6e stfsux f26,r27,r28
-+ 2b0: 7e f8 cd 2e stfsx f23,r24,r25
-+ 2b4: b2 21 00 0a sth r17,10\(r1\)
-+ 2b8: 7c c7 47 2c sthbrx r6,r7,r8
-+ 2bc: b6 41 00 0c sthu r18,12\(r1\)
-+ 2c0: 7e b6 bb 6e sthux r21,r22,r23
-+ 2c4: 7d 8d 73 2e sthx r12,r13,r14
-+ 2c8: 7f dd fa 79 xor. r29,r30,r31
-+ 2cc: 7f dd fa 78 xor r29,r30,r31
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/common.s binutils-2.19.1/gas/testsuite/gas/ppc/common.s
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/common.s 1969-12-31 16:00:00.000000000 -0800
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/common.s 2009-03-02 05:37:44.000000000 -0800
-@@ -0,0 +1,182 @@
-+ .section ".text"
-+start:
-+ and. 3,4,5
-+ and 3,4,5
-+ andc 13,14,15
-+ andc. 16,17,18
-+ ba label_abs
-+ bc 0,1,foo
-+ bca 4,5,foo_abs
-+ bcl 2,3,foo
-+ bcla 10,7,foo_abs
-+ bctr
-+ bctrl
-+ bdza foo_abs
-+ bdz foo
-+ bdzla foo_abs
-+ bdzl foo
-+ beq 0,foo
-+ beqa 2,foo_abs
-+ beql 1,foo
-+ beqla 3,foo_abs
-+ bge 0,foo
-+ bgea 4,foo_abs
-+ bgel 2,foo
-+ bgela 6,foo_abs
-+ bgt 4,foo
-+ bgta 6,foo_abs
-+ bgtl 5,foo
-+ bgtla 7,foo_abs
-+ b label
-+ bla label_abs
-+ ble 0,foo
-+ blea 4,foo
-+ blel 2,foo
-+ blela 6,foo_abs
-+ bl label
-+ blt 0,foo
-+ blta 2,foo_abs
-+ bltl 1,foo
-+ bltla 3,foo_abs
-+ bne 0,foo
-+ bnea 2,foo
-+ bnel 1,foo
-+ bnela 3,foo_abs
-+ bng 1,foo
-+ bnga 5,foo_abs
-+ bngl 3,foo
-+ bngla 7,foo_abs
-+ bnl 1,foo
-+ bnla 5,foo_abs
-+ bnll 3,foo
-+ bnlla 7,foo_abs
-+ bns 4,foo
-+ bnsa 6,foo_abs
-+ bnsl 5,foo
-+ bnsla 7,foo_abs
-+ bso 4,foo
-+ bsoa 6,foo_abs
-+ bsol 5,foo
-+ bsola 7,foo_abs
-+ crand 4,5,6
-+ crandc 3,4,5
-+ creqv 7,0,1
-+ crnand 1,2,3
-+ crnor 0,1,2
-+ cror 5,6,7
-+ crorc 2,3,4
-+ crxor 6,7,0
-+ eqv. 10,11,12
-+ eqv 10,11,12
-+ fabs. 21,31
-+ fabs 21,31
-+ fcmpo 3,10,11
-+ fcmpu 3,4,5
-+ fmr. 3,4
-+ fmr 3,4
-+ fnabs. 20,30
-+ fnabs 20,30
-+ fneg. 3,4
-+ fneg 3,4
-+ frsp 6,7
-+ frsp. 8,9
-+ lbz 9,0(1)
-+ lbzu 10,1(1)
-+ lbzux 20,21,22
-+ lbzx 3,4,5
-+ lfd 21,8(1)
-+ lfdu 22,16(1)
-+ lfdux 20,21,22
-+ lfdx 13,14,15
-+ lfs 19,0(1)
-+ lfsu 20,4(1)
-+ lfsux 10,11,12
-+ lfsx 10,11,12
-+ lha 15,6(1)
-+ lhau 16,8(1)
-+ lhaux 9,10,11
-+ lhax 9,10,11
-+ lhbrx 3,4,5
-+ lhz 13,0(1)
-+ lhzu 14,2(1)
-+ lhzux 20,22,24
-+ lhzx 23,24,25
-+ mcrf 0,1
-+ mcrfs 3,4
-+ mcrxr 3
-+ mfcr 3
-+ mfctr 3
-+ mfdar 5
-+ mfdsisr 4
-+ mffs 30
-+ mffs. 31
-+ mflr 2
-+ mfmsr 19
-+ mfocrf 3,0x80
-+ mfrtcl 1
-+ mfrtcu 0
-+ mfsdr1 6
-+ mfspr 3,0x80
-+ mfsrr0 7
-+ mfsrr1 8
-+ mfxer 30
-+ mr. 30,31
-+ mr 30,31
-+ mtcr 3
-+ mtcrf 0x80,3
-+ mtctr 19
-+ mtdar 21
-+ mtdec 24
-+ mtdsisr 20
-+ mtfsb0. 3
-+ mtfsb0 3
-+ mtfsb1. 3
-+ mtfsb1 3
-+ mtfsf 6,10
-+ mtfsf. 6,11
-+ mtfsfi 6,0
-+ mtfsfi. 6,15
-+ mtlr 18
-+ mtmsr 10
-+ mtocrf 0x80,3
-+ mtrtcl 23
-+ mtrtcu 22
-+ mtsdr1 25
-+ mtspr 0x80,3
-+ mtsrr0 26
-+ mtsrr1 27
-+ mtxer 17
-+ nand. 28,29,30
-+ nand 28,29,30
-+ neg. 3,4
-+ neg 3,4
-+ nego 16,17
-+ nego. 18,19
-+ nor. 20,21,22
-+ nor 20,21,22
-+ not. 20,21
-+ not 20,21
-+ or 0,2,4
-+ or. 12,14,16
-+ orc 15,16,17
-+ orc. 18,19,20
-+ rfi
-+ stb 11,2(1)
-+ stbu 12,3(1)
-+ stbux 13,14,15
-+ stbx 3,4,5
-+ stfd 25,32(1)
-+ stfdu 26,40(1)
-+ stfdux 0,1,2
-+ stfdx 29,30,31
-+ stfs 23,20(1)
-+ stfsu 24,24(1)
-+ stfsux 26,27,28
-+ stfsx 23,24,25
-+ sth 17,10(1)
-+ sthbrx 6,7,8
-+ sthu 18,12(1)
-+ sthux 21,22,23
-+ sthx 12,13,14
-+ xor. 29,30,31
-+ xor 29,30,31
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/e500mc.d binutils-2.19.1/gas/testsuite/gas/ppc/e500mc.d
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/e500mc.d 2008-04-14 04:01:38.000000000 -0700
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/e500mc.d 2009-03-02 05:59:36.000000000 -0800
-@@ -6,7 +6,7 @@
-
- Disassembly of section \.text:
-
--0+0000000 <start>:
-+0+00 <start>:
- 0: 4c 00 00 4e rfdi
- 4: 4c 00 00 cc rfgi
- 8: 4c 1f f9 8c dnh 0,1023
-@@ -14,38 +14,43 @@
- 10: 7c 09 57 be icbiep r9,r10
- 14: 7c 00 69 dc msgclr r13
- 18: 7c 00 71 9c msgsnd r14
-- 1c: 7c 00 00 7c wait
-- 20: 7f 9c e3 78 mdors
-- 24: 7c 00 02 1c ehpriv
-- 28: 7c 18 cb c6 dsn r24,r25
-- 2c: 7c 22 18 be lbepx r1,r2,r3
-- 30: 7c 85 32 3e lhepx r4,r5,r6
-- 34: 7c e8 48 3e lwepx r7,r8,r9
-- 38: 7d 4b 60 3a ldepx r10,r11,r12
-- 3c: 7d ae 7c be lfdepx r13,r14,r15
-- 40: 7e 11 91 be stbepx r16,r17,r18
-- 44: 7e 74 ab 3e sthepx r19,r20,r21
-- 48: 7e d7 c1 3e stwepx r22,r23,r24
-- 4c: 7f 3a d9 3a stdepx r25,r26,r27
-- 50: 7f 9d f5 be stfdepx r28,r29,r30
-- 54: 7c 01 14 06 lbdx r0,r1,r2
-- 58: 7d 8d 74 46 lhdx r12,r13,r14
-- 5c: 7c 64 2c 86 lwdx r3,r4,r5
-- 60: 7f 5b e6 46 lfddx f26,r27,r28
-- 64: 7d f0 8c c6 lddx r15,r16,r17
-- 68: 7c c7 45 06 stbdx r6,r7,r8
-- 6c: 7e 53 a5 46 sthdx r18,r19,r20
-- 70: 7d 2a 5d 86 stwdx r9,r10,r11
-- 74: 7f be ff 46 stfddx f29,r30,r31
-- 78: 7e b6 bd c6 stddx r21,r22,r23
-- 7c: 7c 20 0d ec dcbal r0,r1
-- 80: 7c 26 3f ec dcbzl r6,r7
-- 84: 7c 1f 00 7e dcbstep r31,r0
-- 88: 7c 01 10 fe dcbfep r1,r2
-- 8c: 7c 64 29 fe dcbtstep r3,r4,r5
-- 90: 7c c7 42 7e dcbtep r6,r7,r8
-- 94: 7c 0b 67 fe dcbzep r11,r12
-- 98: 7c 00 06 26 tlbilx 0,0,r0
-- 9c: 7c 20 06 26 tlbilx 1,0,r0
-- a0: 7c 62 1e 26 tlbilx 3,r2,r3
-- a4: 7c 64 2e 26 tlbilx 3,r4,r5
-+ 1c: 7c 00 00 7c wait
-+ 20: 7c 00 00 7c wait
-+ 24: 7c 20 00 7c waitrsv
-+ 28: 7c 20 00 7c waitrsv
-+ 2c: 7c 40 00 7c waitimpl
-+ 30: 7c 40 00 7c waitimpl
-+ 34: 7f 9c e3 78 mdors
-+ 38: 7c 00 02 1c ehpriv
-+ 3c: 7c 18 cb c6 dsn r24,r25
-+ 40: 7c 22 18 be lbepx r1,r2,r3
-+ 44: 7c 85 32 3e lhepx r4,r5,r6
-+ 48: 7c e8 48 3e lwepx r7,r8,r9
-+ 4c: 7d 4b 60 3a ldepx r10,r11,r12
-+ 50: 7d ae 7c be lfdepx f13,r14,r15
-+ 54: 7e 11 91 be stbepx r16,r17,r18
-+ 58: 7e 74 ab 3e sthepx r19,r20,r21
-+ 5c: 7e d7 c1 3e stwepx r22,r23,r24
-+ 60: 7f 3a d9 3a stdepx r25,r26,r27
-+ 64: 7f 9d f5 be stfdepx f28,r29,r30
-+ 68: 7c 01 14 06 lbdx r0,r1,r2
-+ 6c: 7d 8d 74 46 lhdx r12,r13,r14
-+ 70: 7c 64 2c 86 lwdx r3,r4,r5
-+ 74: 7f 5b e6 46 lfddx f26,r27,r28
-+ 78: 7d f0 8c c6 lddx r15,r16,r17
-+ 7c: 7c c7 45 06 stbdx r6,r7,r8
-+ 80: 7e 53 a5 46 sthdx r18,r19,r20
-+ 84: 7d 2a 5d 86 stwdx r9,r10,r11
-+ 88: 7f be ff 46 stfddx f29,r30,r31
-+ 8c: 7e b6 bd c6 stddx r21,r22,r23
-+ 90: 7c 20 0d ec dcbal r0,r1
-+ 94: 7c 26 3f ec dcbzl r6,r7
-+ 98: 7c 1f 00 7e dcbstep r31,r0
-+ 9c: 7c 01 10 fe dcbfep r1,r2
-+ a0: 7c 64 29 fe dcbtstep r3,r4,r5
-+ a4: 7c c7 42 7e dcbtep r6,r7,r8
-+ a8: 7c 0b 67 fe dcbzep r11,r12
-+ ac: 7c 00 06 26 tlbilx 0,0,r0
-+ b0: 7c 20 06 26 tlbilx 1,0,r0
-+ b4: 7c 62 1e 26 tlbilx 3,r2,r3
-+ b8: 7c 64 2e 26 tlbilx 3,r4,r5
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/e500mc.s binutils-2.19.1/gas/testsuite/gas/ppc/e500mc.s
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/e500mc.s 2008-04-14 04:01:38.000000000 -0700
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/e500mc.s 2009-03-02 05:59:36.000000000 -0800
-@@ -9,6 +9,11 @@
- msgclr 13
- msgsnd 14
- wait
-+ wait 0
-+ waitrsv
-+ wait 1
-+ waitimpl
-+ wait 2
- mdors
- ehpriv
- dsn 24, 25
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/power4_32.d binutils-2.19.1/gas/testsuite/gas/ppc/power4_32.d
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/power4_32.d 1969-12-31 16:00:00.000000000 -0800
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/power4_32.d 2009-03-02 05:54:22.000000000 -0800
-@@ -0,0 +1,46 @@
-+#objdump: -d -Mpower4
-+#as: -a32 -mpower4
-+#name: Power4 instructions
-+
-+.*: +file format elf32-powerpc.*
-+
-+Disassembly of section \.text:
-+
-+0+00 <start>:
-+ 0: 80 c7 00 00 lwz r6,0\(r7\)
-+ 4: 80 c7 00 10 lwz r6,16\(r7\)
-+ 8: 80 c7 ff f0 lwz r6,-16\(r7\)
-+ c: 80 c7 80 00 lwz r6,-32768\(r7\)
-+ 10: 80 c7 7f f0 lwz r6,32752\(r7\)
-+ 14: 90 c7 00 00 stw r6,0\(r7\)
-+ 18: 90 c7 00 10 stw r6,16\(r7\)
-+ 1c: 90 c7 ff f0 stw r6,-16\(r7\)
-+ 20: 90 c7 80 00 stw r6,-32768\(r7\)
-+ 24: 90 c7 7f f0 stw r6,32752\(r7\)
-+ 28: 00 00 02 00 attn
-+ 2c: 7c 6f f1 20 mtcr r3
-+ 30: 7c 6f f1 20 mtcr r3
-+ 34: 7c 68 11 20 mtcrf 129,r3
-+ 38: 7c 70 11 20 mtocrf 1,r3
-+ 3c: 7c 70 21 20 mtocrf 2,r3
-+ 40: 7c 70 41 20 mtocrf 4,r3
-+ 44: 7c 70 81 20 mtocrf 8,r3
-+ 48: 7c 71 01 20 mtocrf 16,r3
-+ 4c: 7c 72 01 20 mtocrf 32,r3
-+ 50: 7c 74 01 20 mtocrf 64,r3
-+ 54: 7c 78 01 20 mtocrf 128,r3
-+ 58: 7c 60 00 26 mfcr r3
-+ 5c: 7c 70 10 26 mfocrf r3,1
-+ 60: 7c 70 20 26 mfocrf r3,2
-+ 64: 7c 70 40 26 mfocrf r3,4
-+ 68: 7c 70 80 26 mfocrf r3,8
-+ 6c: 7c 71 00 26 mfocrf r3,16
-+ 70: 7c 72 00 26 mfocrf r3,32
-+ 74: 7c 74 00 26 mfocrf r3,64
-+ 78: 7c 78 00 26 mfocrf r3,128
-+ 7c: 7c 01 17 ec dcbz r1,r2
-+ 80: 7c 23 27 ec dcbzl r3,r4
-+ 84: 7c 05 37 ec dcbz r5,r6
-+ 88: 7c 05 32 2c dcbt r5,r6
-+ 8c: 7c 05 32 2c dcbt r5,r6
-+ 90: 7d 05 32 2c dcbt r5,r6,8
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/power4_32.s binutils-2.19.1/gas/testsuite/gas/ppc/power4_32.s
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/power4_32.s 1969-12-31 16:00:00.000000000 -0800
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/power4_32.s 2009-03-02 05:54:22.000000000 -0800
-@@ -0,0 +1,39 @@
-+ .section ".text"
-+start:
-+ lwz 6,0(7)
-+ lwz 6,16(7)
-+ lwz 6,-16(7)
-+ lwz 6,-32768(7)
-+ lwz 6,32752(7)
-+ stw 6,0(7)
-+ stw 6,16(7)
-+ stw 6,-16(7)
-+ stw 6,-32768(7)
-+ stw 6,32752(7)
-+ attn
-+ mtcr 3
-+ mtcrf 0xff,3
-+ mtcrf 0x81,3
-+ mtcrf 0x01,3
-+ mtcrf 0x02,3
-+ mtcrf 0x04,3
-+ mtcrf 0x08,3
-+ mtcrf 0x10,3
-+ mtcrf 0x20,3
-+ mtcrf 0x40,3
-+ mtcrf 0x80,3
-+ mfcr 3
-+ mfcr 3,0x01
-+ mfcr 3,0x02
-+ mfcr 3,0x04
-+ mfcr 3,0x08
-+ mfcr 3,0x10
-+ mfcr 3,0x20
-+ mfcr 3,0x40
-+ mfcr 3,0x80
-+ dcbz 1, 2
-+ dcbzl 3, 4
-+ dcbz 5, 6
-+ dcbt 5,6
-+ dcbt 5,6,0
-+ dcbt 5,6,8
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/power6.d binutils-2.19.1/gas/testsuite/gas/ppc/power6.d
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/power6.d 2008-07-31 19:44:12.000000000 -0700
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/power6.d 2009-03-02 05:59:36.000000000 -0800
-@@ -28,4 +28,44 @@
- 48: 7e 08 3a ac dstt r8,r7,0
- 4c: 7c 65 32 ec dstst r5,r6,3
- 50: 7e 44 2a ec dststt r4,r5,2
--
-+ 54: 00 00 02 00 attn
-+ 58: 7c 6f f1 20 mtcr r3
-+ 5c: 7c 6f f1 20 mtcr r3
-+ 60: 7c 68 11 20 mtcrf 129,r3
-+ 64: 7c 70 11 20 mtocrf 1,r3
-+ 68: 7c 70 21 20 mtocrf 2,r3
-+ 6c: 7c 70 41 20 mtocrf 4,r3
-+ 70: 7c 70 81 20 mtocrf 8,r3
-+ 74: 7c 71 01 20 mtocrf 16,r3
-+ 78: 7c 72 01 20 mtocrf 32,r3
-+ 7c: 7c 74 01 20 mtocrf 64,r3
-+ 80: 7c 78 01 20 mtocrf 128,r3
-+ 84: 7c 60 00 26 mfcr r3
-+ 88: 7c 70 10 26 mfocrf r3,1
-+ 8c: 7c 70 20 26 mfocrf r3,2
-+ 90: 7c 70 40 26 mfocrf r3,4
-+ 94: 7c 70 80 26 mfocrf r3,8
-+ 98: 7c 71 00 26 mfocrf r3,16
-+ 9c: 7c 72 00 26 mfocrf r3,32
-+ a0: 7c 74 00 26 mfocrf r3,64
-+ a4: 7c 78 00 26 mfocrf r3,128
-+ a8: 7c 01 17 ec dcbz r1,r2
-+ ac: 7c 23 27 ec dcbzl r3,r4
-+ b0: 7c 05 37 ec dcbz r5,r6
-+ b4: fc 0c 55 8e mtfsf 6,f10
-+ b8: fc 0c 5d 8f mtfsf. 6,f11
-+ bc: fc 0c 55 8e mtfsf 6,f10
-+ c0: fc 0c 5d 8f mtfsf. 6,f11
-+ c4: fc 0d 55 8e mtfsf 6,f10,0,1
-+ c8: fc 0d 5d 8f mtfsf. 6,f11,0,1
-+ cc: fe 0c 55 8e mtfsf 6,f10,1,0
-+ d0: fe 0c 5d 8f mtfsf. 6,f11,1,0
-+ d4: ff 00 01 0c mtfsfi 6,0
-+ d8: ff 00 f1 0d mtfsfi. 6,15
-+ dc: ff 00 01 0c mtfsfi 6,0
-+ e0: ff 00 f1 0d mtfsfi. 6,15
-+ e4: ff 01 01 0c mtfsfi 6,0,1
-+ e8: ff 01 f1 0d mtfsfi. 6,15,1
-+ ec: 7d 6a 02 74 cbcdtd r10,r11
-+ f0: 7d 6a 02 34 cdtbcd r10,r11
-+ f4: 7d 4b 60 94 addg6s r10,r11,r12
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/power6.s binutils-2.19.1/gas/testsuite/gas/ppc/power6.s
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/power6.s 2008-07-31 19:44:12.000000000 -0700
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/power6.s 2009-03-02 05:59:36.000000000 -0800
-@@ -23,3 +23,44 @@
- dstt 8,7,0
- dstst 5,6,3
- dststt 4,5,2
-+ attn
-+ mtcr 3
-+ mtcrf 0xff,3
-+ mtcrf 0x81,3
-+ mtcrf 0x01,3
-+ mtcrf 0x02,3
-+ mtcrf 0x04,3
-+ mtcrf 0x08,3
-+ mtcrf 0x10,3
-+ mtcrf 0x20,3
-+ mtcrf 0x40,3
-+ mtcrf 0x80,3
-+ mfcr 3
-+ mfcr 3,0x01
-+ mfcr 3,0x02
-+ mfcr 3,0x04
-+ mfcr 3,0x08
-+ mfcr 3,0x10
-+ mfcr 3,0x20
-+ mfcr 3,0x40
-+ mfcr 3,0x80
-+ dcbz 1, 2
-+ dcbzl 3, 4
-+ dcbz 5, 6
-+ mtfsf 6,10
-+ mtfsf. 6,11
-+ mtfsf 6,10,0,0
-+ mtfsf. 6,11,0,0
-+ mtfsf 6,10,0,1
-+ mtfsf. 6,11,0,1
-+ mtfsf 6,10,1,0
-+ mtfsf. 6,11,1,0
-+ mtfsfi 6,0
-+ mtfsfi. 6,15
-+ mtfsfi 6,0,0
-+ mtfsfi. 6,15,0
-+ mtfsfi 6,0,1
-+ mtfsfi. 6,15,1
-+ cbcdtd 10,11
-+ cdtbcd 10,11
-+ addg6s 10,11,12
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/power7.d binutils-2.19.1/gas/testsuite/gas/ppc/power7.d
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/power7.d 2008-08-01 21:38:51.000000000 -0700
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/power7.d 2009-03-02 05:59:36.000000000 -0800
-@@ -1,8 +1,8 @@
--#as: -a32 -mpower7
-+#as: -mpower7
- #objdump: -dr -Mpower7
- #name: POWER7 tests (includes DFP, Altivec and VSX)
-
--.*: +file format elf32-powerpc.*
-+.*: +file format elf(32)?(64)?-powerpc.*
-
- Disassembly of section \.text:
-
-@@ -33,25 +33,81 @@
- 5c: f1 6c 67 87 xvmovdp vs43,vs44
- 60: f0 64 2f 80 xvcpsgndp vs3,vs4,vs5
- 64: f1 6c 6f 87 xvcpsgndp vs43,vs44,vs45
-- 68: 4c 00 03 24 doze
-- 6c: 4c 00 03 64 nap
-- 70: 4c 00 03 a4 sleep
-- 74: 4c 00 03 e4 rvwinkle
-- 78: 7c 83 01 34 prtyw r3,r4
-- 7c: 7d cd 01 74 prtyd r13,r14
-- 80: 7d 5c 02 a6 mfcfar r10
-- 84: 7d 7c 03 a6 mtcfar r11
-- 88: 7c 83 2b f8 cmpb r3,r4,r5
-- 8c: 7c c0 3c be mffgpr f6,r7
-- 90: 7d 00 4d be mftgpr r8,f9
-- 94: 7d 4b 66 2a lwzcix r10,r11,r12
-- 98: 7d ae 7e 2e lfdpx f13,r14,r15
-- 9c: ee 11 90 04 dadd f16,f17,f18
-- a0: fe 96 c0 04 daddq f20,f22,f24
-- a4: 7c 60 06 6c dss 3
-- a8: 7e 00 06 6c dssall
-- ac: 7c 25 22 ac dst r5,r4,1
-- b0: 7e 08 3a ac dstt r8,r7,0
-- b4: 7c 65 32 ec dstst r5,r6,3
-- b8: 7e 44 2a ec dststt r4,r5,2
-- bc: 4e 80 00 20 blr
-+ 68: 7c 00 00 7c wait
-+ 6c: 7c 00 00 7c wait
-+ 70: 7c 20 00 7c waitrsv
-+ 74: 7c 20 00 7c waitrsv
-+ 78: 7c 40 00 7c waitimpl
-+ 7c: 7c 40 00 7c waitimpl
-+ 80: 4c 00 03 24 doze
-+ 84: 4c 00 03 64 nap
-+ 88: 4c 00 03 a4 sleep
-+ 8c: 4c 00 03 e4 rvwinkle
-+ 90: 7c 83 01 34 prtyw r3,r4
-+ 94: 7d cd 01 74 prtyd r13,r14
-+ 98: 7d 5c 02 a6 mfcfar r10
-+ 9c: 7d 7c 03 a6 mtcfar r11
-+ a0: 7c 83 2b f8 cmpb r3,r4,r5
-+ a4: 7d 4b 66 2a lwzcix r10,r11,r12
-+ a8: ee 11 90 04 dadd f16,f17,f18
-+ ac: fe 96 c0 04 daddq f20,f22,f24
-+ b0: 7c 60 06 6c dss 3
-+ b4: 7e 00 06 6c dssall
-+ b8: 7c 25 22 ac dst r5,r4,1
-+ bc: 7e 08 3a ac dstt r8,r7,0
-+ c0: 7c 65 32 ec dstst r5,r6,3
-+ c4: 7e 44 2a ec dststt r4,r5,2
-+ c8: 7d 4b 63 56 divwe r10,r11,r12
-+ cc: 7d 6c 6b 57 divwe\. r11,r12,r13
-+ d0: 7d 8d 77 56 divweo r12,r13,r14
-+ d4: 7d ae 7f 57 divweo\. r13,r14,r15
-+ d8: 7d 4b 63 16 divweu r10,r11,r12
-+ dc: 7d 6c 6b 17 divweu\. r11,r12,r13
-+ e0: 7d 8d 77 16 divweuo r12,r13,r14
-+ e4: 7d ae 7f 17 divweuo\. r13,r14,r15
-+ e8: 7e 27 d9 f8 bpermd r7,r17,r27
-+ ec: 7e 8a 02 f4 popcntw r10,r20
-+ f0: 7e 8a 03 f4 popcntd r10,r20
-+ f4: 7e 95 b4 28 ldbrx r20,r21,r22
-+ f8: 7e 95 b5 28 stdbrx r20,r21,r22
-+ fc: 7d 40 56 ee lfiwzx f10,0,r10
-+ 100: 7d 49 56 ee lfiwzx f10,r9,r10
-+ 104: ec 80 2e 9c fcfids f4,f5
-+ 108: ec 80 2e 9d fcfids\. f4,f5
-+ 10c: ec 80 2f 9c fcfidus f4,f5
-+ 110: ec 80 2f 9d fcfidus\. f4,f5
-+ 114: fc 80 29 1c fctiwu f4,f5
-+ 118: fc 80 29 1d fctiwu\. f4,f5
-+ 11c: fc 80 29 1e fctiwuz f4,f5
-+ 120: fc 80 29 1f fctiwuz\. f4,f5
-+ 124: fc 80 2f 5c fctidu f4,f5
-+ 128: fc 80 2f 5d fctidu\. f4,f5
-+ 12c: fc 80 2f 5e fctiduz f4,f5
-+ 130: fc 80 2f 5f fctiduz\. f4,f5
-+ 134: fc 80 2f 9c fcfidu f4,f5
-+ 138: fc 80 2f 9d fcfidu\. f4,f5
-+ 13c: fc 0a 59 00 ftdiv cr0,f10,f11
-+ 140: ff 8a 59 00 ftdiv cr7,f10,f11
-+ 144: fc 00 51 40 ftsqrt cr0,f10
-+ 148: ff 80 51 40 ftsqrt cr7,f10
-+ 14c: 7e 08 4a 2c dcbtt r8,r9
-+ 150: 7e 08 49 ec dcbtstt r8,r9
-+ 154: ed 40 66 44 dcffix f10,f12
-+ 158: ee 80 b6 45 dcffix\. f20,f22
-+ 15c: 7d 4b 60 68 lbarx r10,r11,r12
-+ 160: 7d 4b 60 68 lbarx r10,r11,r12
-+ 164: 7d 4b 60 69 lbarx r10,r11,r12,1
-+ 168: 7e 95 b0 e8 lharx r20,r21,r22
-+ 16c: 7e 95 b0 e8 lharx r20,r21,r22
-+ 170: 7e 95 b0 e9 lharx r20,r21,r22,1
-+ 174: 7d 4b 65 6d stbcx\. r10,r11,r12
-+ 178: 7d 4b 65 ad sthcx\. r10,r11,r12
-+ 17c: fd c0 78 30 fre f14,f15
-+ 180: fd c0 78 31 fre\. f14,f15
-+ 184: ed c0 78 30 fres f14,f15
-+ 188: ed c0 78 31 fres\. f14,f15
-+ 18c: fd c0 78 34 frsqrte f14,f15
-+ 190: fd c0 78 35 frsqrte\. f14,f15
-+ 194: ed c0 78 34 frsqrtes f14,f15
-+ 198: ed c0 78 35 frsqrtes\. f14,f15
-+ 19c: 7c 43 27 1e isel r2,r3,r4,28
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/power7.s binutils-2.19.1/gas/testsuite/gas/ppc/power7.s
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/power7.s 2008-08-01 21:38:51.000000000 -0700
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/power7.s 2009-03-02 05:59:36.000000000 -0800
-@@ -1,9 +1,4 @@
-- .file "power7.c"
- .section ".text"
-- .align 2
-- .p2align 4,,15
-- .globl power7
-- .type power7, @function
- power7:
- lxvd2x 3,4,5
- lxvd2ux 3,4,5
-@@ -31,6 +26,12 @@
- xvcpsgndp 43,44,44
- xvcpsgndp 3,4,5
- xvcpsgndp 43,44,45
-+ wait
-+ wait 0
-+ waitrsv
-+ wait 1
-+ waitimpl
-+ wait 2
- doze
- nap
- sleep
-@@ -40,10 +41,7 @@
- mfcfar 10
- mtcfar 11
- cmpb 3,4,5
-- mffgpr 6,7
-- mftgpr 8,9
- lwzcix 10,11,12
-- lfdpx 13,14,15
- dadd 16,17,18
- daddq 20,22,24
- dss 3
-@@ -52,7 +50,57 @@
- dstt 8,7,0
- dstst 5,6,3
- dststt 4,5,2
-- blr
-- .size power7,.-power7
-- .ident "GCC: (GNU) 4.1.2 20070115 (prerelease) (SUSE Linux)"
-- .section .note.GNU-stack,"",@progbits
-+ divwe 10,11,12
-+ divwe. 11,12,13
-+ divweo 12,13,14
-+ divweo. 13,14,15
-+ divweu 10,11,12
-+ divweu. 11,12,13
-+ divweuo 12,13,14
-+ divweuo. 13,14,15
-+ bpermd 7,17,27
-+ popcntw 10,20
-+ popcntd 10,20
-+ ldbrx 20,21,22
-+ stdbrx 20,21,22
-+ lfiwzx 10,0,10
-+ lfiwzx 10,9,10
-+ fcfids 4,5
-+ fcfids. 4,5
-+ fcfidus 4,5
-+ fcfidus. 4,5
-+ fctiwu 4,5
-+ fctiwu. 4,5
-+ fctiwuz 4,5
-+ fctiwuz. 4,5
-+ fctidu 4,5
-+ fctidu. 4,5
-+ fctiduz 4,5
-+ fctiduz. 4,5
-+ fcfidu 4,5
-+ fcfidu. 4,5
-+ ftdiv 0,10,11
-+ ftdiv 7,10,11
-+ ftsqrt 0,10
-+ ftsqrt 7,10
-+ dcbtt 8,9
-+ dcbtstt 8,9
-+ dcffix 10,12
-+ dcffix. 20,22
-+ lbarx 10,11,12
-+ lbarx 10,11,12,0
-+ lbarx 10,11,12,1
-+ lharx 20,21,22
-+ lharx 20,21,22,0
-+ lharx 20,21,22,1
-+ stbcx. 10,11,12
-+ sthcx. 10,11,12
-+ fre 14,15
-+ fre. 14,15
-+ fres 14,15
-+ fres. 14,15
-+ frsqrte 14,15
-+ frsqrte. 14,15
-+ frsqrtes 14,15
-+ frsqrtes. 14,15
-+ isel 2,3,4,28
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/ppc.exp binutils-2.19.1/gas/testsuite/gas/ppc/ppc.exp
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/ppc.exp 2008-08-01 21:38:51.000000000 -0700
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/ppc.exp 2009-03-02 05:59:36.000000000 -0800
-@@ -45,7 +45,10 @@
- run_dump_test "ppc750ps"
- run_dump_test "e500mc"
- run_dump_test "cell"
-+ run_dump_test "common"
-+ run_dump_test "power4_32"
- run_dump_test "power6"
- run_dump_test "power7"
-+ run_dump_test "vsx"
- }
- }
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/vsx.d binutils-2.19.1/gas/testsuite/gas/ppc/vsx.d
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/vsx.d 1969-12-31 16:00:00.000000000 -0800
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/vsx.d 2009-03-02 05:59:36.000000000 -0800
-@@ -0,0 +1,174 @@
-+#as: -mvsx
-+#objdump: -d -Mvsx
-+#name: VSX tests
-+
-+.*: +file format elf(32)?(64)?-powerpc.*
-+
-+
-+Disassembly of section \.text:
-+
-+0+00 <start>:
-+ 0: 7d 0a a4 99 lxsdx vs40,r10,r20
-+ 4: 7d 0a a4 d9 lxsdux vs40,r10,r20
-+ 8: 7d 0a a6 99 lxvd2x vs40,r10,r20
-+ c: 7d 0a a6 d9 lxvd2ux vs40,r10,r20
-+ 10: 7d 0a a2 99 lxvdsx vs40,r10,r20
-+ 14: 7d 0a a6 19 lxvw4x vs40,r10,r20
-+ 18: 7d 0a a6 59 lxvw4ux vs40,r10,r20
-+ 1c: 7d 0a a5 99 stxsdx vs40,r10,r20
-+ 20: 7d 0a a5 d9 stxsdux vs40,r10,r20
-+ 24: 7d 0a a7 99 stxvd2x vs40,r10,r20
-+ 28: 7d 0a a7 d9 stxvd2ux vs40,r10,r20
-+ 2c: 7d 0a a7 19 stxvw4x vs40,r10,r20
-+ 30: 7d 0a a7 59 stxvw4ux vs40,r10,r20
-+ 34: f1 00 e5 67 xsabsdp vs40,vs60
-+ 38: f1 12 e1 07 xsadddp vs40,vs50,vs60
-+ 3c: f0 92 e1 5e xscmpodp cr1,vs50,vs60
-+ 40: f0 92 e1 1e xscmpudp cr1,vs50,vs60
-+ 44: f1 12 e5 87 xscpsgndp vs40,vs50,vs60
-+ 48: f1 00 e4 27 xscvdpsp vs40,vs60
-+ 4c: f1 00 e5 63 xscvdpsxds vs40,vs60
-+ 50: f1 00 e1 63 xscvdpsxws vs40,vs60
-+ 54: f1 00 e5 23 xscvdpuxds vs40,vs60
-+ 58: f1 00 e1 23 xscvdpuxws vs40,vs60
-+ 5c: f1 00 e5 27 xscvspdp vs40,vs60
-+ 60: f1 00 e5 e3 xscvsxddp vs40,vs60
-+ 64: f1 00 e5 a3 xscvuxddp vs40,vs60
-+ 68: f1 12 e1 c7 xsdivdp vs40,vs50,vs60
-+ 6c: f1 12 e1 0f xsmaddadp vs40,vs50,vs60
-+ 70: f1 12 e1 4f xsmaddmdp vs40,vs50,vs60
-+ 74: f1 12 e5 07 xsmaxdp vs40,vs50,vs60
-+ 78: f1 12 e5 47 xsmindp vs40,vs50,vs60
-+ 7c: f1 12 e1 8f xsmsubadp vs40,vs50,vs60
-+ 80: f1 12 e1 cf xsmsubmdp vs40,vs50,vs60
-+ 84: f1 12 e1 87 xsmuldp vs40,vs50,vs60
-+ 88: f1 00 e5 a7 xsnabsdp vs40,vs60
-+ 8c: f1 00 e5 e7 xsnegdp vs40,vs60
-+ 90: f1 12 e5 0f xsnmaddadp vs40,vs50,vs60
-+ 94: f1 12 e5 4f xsnmaddmdp vs40,vs50,vs60
-+ 98: f1 12 e5 8f xsnmsubadp vs40,vs50,vs60
-+ 9c: f1 12 e5 cf xsnmsubmdp vs40,vs50,vs60
-+ a0: f1 00 e1 27 xsrdpi vs40,vs60
-+ a4: f1 00 e1 af xsrdpic vs40,vs60
-+ a8: f1 00 e1 e7 xsrdpim vs40,vs60
-+ ac: f1 00 e1 a7 xsrdpip vs40,vs60
-+ b0: f1 00 e1 67 xsrdpiz vs40,vs60
-+ b4: f1 00 e1 6b xsredp vs40,vs60
-+ b8: f1 00 e1 2b xsrsqrtedp vs40,vs60
-+ bc: f1 00 e1 2f xssqrtdp vs40,vs60
-+ c0: f1 12 e1 47 xssubdp vs40,vs50,vs60
-+ c4: f0 92 e1 ee xstdivdp cr1,vs50,vs60
-+ c8: f0 80 e1 aa xstsqrtdp cr1,vs60
-+ cc: f1 00 e7 67 xvabsdp vs40,vs60
-+ d0: f1 00 e6 67 xvabssp vs40,vs60
-+ d4: f1 12 e3 07 xvadddp vs40,vs50,vs60
-+ d8: f1 12 e2 07 xvaddsp vs40,vs50,vs60
-+ dc: f1 12 e3 1f xvcmpeqdp vs40,vs50,vs60
-+ e0: f1 12 e7 1f xvcmpeqdp. vs40,vs50,vs60
-+ e4: f1 12 e2 1f xvcmpeqsp vs40,vs50,vs60
-+ e8: f1 12 e6 1f xvcmpeqsp. vs40,vs50,vs60
-+ ec: f1 12 e3 9f xvcmpgedp vs40,vs50,vs60
-+ f0: f1 12 e7 9f xvcmpgedp. vs40,vs50,vs60
-+ f4: f1 12 e2 9f xvcmpgesp vs40,vs50,vs60
-+ f8: f1 12 e6 9f xvcmpgesp. vs40,vs50,vs60
-+ fc: f1 12 e3 5f xvcmpgtdp vs40,vs50,vs60
-+ 100: f1 12 e7 5f xvcmpgtdp. vs40,vs50,vs60
-+ 104: f1 12 e2 5f xvcmpgtsp vs40,vs50,vs60
-+ 108: f1 12 e6 5f xvcmpgtsp. vs40,vs50,vs60
-+ 10c: f1 12 e7 87 xvcpsgndp vs40,vs50,vs60
-+ 110: f1 1c e7 87 xvmovdp vs40,vs60
-+ 114: f1 1c e7 87 xvmovdp vs40,vs60
-+ 118: f1 12 e6 87 xvcpsgnsp vs40,vs50,vs60
-+ 11c: f1 1c e6 87 xvmovsp vs40,vs60
-+ 120: f1 1c e6 87 xvmovsp vs40,vs60
-+ 124: f1 00 e6 27 xvcvdpsp vs40,vs60
-+ 128: f1 00 e7 63 xvcvdpsxds vs40,vs60
-+ 12c: f1 00 e3 63 xvcvdpsxws vs40,vs60
-+ 130: f1 00 e7 23 xvcvdpuxds vs40,vs60
-+ 134: f1 00 e3 23 xvcvdpuxws vs40,vs60
-+ 138: f1 00 e7 27 xvcvspdp vs40,vs60
-+ 13c: f1 00 e6 63 xvcvspsxds vs40,vs60
-+ 140: f1 00 e2 63 xvcvspsxws vs40,vs60
-+ 144: f1 00 e6 23 xvcvspuxds vs40,vs60
-+ 148: f1 00 e2 23 xvcvspuxws vs40,vs60
-+ 14c: f1 00 e7 e3 xvcvsxddp vs40,vs60
-+ 150: f1 00 e6 e3 xvcvsxdsp vs40,vs60
-+ 154: f1 00 e3 e3 xvcvsxwdp vs40,vs60
-+ 158: f1 00 e2 e3 xvcvsxwsp vs40,vs60
-+ 15c: f1 00 e7 a3 xvcvuxddp vs40,vs60
-+ 160: f1 00 e6 a3 xvcvuxdsp vs40,vs60
-+ 164: f1 00 e3 a3 xvcvuxwdp vs40,vs60
-+ 168: f1 00 e2 a3 xvcvuxwsp vs40,vs60
-+ 16c: f1 12 e3 c7 xvdivdp vs40,vs50,vs60
-+ 170: f1 12 e2 c7 xvdivsp vs40,vs50,vs60
-+ 174: f1 12 e3 0f xvmaddadp vs40,vs50,vs60
-+ 178: f1 12 e3 4f xvmaddmdp vs40,vs50,vs60
-+ 17c: f1 12 e2 0f xvmaddasp vs40,vs50,vs60
-+ 180: f1 12 e2 4f xvmaddmsp vs40,vs50,vs60
-+ 184: f1 12 e7 07 xvmaxdp vs40,vs50,vs60
-+ 188: f1 12 e6 07 xvmaxsp vs40,vs50,vs60
-+ 18c: f1 12 e7 47 xvmindp vs40,vs50,vs60
-+ 190: f1 12 e6 47 xvminsp vs40,vs50,vs60
-+ 194: f1 12 e3 8f xvmsubadp vs40,vs50,vs60
-+ 198: f1 12 e3 cf xvmsubmdp vs40,vs50,vs60
-+ 19c: f1 12 e2 8f xvmsubasp vs40,vs50,vs60
-+ 1a0: f1 12 e2 cf xvmsubmsp vs40,vs50,vs60
-+ 1a4: f1 12 e3 87 xvmuldp vs40,vs50,vs60
-+ 1a8: f1 12 e2 87 xvmulsp vs40,vs50,vs60
-+ 1ac: f1 00 e7 a7 xvnabsdp vs40,vs60
-+ 1b0: f1 00 e6 a7 xvnabssp vs40,vs60
-+ 1b4: f1 00 e7 e7 xvnegdp vs40,vs60
-+ 1b8: f1 00 e6 e7 xvnegsp vs40,vs60
-+ 1bc: f1 12 e7 0f xvnmaddadp vs40,vs50,vs60
-+ 1c0: f1 12 e7 4f xvnmaddmdp vs40,vs50,vs60
-+ 1c4: f1 12 e6 0f xvnmaddasp vs40,vs50,vs60
-+ 1c8: f1 12 e6 4f xvnmaddmsp vs40,vs50,vs60
-+ 1cc: f1 12 e7 8f xvnmsubadp vs40,vs50,vs60
-+ 1d0: f1 12 e7 cf xvnmsubmdp vs40,vs50,vs60
-+ 1d4: f1 12 e6 8f xvnmsubasp vs40,vs50,vs60
-+ 1d8: f1 12 e6 cf xvnmsubmsp vs40,vs50,vs60
-+ 1dc: f1 00 e3 27 xvrdpi vs40,vs60
-+ 1e0: f1 00 e3 af xvrdpic vs40,vs60
-+ 1e4: f1 00 e3 e7 xvrdpim vs40,vs60
-+ 1e8: f1 00 e3 a7 xvrdpip vs40,vs60
-+ 1ec: f1 00 e3 67 xvrdpiz vs40,vs60
-+ 1f0: f1 00 e3 6b xvredp vs40,vs60
-+ 1f4: f1 00 e2 6b xvresp vs40,vs60
-+ 1f8: f1 00 e2 27 xvrspi vs40,vs60
-+ 1fc: f1 00 e2 af xvrspic vs40,vs60
-+ 200: f1 00 e2 e7 xvrspim vs40,vs60
-+ 204: f1 00 e2 a7 xvrspip vs40,vs60
-+ 208: f1 00 e2 67 xvrspiz vs40,vs60
-+ 20c: f1 00 e3 2b xvrsqrtedp vs40,vs60
-+ 210: f1 00 e2 2b xvrsqrtesp vs40,vs60
-+ 214: f1 00 e3 2f xvsqrtdp vs40,vs60
-+ 218: f1 00 e2 2f xvsqrtsp vs40,vs60
-+ 21c: f1 12 e3 47 xvsubdp vs40,vs50,vs60
-+ 220: f1 12 e2 47 xvsubsp vs40,vs50,vs60
-+ 224: f0 92 e3 ee xvtdivdp cr1,vs50,vs60
-+ 228: f0 92 e2 ee xvtdivsp cr1,vs50,vs60
-+ 22c: f0 80 e3 aa xvtsqrtdp cr1,vs60
-+ 230: f0 80 e2 aa xvtsqrtsp cr1,vs60
-+ 234: f1 12 e4 17 xxland vs40,vs50,vs60
-+ 238: f1 12 e4 57 xxlandc vs40,vs50,vs60
-+ 23c: f1 12 e5 17 xxlnor vs40,vs50,vs60
-+ 240: f1 12 e4 97 xxlor vs40,vs50,vs60
-+ 244: f1 12 e4 d7 xxlxor vs40,vs50,vs60
-+ 248: f1 12 e0 97 xxmrghw vs40,vs50,vs60
-+ 24c: f1 12 e1 97 xxmrglw vs40,vs50,vs60
-+ 250: f1 12 e0 57 xxmrghd vs40,vs50,vs60
-+ 254: f1 12 e1 57 xxpermdi vs40,vs50,vs60,1
-+ 258: f1 12 e2 57 xxpermdi vs40,vs50,vs60,2
-+ 25c: f1 12 e3 57 xxmrgld vs40,vs50,vs60
-+ 260: f1 12 90 57 xxspltd vs40,vs50,0
-+ 264: f1 12 90 57 xxspltd vs40,vs50,0
-+ 268: f1 12 93 57 xxspltd vs40,vs50,1
-+ 26c: f1 12 93 57 xxspltd vs40,vs50,1
-+ 270: f1 12 e0 57 xxmrghd vs40,vs50,vs60
-+ 274: f1 12 e0 57 xxmrghd vs40,vs50,vs60
-+ 278: f1 12 e3 57 xxmrgld vs40,vs50,vs60
-+ 27c: f1 12 92 57 xxswapd vs40,vs50
-+ 280: f1 12 92 57 xxswapd vs40,vs50
-+ 284: f1 12 e7 bf xxsel vs40,vs50,vs60,vs62
-+ 288: f1 12 e2 17 xxsldwi vs40,vs50,vs60,2
-+ 28c: f1 02 e2 93 xxspltw vs40,vs60,2
-diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/vsx.s binutils-2.19.1/gas/testsuite/gas/ppc/vsx.s
---- binutils-2.19.1.orig/gas/testsuite/gas/ppc/vsx.s 1969-12-31 16:00:00.000000000 -0800
-+++ binutils-2.19.1/gas/testsuite/gas/ppc/vsx.s 2009-03-02 05:59:36.000000000 -0800
-@@ -0,0 +1,166 @@
-+ .section ".text"
-+start:
-+ lxsdx 40,10,20
-+ lxsdux 40,10,20
-+ lxvd2x 40,10,20
-+ lxvd2ux 40,10,20
-+ lxvdsx 40,10,20
-+ lxvw4x 40,10,20
-+ lxvw4ux 40,10,20
-+ stxsdx 40,10,20
-+ stxsdux 40,10,20
-+ stxvd2x 40,10,20
-+ stxvd2ux 40,10,20
-+ stxvw4x 40,10,20
-+ stxvw4ux 40,10,20
-+ xsabsdp 40,60
-+ xsadddp 40,50,60
-+ xscmpodp 1,50,60
-+ xscmpudp 1,50,60
-+ xscpsgndp 40,50,60
-+ xscvdpsp 40,60
-+ xscvdpsxds 40,60
-+ xscvdpsxws 40,60
-+ xscvdpuxds 40,60
-+ xscvdpuxws 40,60
-+ xscvspdp 40,60
-+ xscvsxddp 40,60
-+ xscvuxddp 40,60
-+ xsdivdp 40,50,60
-+ xsmaddadp 40,50,60
-+ xsmaddmdp 40,50,60
-+ xsmaxdp 40,50,60
-+ xsmindp 40,50,60
-+ xsmsubadp 40,50,60
-+ xsmsubmdp 40,50,60
-+ xsmuldp 40,50,60
-+ xsnabsdp 40,60
-+ xsnegdp 40,60
-+ xsnmaddadp 40,50,60
-+ xsnmaddmdp 40,50,60
-+ xsnmsubadp 40,50,60
-+ xsnmsubmdp 40,50,60
-+ xsrdpi 40,60
-+ xsrdpic 40,60
-+ xsrdpim 40,60
-+ xsrdpip 40,60
-+ xsrdpiz 40,60
-+ xsredp 40,60
-+ xsrsqrtedp 40,60
-+ xssqrtdp 40,60
-+ xssubdp 40,50,60
-+ xstdivdp 1,50,60
-+ xstsqrtdp 1,60
-+ xvabsdp 40,60
-+ xvabssp 40,60
-+ xvadddp 40,50,60
-+ xvaddsp 40,50,60
-+ xvcmpeqdp 40,50,60
-+ xvcmpeqdp. 40,50,60
-+ xvcmpeqsp 40,50,60
-+ xvcmpeqsp. 40,50,60
-+ xvcmpgedp 40,50,60
-+ xvcmpgedp. 40,50,60
-+ xvcmpgesp 40,50,60
-+ xvcmpgesp. 40,50,60
-+ xvcmpgtdp 40,50,60
-+ xvcmpgtdp. 40,50,60
-+ xvcmpgtsp 40,50,60
-+ xvcmpgtsp. 40,50,60
-+ xvcpsgndp 40,50,60
-+ xvmovdp 40,60
-+ xvcpsgndp 40,60,60
-+ xvcpsgnsp 40,50,60
-+ xvmovsp 40,60
-+ xvcpsgnsp 40,60,60
-+ xvcvdpsp 40,60
-+ xvcvdpsxds 40,60
-+ xvcvdpsxws 40,60
-+ xvcvdpuxds 40,60
-+ xvcvdpuxws 40,60
-+ xvcvspdp 40,60
-+ xvcvspsxds 40,60
-+ xvcvspsxws 40,60
-+ xvcvspuxds 40,60
-+ xvcvspuxws 40,60
-+ xvcvsxddp 40,60
-+ xvcvsxdsp 40,60
-+ xvcvsxwdp 40,60
-+ xvcvsxwsp 40,60
-+ xvcvuxddp 40,60
-+ xvcvuxdsp 40,60
-+ xvcvuxwdp 40,60
-+ xvcvuxwsp 40,60
-+ xvdivdp 40,50,60
-+ xvdivsp 40,50,60
-+ xvmaddadp 40,50,60
-+ xvmaddmdp 40,50,60
-+ xvmaddasp 40,50,60
-+ xvmaddmsp 40,50,60
-+ xvmaxdp 40,50,60
-+ xvmaxsp 40,50,60
-+ xvmindp 40,50,60
-+ xvminsp 40,50,60
-+ xvmsubadp 40,50,60
-+ xvmsubmdp 40,50,60
-+ xvmsubasp 40,50,60
-+ xvmsubmsp 40,50,60
-+ xvmuldp 40,50,60
-+ xvmulsp 40,50,60
-+ xvnabsdp 40,60
-+ xvnabssp 40,60
-+ xvnegdp 40,60
-+ xvnegsp 40,60
-+ xvnmaddadp 40,50,60
-+ xvnmaddmdp 40,50,60
-+ xvnmaddasp 40,50,60
-+ xvnmaddmsp 40,50,60
-+ xvnmsubadp 40,50,60
-+ xvnmsubmdp 40,50,60
-+ xvnmsubasp 40,50,60
-+ xvnmsubmsp 40,50,60
-+ xvrdpi 40,60
-+ xvrdpic 40,60
-+ xvrdpim 40,60
-+ xvrdpip 40,60
-+ xvrdpiz 40,60
-+ xvredp 40,60
-+ xvresp 40,60
-+ xvrspi 40,60
-+ xvrspic 40,60
-+ xvrspim 40,60
-+ xvrspip 40,60
-+ xvrspiz 40,60
-+ xvrsqrtedp 40,60
-+ xvrsqrtesp 40,60
-+ xvsqrtdp 40,60
-+ xvsqrtsp 40,60
-+ xvsubdp 40,50,60
-+ xvsubsp 40,50,60
-+ xvtdivdp 1,50,60
-+ xvtdivsp 1,50,60
-+ xvtsqrtdp 1,60
-+ xvtsqrtsp 1,60
-+ xxland 40,50,60
-+ xxlandc 40,50,60
-+ xxlnor 40,50,60
-+ xxlor 40,50,60
-+ xxlxor 40,50,60
-+ xxmrghw 40,50,60
-+ xxmrglw 40,50,60
-+ xxpermdi 40,50,60,0b00
-+ xxpermdi 40,50,60,0b01
-+ xxpermdi 40,50,60,0b10
-+ xxpermdi 40,50,60,0b11
-+ xxspltd 40,50,0
-+ xxpermdi 40,50,50,0b00
-+ xxspltd 40,50,1
-+ xxpermdi 40,50,50,0b11
-+ xxmrghd 40,50,60
-+ xxpermdi 40,50,60,0b00
-+ xxmrgld 40,50,60
-+ xxpermdi 40,50,50,0b10
-+ xxswapd 40,50
-+ xxsel 40,50,60,62
-+ xxsldwi 40,50,60,2
-+ xxspltw 40,60,2
-diff -Naur binutils-2.19.1.orig/include/elf/ChangeLog binutils-2.19.1/include/elf/ChangeLog
---- binutils-2.19.1.orig/include/elf/ChangeLog 2008-08-20 16:28:58.000000000 -0700
-+++ binutils-2.19.1/include/elf/ChangeLog 2009-03-02 05:41:07.000000000 -0800
-@@ -1,3 +1,11 @@
-+2009-03-02 Alan Modra <amodra@bigpond.net.au>
-+
-+ 2008-11-14 Nathan Sidwell <nathan@codesourcery.com>
-+ * internal.h (struct elf_segment_map): Add header_size field.
-+
-+ 2008-10-10 Nathan Froyd <froydnj@codesourcery.com>
-+ * ppc.h: Add Tag_GNU_Power_ABI_Struct_Return.
-+
- 2008-08-20 Bob Wilson <bob.wilson@acm.org>
-
- * xtensa.h (R_XTENSA_TLSDESC_FN, R_XTENSA_TLSDESC_ARG)
-diff -Naur binutils-2.19.1.orig/include/elf/internal.h binutils-2.19.1/include/elf/internal.h
---- binutils-2.19.1.orig/include/elf/internal.h 2008-03-12 22:27:41.000000000 -0700
-+++ binutils-2.19.1/include/elf/internal.h 2009-03-02 05:41:07.000000000 -0800
-@@ -266,6 +266,8 @@
- bfd_vma p_align;
- /* Segment size in file and memory */
- bfd_vma p_size;
-+ /* Required size of filehdr + phdrs, if non-zero */
-+ bfd_vma header_size;
- /* Whether the p_flags field is valid; if not, the flags are based
- on the section flags. */
- unsigned int p_flags_valid : 1;
-diff -Naur binutils-2.19.1.orig/include/elf/ppc.h binutils-2.19.1/include/elf/ppc.h
---- binutils-2.19.1.orig/include/elf/ppc.h 2008-07-26 06:10:47.000000000 -0700
-+++ binutils-2.19.1/include/elf/ppc.h 2009-03-02 05:35:25.000000000 -0800
-@@ -186,6 +186,11 @@
- registers, 3 for SPE registers; 0 for not tagged or not using any
- ABIs affected by the differences. */
- Tag_GNU_Power_ABI_Vector = 8,
-+
-+ /* Value 1 for ABIs using r3/r4 for returning structures <= 8 bytes,
-+ 2 for ABIs using memory; 0 for not tagged or not using any ABIs
-+ affected by the differences. */
-+ Tag_GNU_Power_ABI_Struct_Return = 12
- };
-
- #endif /* _ELF_PPC_H */
-diff -Naur binutils-2.19.1.orig/include/opcode/ChangeLog binutils-2.19.1/include/opcode/ChangeLog
---- binutils-2.19.1.orig/include/opcode/ChangeLog 2008-08-28 07:07:48.000000000 -0700
-+++ binutils-2.19.1/include/opcode/ChangeLog 2009-03-02 05:59:36.000000000 -0800
-@@ -1,3 +1,12 @@
-+2009-03-02 Alan Modra <amodra@bigpond.net.au>
-+
-+ 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
-+ * ppc.h (PPC_OPCODE_POWER7): New.
-+
-+ 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
-+ * ppc.h (struct powerpc_opcode): New field "deprecated".
-+ (PPC_OPCODE_NOPOWER4): Delete.
-+
- 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
-
- * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
-diff -Naur binutils-2.19.1.orig/include/opcode/ppc.h binutils-2.19.1/include/opcode/ppc.h
---- binutils-2.19.1.orig/include/opcode/ppc.h 2008-08-01 21:38:51.000000000 -0700
-+++ binutils-2.19.1/include/opcode/ppc.h 2009-03-02 05:59:36.000000000 -0800
-@@ -46,6 +46,11 @@
- are listed below. */
- ppc_cpu_t flags;
-
-+ /* One bit flags for the opcode. These are used to indicate which
-+ specific processors no longer support the instructions. The defined
-+ values are listed below. */
-+ ppc_cpu_t deprecated;
-+
- /* An array of operand codes. Each code is an index into the
- operand table. They appear in the order which the operands must
- appear in assembly code, and are terminated by a zero. */
-@@ -109,8 +114,8 @@
- /* Opcode is only supported by Power4 architecture. */
- #define PPC_OPCODE_POWER4 0x4000
-
--/* Opcode isn't supported by Power4 architecture. */
--#define PPC_OPCODE_NOPOWER4 0x8000
-+/* Opcode is only supported by Power7 architecture. */
-+#define PPC_OPCODE_POWER7 0x8000
-
- /* Opcode is only supported by POWERPC Classic architecture. */
- #define PPC_OPCODE_CLASSIC 0x10000
-diff -Naur binutils-2.19.1.orig/ld/ChangeLog binutils-2.19.1/ld/ChangeLog
---- binutils-2.19.1.orig/ld/ChangeLog 2009-02-02 02:31:31.000000000 -0800
-+++ binutils-2.19.1/ld/ChangeLog 2009-03-02 05:56:19.000000000 -0800
-@@ -1,3 +1,65 @@
-+2009-03-02 Alan Modra <amodra@bigpond.net.au>
-+
-+ 2009-02-16 Alan Modra <amodra@bigpond.net.au>
-+ * ldlang.c (push_stat_ptr, pop_stat_ptr): New functions.
-+ (stat_save, stat_save_ptr): New variables.
-+ (lang_insert_orphan): Use push_stat_ptr and pop_stat_ptr.
-+ (load_symbols): Likewise. Delete dead "bad_load" code.
-+ (open_input_bfds): Warn on script containing output sections.
-+ (lang_enter_output_section_statement): Use push_stat_ptr.
-+ (lang_enter_group): Likewise.
-+ (lang_leave_output_section_statement): Use pop_stat_ptr.
-+ (lang_leave_group): Likewise.
-+ * ldlang.h (push_stat_ptr, pop_stat_ptr): Declare.
-+ * ldctor.c (ldctor_build_sets): Use push_stat_ptr and pop_stat_ptr.
-+ * emultempl/beos.em (gld_${EMULATION_NAME}_set_symbols): Likewise.
-+ * emultempl/pe.em (gld_${EMULATION_NAME}_set_symbols): Likewise.
-+ * emultempl/pep.em (gld_${EMULATION_NAME}_set_symbols): Likewise.
-+ * emultempl/xtensaelf.em (ld_xtensa_insert_page_offsets): Likewise.
-+
-+ 2008-10-04 Alan Modra <amodra@bigpond.net.au>
-+ PR 6931
-+ * ldemul.c (ldemul_place_orphan): Add "constraint" param.
-+ * ldemul.h (ldemul_place_orphan): Update prototype.
-+ (struct ld_emulation_xfer_struct <place_orphan>): Likewise add param.
-+ * ldlang.c (unique_section_p): Make static.
-+ (lang_output_section_statement_lookup): Optimise creation of SPECIAL
-+ sections.
-+ (lang_insert_orphan): Add "constraint" param. Pass to
-+ lang_enter_output_section_statement.
-+ (init_os): Don't use an existing bfd section for SPECIAL sections.
-+ (lang_place_orphans): Don't rename unique output sections, instead
-+ mark their output section statements SPECIAL.
-+ * ldlang.h (lang_insert_orphan): Update prototype.
-+ (unique_section_p): Delete.
-+ * emultempl/beos.em (place_orphan): Add "constraint" param.
-+ * emultempl/elf32.em (place_orphan): Likewise. Don't match existing
-+ output sections if set.
-+ * emultempl/pe.em (place_orphan): Likewise.
-+ * emultempl/pep.em (place_orphan): Likewise.
-+ * emultempl/mmo.em (mmo_place_orphan): Update.
-+ * emultempl/spuelf.em (spu_place_special_section): Update.
-+
-+ 2008-10-03 Alan Modra <amodra@bigpond.net.au>
-+ PR 6931
-+ * ldemul.c (ldemul_place_orphan): Add "name" param.
-+ * ldemul.h (ldemul_place_orphan): Update prototype.
-+ (struct ld_emulation_xfer_struct <place_orphan>): Likewise.
-+ * ldlang.c (lang_place_orphans): Generate unique section names here..
-+ * emultempl/elf32.em (place_orphan): ..rather than here. Don't
-+ directly use an existing output section statement that has no
-+ bfd section.
-+ * emultempl/pe.em (place_orphan): Likewise.
-+ * emultempl/pep.em (place_orphan): Likewise.
-+ * emultempl/beos.em (place_orphan): Adjust.
-+ * emultempl/spuelf.em (spu_place_special_section): Adjust
-+ place_orphan call.
-+ * emultempl/genelf.em (gld${EMULATION_NAME}_after_open): New function.
-+ (LDEMUL_AFTER_OPEN): Define.
-+
-+ 2008-09-25 Alan Modra <amodra@bigpond.net.au>
-+ * ldexp.c (fold_binary): Evaluate rhs when lhs not valid.
-+
- 2009-02-02 Tristan Gingold <gingold@adacore.com>
-
- * deffilep.c: Add autogenerated file.
-diff -Naur binutils-2.19.1.orig/ld/emultempl/beos.em binutils-2.19.1/ld/emultempl/beos.em
---- binutils-2.19.1.orig/ld/emultempl/beos.em 2008-09-08 17:10:16.000000000 -0700
-+++ binutils-2.19.1/ld/emultempl/beos.em 2009-03-02 05:56:19.000000000 -0800
-@@ -8,7 +8,7 @@
- fragment <<EOF
- /* This file is part of GLD, the Gnu Linker.
- Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
-- 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
-+ 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
-
- This file is part of the GNU Binutils.
-
-@@ -330,7 +330,6 @@
- /* Run through and invent symbols for all the
- names and insert the defaults. */
- int j;
-- lang_statement_list_type *save;
-
- if (!init[IMAGEBASEOFF].inited)
- {
-@@ -347,9 +346,7 @@
- return;
-
- /* Glue the assignments into the abs section */
-- save = stat_ptr;
--
-- stat_ptr = &(abs_output_section->children);
-+ push_stat_ptr (&abs_output_section->children);
-
- for (j = 0; init[j].ptr; j++)
- {
-@@ -367,7 +364,7 @@
- else abort();
- }
- /* Restore the pointer. */
-- stat_ptr = save;
-+ pop_stat_ptr ();
-
- if (pe.FileAlignment >
- pe.SectionAlignment)
-@@ -609,8 +606,6 @@
- static void
- gld_${EMULATION_NAME}_before_allocation (void)
- {
-- extern lang_statement_list_type *stat_ptr;
--
- #ifdef TARGET_IS_ppcpe
- /* Here we rummage through the found bfds to collect toc information */
- {
-@@ -665,9 +660,10 @@
- which are not mentioned in the linker script. */
-
- static bfd_boolean
--gld${EMULATION_NAME}_place_orphan (asection *s)
-+gld${EMULATION_NAME}_place_orphan (asection *s,
-+ const char *secname,
-+ int constraint)
- {
-- const char *secname;
- char *output_secname, *ps;
- lang_output_section_statement_type *os;
- lang_statement_union_type *l;
-@@ -682,8 +678,6 @@
- if (link_info.relocatable)
- return FALSE;
-
-- secname = bfd_get_section_name (s->owner, s);
--
- /* Everything from the '\$' on gets deleted so don't allow '\$' as the
- first character. */
- if (*secname == '\$')
-@@ -697,7 +691,7 @@
- output_secname = xstrdup (secname);
- ps = strchr (output_secname + 1, '\$');
- *ps = 0;
-- os = lang_output_section_statement_lookup (output_secname, 0, TRUE);
-+ os = lang_output_section_statement_lookup (output_secname, constraint, TRUE);
-
- /* Find the '\$' wild statement for this section. We currently require the
- linker script to explicitly mention "*(.foo\$)".
-diff -Naur binutils-2.19.1.orig/ld/emultempl/elf32.em binutils-2.19.1/ld/emultempl/elf32.em
---- binutils-2.19.1.orig/ld/emultempl/elf32.em 2008-09-06 21:02:31.000000000 -0700
-+++ binutils-2.19.1/ld/emultempl/elf32.em 2009-03-02 05:34:03.000000000 -0800
-@@ -62,7 +62,8 @@
- static void gld${EMULATION_NAME}_before_parse (void);
- static void gld${EMULATION_NAME}_after_open (void);
- static void gld${EMULATION_NAME}_before_allocation (void);
--static bfd_boolean gld${EMULATION_NAME}_place_orphan (asection *s);
-+static bfd_boolean gld${EMULATION_NAME}_place_orphan
-+ (asection *, const char *, int);
- static void gld${EMULATION_NAME}_finish (void);
-
- EOF
-@@ -1635,7 +1636,9 @@
- sections in the right segment. */
-
- static bfd_boolean
--gld${EMULATION_NAME}_place_orphan (asection *s)
-+gld${EMULATION_NAME}_place_orphan (asection *s,
-+ const char *secname,
-+ int constraint)
- {
- static struct orphan_save hold[] =
- {
-@@ -1673,15 +1676,12 @@
- };
- static int orphan_init_done = 0;
- struct orphan_save *place;
-- const char *secname;
- lang_output_section_statement_type *after;
- lang_output_section_statement_type *os;
- int isdyn = 0;
- int iself = s->owner->xvec->flavour == bfd_target_elf_flavour;
- unsigned int sh_type = iself ? elf_section_type (s) : SHT_NULL;
-
-- secname = bfd_get_section_name (s->owner, s);
--
- if (! link_info.relocatable
- && link_info.combreloc
- && (s->flags & SEC_ALLOC))
-@@ -1707,28 +1707,23 @@
- }
- }
-
-- if (isdyn || (!config.unique_orphan_sections && !unique_section_p (s)))
-- {
-- /* Look through the script to see where to place this section. */
-- os = lang_output_section_find (secname);
--
-- if (os != NULL
-- && (os->bfd_section == NULL
-- || os->bfd_section->flags == 0
-- || (_bfd_elf_match_sections_by_type (link_info.output_bfd,
-- os->bfd_section,
-- s->owner, s)
-- && ((s->flags ^ os->bfd_section->flags)
-- & (SEC_LOAD | SEC_ALLOC)) == 0)))
-- {
-- /* We already have an output section statement with this
-- name, and its bfd section, if any, has compatible flags.
-- If the section already exists but does not have any flags
-- set, then it has been created by the linker, probably as a
-- result of a --section-start command line switch. */
-- lang_add_section (&os->children, s, os);
-- return TRUE;
-- }
-+ /* Look through the script to see where to place this section. */
-+ if (constraint == 0
-+ && (os = lang_output_section_find (secname)) != NULL
-+ && os->bfd_section != NULL
-+ && (os->bfd_section->flags == 0
-+ || (_bfd_elf_match_sections_by_type (link_info.output_bfd,
-+ os->bfd_section, s->owner, s)
-+ && ((s->flags ^ os->bfd_section->flags)
-+ & (SEC_LOAD | SEC_ALLOC)) == 0)))
-+ {
-+ /* We already have an output section statement with this
-+ name, and its bfd section has compatible flags.
-+ If the section already exists but does not have any flags
-+ set, then it has been created by the linker, probably as a
-+ result of a --section-start command line switch. */
-+ lang_add_section (&os->children, s, os);
-+ return TRUE;
- }
-
- if (!orphan_init_done)
-@@ -1748,7 +1743,7 @@
- sections into the .text section to get them out of the way. */
- if (link_info.executable
- && ! link_info.relocatable
-- && CONST_STRNEQ (secname, ".gnu.warning.")
-+ && CONST_STRNEQ (s->name, ".gnu.warning.")
- && hold[orphan_text].os != NULL)
- {
- lang_add_section (&hold[orphan_text].os->children, s,
-@@ -1803,19 +1798,7 @@
- after = &lang_output_section_statement.head->output_section_statement;
- }
-
-- /* Choose a unique name for the section. This will be needed if the
-- same section name appears in the input file with different
-- loadable or allocatable characteristics. */
-- if (bfd_get_section_by_name (link_info.output_bfd, secname) != NULL)
-- {
-- static int count = 1;
-- secname = bfd_get_unique_section_name (link_info.output_bfd,
-- secname, &count);
-- if (secname == NULL)
-- einfo ("%F%P: place_orphan failed: %E\n");
-- }
--
-- lang_insert_orphan (s, secname, after, place, NULL, NULL);
-+ lang_insert_orphan (s, secname, constraint, after, place, NULL, NULL);
-
- return TRUE;
- }
-diff -Naur binutils-2.19.1.orig/ld/emultempl/genelf.em binutils-2.19.1/ld/emultempl/genelf.em
---- binutils-2.19.1.orig/ld/emultempl/genelf.em 2007-07-19 12:56:10.000000000 -0700
-+++ binutils-2.19.1/ld/emultempl/genelf.em 2009-03-02 05:32:55.000000000 -0800
-@@ -34,7 +34,27 @@
- gld${EMULATION_NAME}_map_segments (FALSE);
- finish_default ();
- }
-+
-+static void
-+gld${EMULATION_NAME}_after_open (void)
-+{
-+ bfd *ibfd;
-+ asection *sec;
-+ asymbol **syms;
-+
-+ if (link_info.relocatable)
-+ for (ibfd = link_info.input_bfds; ibfd != NULL; ibfd = ibfd->link_next)
-+ if ((syms = bfd_get_outsymbols (ibfd)) != NULL
-+ && bfd_get_flavour (ibfd) == bfd_target_elf_flavour)
-+ for (sec = ibfd->sections; sec != NULL; sec = sec->next)
-+ if ((sec->flags & (SEC_GROUP | SEC_LINKER_CREATED)) == SEC_GROUP)
-+ {
-+ struct bfd_elf_section_data *sec_data = elf_section_data (sec);
-+ elf_group_id (sec) = syms[sec_data->this_hdr.sh_info - 1];
-+ }
-+}
- EOF
- # Put these extra routines in ld_${EMULATION_NAME}_emulation
- #
- LDEMUL_FINISH=gld${EMULATION_NAME}_finish
-+LDEMUL_AFTER_OPEN=gld${EMULATION_NAME}_after_open
-diff -Naur binutils-2.19.1.orig/ld/emultempl/mmo.em binutils-2.19.1/ld/emultempl/mmo.em
---- binutils-2.19.1.orig/ld/emultempl/mmo.em 2008-02-14 19:35:53.000000000 -0800
-+++ binutils-2.19.1/ld/emultempl/mmo.em 2009-03-02 05:34:03.000000000 -0800
-@@ -47,7 +47,9 @@
- from elf32.em. */
-
- static bfd_boolean
--mmo_place_orphan (asection *s)
-+mmo_place_orphan (asection *s,
-+ const char *secname,
-+ int constraint ATTRIBUTE_UNUSED)
- {
- static struct orphan_save hold_text =
- {
-@@ -56,7 +58,6 @@
- 0, 0, 0, 0
- };
- struct orphan_save *place;
-- const char *secname;
- lang_output_section_statement_type *after;
- lang_output_section_statement_type *os;
-
-@@ -66,7 +67,6 @@
- return FALSE;
-
- /* Only care for sections we're going to load. */
-- secname = s->name;
- os = lang_output_section_find (secname);
-
- /* We have an output section by this name. Place the section inside it
-@@ -93,7 +93,7 @@
-
- /* If there's an output section by this name, we'll use it, regardless
- of section flags, in contrast to what's done in elf32.em. */
-- os = lang_insert_orphan (s, secname, after, place, NULL, NULL);
-+ os = lang_insert_orphan (s, secname, 0, after, place, NULL, NULL);
-
- /* We need an output section for .text as a root, so if there was none
- (might happen with a peculiar linker script such as in "map
-diff -Naur binutils-2.19.1.orig/ld/emultempl/pe.em binutils-2.19.1/ld/emultempl/pe.em
---- binutils-2.19.1.orig/ld/emultempl/pe.em 2008-09-09 02:49:56.000000000 -0700
-+++ binutils-2.19.1/ld/emultempl/pe.em 2009-03-02 05:56:19.000000000 -0800
-@@ -10,7 +10,7 @@
- (echo;echo;echo;echo;echo)>e${EMULATION_NAME}.c # there, now line numbers match ;-)
- fragment <<EOF
- /* Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
-- 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
-+ 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
-
- This file is part of the GNU Binutils.
-
-@@ -697,7 +697,6 @@
- /* Run through and invent symbols for all the
- names and insert the defaults. */
- int j;
-- lang_statement_list_type *save;
-
- if (!init[IMAGEBASEOFF].inited)
- {
-@@ -720,9 +719,7 @@
- return;
-
- /* Glue the assignments into the abs section. */
-- save = stat_ptr;
--
-- stat_ptr = &(abs_output_section->children);
-+ push_stat_ptr (&abs_output_section->children);
-
- for (j = 0; init[j].ptr; j++)
- {
-@@ -744,7 +741,7 @@
- image_base_statement = rv;
- }
- /* Restore the pointer. */
-- stat_ptr = save;
-+ pop_stat_ptr ();
-
- if (pe.FileAlignment >
- pe.SectionAlignment)
-@@ -1613,40 +1610,37 @@
- sort_sections. */
-
- static bfd_boolean
--gld_${EMULATION_NAME}_place_orphan (asection *s)
-+gld_${EMULATION_NAME}_place_orphan (asection *s,
-+ const char *secname,
-+ int constraint)
- {
-- const char *secname;
-- const char *orig_secname;
-+ const char *orig_secname = secname;
- char *dollar = NULL;
- lang_output_section_statement_type *os;
- lang_statement_list_type add_child;
-
-- secname = bfd_get_section_name (s->owner, s);
--
- /* Look through the script to see where to place this section. */
-- orig_secname = secname;
- if (!link_info.relocatable
- && (dollar = strchr (secname, '$')) != NULL)
- {
-- size_t len = dollar - orig_secname;
-+ size_t len = dollar - secname;
- char *newname = xmalloc (len + 1);
-- memcpy (newname, orig_secname, len);
-+ memcpy (newname, secname, len);
- newname[len] = '\0';
- secname = newname;
- }
-
-- os = lang_output_section_find (secname);
--
- lang_list_init (&add_child);
-
-- if (os != NULL
-- && (os->bfd_section == NULL
-- || os->bfd_section->flags == 0
-+ if (constraint == 0
-+ && (os = lang_output_section_find (secname)) != NULL
-+ && os->bfd_section != NULL
-+ && (os->bfd_section->flags == 0
- || ((s->flags ^ os->bfd_section->flags)
- & (SEC_LOAD | SEC_ALLOC)) == 0))
- {
- /* We already have an output section statement with this
-- name, and its bfd section, if any, has compatible flags.
-+ name, and its bfd section has compatible flags.
- If the section already exists but does not have any flags set,
- then it has been created by the linker, probably as a result of
- a --section-start command line switch. */
-@@ -1723,21 +1717,10 @@
- ->output_section_statement);
- }
-
-- /* Choose a unique name for the section. This will be needed if the
-- same section name appears in the input file with different
-- loadable or allocatable characteristics. */
-- if (bfd_get_section_by_name (link_info.output_bfd, secname) != NULL)
-- {
-- static int count = 1;
-- secname = bfd_get_unique_section_name (link_info.output_bfd,
-- secname, &count);
-- if (secname == NULL)
-- einfo ("%F%P: place_orphan failed: %E\n");
-- }
--
- /* All sections in an executable must be aligned to a page boundary. */
- address = exp_unop (ALIGN_K, exp_nameop (NAME, "__section_alignment__"));
-- os = lang_insert_orphan (s, secname, after, place, address, &add_child);
-+ os = lang_insert_orphan (s, secname, constraint, after, place, address,
-+ &add_child);
- }
-
- {
-diff -Naur binutils-2.19.1.orig/ld/emultempl/pep.em binutils-2.19.1/ld/emultempl/pep.em
---- binutils-2.19.1.orig/ld/emultempl/pep.em 2008-09-09 02:49:56.000000000 -0700
-+++ binutils-2.19.1/ld/emultempl/pep.em 2009-03-02 05:56:19.000000000 -0800
-@@ -9,7 +9,7 @@
- rm -f e${EMULATION_NAME}.c
- (echo;echo;echo;echo;echo)>e${EMULATION_NAME}.c # there, now line numbers match ;-)
- fragment <<EOF
--/* Copyright 2006, 2007, 2008 Free Software Foundation, Inc.
-+/* Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
- Written by Kai Tietz, OneVision Software GmbH&CoKg.
-
- This file is part of the GNU Binutils.
-@@ -657,7 +657,6 @@
- /* Run through and invent symbols for all the
- names and insert the defaults. */
- int j;
-- lang_statement_list_type *save;
-
- if (!init[IMAGEBASEOFF].inited)
- {
-@@ -680,9 +679,7 @@
- return;
-
- /* Glue the assignments into the abs section. */
-- save = stat_ptr;
--
-- stat_ptr = &(abs_output_section->children);
-+ push_stat_ptr (&abs_output_section->children);
-
- for (j = 0; init[j].ptr; j++)
- {
-@@ -704,7 +701,7 @@
- image_base_statement = rv;
- }
- /* Restore the pointer. */
-- stat_ptr = save;
-+ pop_stat_ptr ();
-
- if (pep.FileAlignment > pep.SectionAlignment)
- {
-@@ -1372,40 +1369,37 @@
- sort_sections. */
-
- static bfd_boolean
--gld_${EMULATION_NAME}_place_orphan (asection *s)
-+gld_${EMULATION_NAME}_place_orphan (asection *s,
-+ const char *secname,
-+ int constraint)
- {
-- const char *secname;
-- const char *orig_secname;
-+ const char *orig_secname = secname;
- char *dollar = NULL;
- lang_output_section_statement_type *os;
- lang_statement_list_type add_child;
-
-- secname = bfd_get_section_name (s->owner, s);
--
- /* Look through the script to see where to place this section. */
-- orig_secname = secname;
- if (!link_info.relocatable
- && (dollar = strchr (secname, '$')) != NULL)
- {
-- size_t len = dollar - orig_secname;
-+ size_t len = dollar - secname;
- char *newname = xmalloc (len + 1);
-- memcpy (newname, orig_secname, len);
-+ memcpy (newname, secname, len);
- newname[len] = '\0';
- secname = newname;
- }
-
-- os = lang_output_section_find (secname);
--
- lang_list_init (&add_child);
-
-- if (os != NULL
-- && (os->bfd_section == NULL
-- || os->bfd_section->flags == 0
-+ if (constraint == 0
-+ && (os = lang_output_section_find (secname)) != NULL
-+ && os->bfd_section != NULL
-+ && (os->bfd_section->flags == 0
- || ((s->flags ^ os->bfd_section->flags)
- & (SEC_LOAD | SEC_ALLOC)) == 0))
- {
- /* We already have an output section statement with this
-- name, and its bfd section, if any, has compatible flags.
-+ name, and its bfd section has compatible flags.
- If the section already exists but does not have any flags set,
- then it has been created by the linker, probably as a result of
- a --section-start command line switch. */
-@@ -1482,21 +1476,10 @@
- ->output_section_statement);
- }
-
-- /* Choose a unique name for the section. This will be needed if the
-- same section name appears in the input file with different
-- loadable or allocatable characteristics. */
-- if (bfd_get_section_by_name (link_info.output_bfd, secname) != NULL)
-- {
-- static int count = 1;
-- secname = bfd_get_unique_section_name (link_info.output_bfd,
-- secname, &count);
-- if (secname == NULL)
-- einfo ("%F%P: place_orphan failed: %E\n");
-- }
--
- /* All sections in an executable must be aligned to a page boundary. */
- address = exp_unop (ALIGN_K, exp_nameop (NAME, "__section_alignment__"));
-- os = lang_insert_orphan (s, secname, after, place, address, &add_child);
-+ os = lang_insert_orphan (s, secname, constraint, after, place, address,
-+ &add_child);
- }
-
- {
-diff -Naur binutils-2.19.1.orig/ld/emultempl/spuelf.em binutils-2.19.1/ld/emultempl/spuelf.em
---- binutils-2.19.1.orig/ld/emultempl/spuelf.em 2008-08-02 09:25:44.000000000 -0700
-+++ binutils-2.19.1/ld/emultempl/spuelf.em 2009-03-02 05:34:03.000000000 -0800
-@@ -114,12 +114,7 @@
-
- os = lang_output_section_find (o != NULL ? o->name : output_name);
- if (os == NULL)
-- {
-- const char *save = s->name;
-- s->name = output_name;
-- gld${EMULATION_NAME}_place_orphan (s);
-- s->name = save;
-- }
-+ gld${EMULATION_NAME}_place_orphan (s, output_name, 0);
- else if (o != NULL && os->children.head != NULL)
- {
- lang_statement_list_type add;
-diff -Naur binutils-2.19.1.orig/ld/emultempl/xtensaelf.em binutils-2.19.1/ld/emultempl/xtensaelf.em
---- binutils-2.19.1.orig/ld/emultempl/xtensaelf.em 2008-02-14 19:35:53.000000000 -0800
-+++ binutils-2.19.1/ld/emultempl/xtensaelf.em 2009-03-02 05:56:19.000000000 -0800
-@@ -1,5 +1,5 @@
- # This shell script emits a C file. -*- C -*-
--# Copyright 2003, 2004, 2005, 2006, 2007, 2008
-+# Copyright 2003, 2004, 2005, 2006, 2007, 2008, 2009
- # Free Software Foundation, Inc.
- #
- # This file is part of the GNU Binutils.
-@@ -1951,20 +1951,17 @@
- lang_assignment_statement_type *assign_stmt;
- lang_statement_union_type *assign_union;
- lang_statement_list_type tmplist;
-- lang_statement_list_type *old_stat_ptr = stat_ptr;
-
- /* There is hidden state in "lang_add_assignment". It
- appends the new assignment statement to the stat_ptr
- list. Thus, we swap it before and after the call. */
-
-- tmplist.head = NULL;
-- tmplist.tail = &tmplist.head;
--
-- stat_ptr = &tmplist;
-+ lang_list_init (&tmplist);
-+ push_stat_ptr (&tmplist);
- /* Warning: side effect; statement appended to stat_ptr. */
- assign_stmt = lang_add_assignment (assign_op);
- assign_union = (lang_statement_union_type *) assign_stmt;
-- stat_ptr = old_stat_ptr;
-+ pop_stat_ptr ();
-
- assign_union->header.next = l;
- *(*stack_p)->iterloc.loc = assign_union;
-diff -Naur binutils-2.19.1.orig/ld/ldctor.c binutils-2.19.1/ld/ldctor.c
---- binutils-2.19.1.orig/ld/ldctor.c 2008-02-14 19:35:53.000000000 -0800
-+++ binutils-2.19.1/ld/ldctor.c 2009-03-02 05:56:19.000000000 -0800
-@@ -1,6 +1,7 @@
- /* ldctor.c -- constructor support routines
- Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
-- 2002, 2003, 2004, 2006, 2007, 2008 Free Software Foundation, Inc.
-+ 2002, 2003, 2004, 2006, 2007, 2008, 2009
-+ Free Software Foundation, Inc.
- By Steve Chamberlain <sac@cygnus.com>
-
- This file is part of the GNU Binutils.
-@@ -198,7 +199,6 @@
- ldctor_build_sets (void)
- {
- static bfd_boolean called;
-- lang_statement_list_type *old;
- bfd_boolean header_printed;
- struct set_info *p;
-
-@@ -244,10 +244,8 @@
- }
- }
-
-- old = stat_ptr;
-- stat_ptr = &constructor_list;
--
-- lang_list_init (stat_ptr);
-+ lang_list_init (&constructor_list);
-+ push_stat_ptr (&constructor_list);
-
- header_printed = FALSE;
- for (p = sets; p != NULL; p = p->next)
-@@ -372,5 +370,5 @@
- lang_add_data (size, exp_intop (0));
- }
-
-- stat_ptr = old;
-+ pop_stat_ptr ();
- }
-diff -Naur binutils-2.19.1.orig/ld/ldemul.c binutils-2.19.1/ld/ldemul.c
---- binutils-2.19.1.orig/ld/ldemul.c 2008-02-14 19:35:53.000000000 -0800
-+++ binutils-2.19.1/ld/ldemul.c 2009-03-02 05:34:02.000000000 -0800
-@@ -120,10 +120,10 @@
- }
-
- bfd_boolean
--ldemul_place_orphan (asection *s)
-+ldemul_place_orphan (asection *s, const char *name, int constraint)
- {
- if (ld_emulation->place_orphan)
-- return (*ld_emulation->place_orphan) (s);
-+ return (*ld_emulation->place_orphan) (s, name, constraint);
- return FALSE;
- }
-
-diff -Naur binutils-2.19.1.orig/ld/ldemul.h binutils-2.19.1/ld/ldemul.h
---- binutils-2.19.1.orig/ld/ldemul.h 2007-07-06 07:09:41.000000000 -0700
-+++ binutils-2.19.1/ld/ldemul.h 2009-03-02 05:34:02.000000000 -0800
-@@ -59,7 +59,7 @@
- extern void ldemul_create_output_section_statements
- (void);
- extern bfd_boolean ldemul_place_orphan
-- (asection *);
-+ (asection *, const char *, int);
- extern bfd_boolean ldemul_parse_args
- (int, char **);
- extern void ldemul_add_options
-@@ -152,7 +152,7 @@
- the default action should be taken. This field may be NULL, in
- which case the default action will always be taken. */
- bfd_boolean (*place_orphan)
-- (asection *);
-+ (asection *, const char *, int);
-
- /* Run after assigning parsing with the args, but before
- reading the script. Used to initialize symbols used in the script. */
-diff -Naur binutils-2.19.1.orig/ld/ldexp.c binutils-2.19.1/ld/ldexp.c
---- binutils-2.19.1.orig/ld/ldexp.c 2008-08-21 06:10:54.000000000 -0700
-+++ binutils-2.19.1/ld/ldexp.c 2009-03-02 05:29:32.000000000 -0800
-@@ -282,6 +282,7 @@
- static void
- fold_binary (etree_type *tree)
- {
-+ etree_value_type lhs;
- exp_fold_tree_1 (tree->binary.lhs);
-
- /* The SEGMENT_START operator is special because its first
-@@ -304,169 +305,167 @@
- expld.result.section = expld.section;
- break;
- }
-+ return;
- }
-- else if (expld.result.valid_p)
-- {
-- etree_value_type lhs = expld.result;
-
-- exp_fold_tree_1 (tree->binary.rhs);
-- if (expld.result.valid_p)
-- {
-- /* If the values are from different sections, or this is an
-- absolute expression, make both the source arguments
-- absolute. However, adding or subtracting an absolute
-- value from a relative value is meaningful, and is an
-- exception. */
-- if (expld.section != bfd_abs_section_ptr
-- && lhs.section == bfd_abs_section_ptr
-- && tree->type.node_code == '+')
-- {
-- /* Keep the section of the rhs term. */
-- expld.result.value = lhs.value + expld.result.value;
-- return;
-- }
-- else if (expld.section != bfd_abs_section_ptr
-- && expld.result.section == bfd_abs_section_ptr
-- && (tree->type.node_code == '+'
-- || tree->type.node_code == '-'))
-- {
-- /* Keep the section of the lhs term. */
-- expld.result.section = lhs.section;
-- }
-- else if (expld.result.section != lhs.section
-- || expld.section == bfd_abs_section_ptr)
-- {
-- make_abs ();
-- lhs.value += lhs.section->vma;
-- }
--
-- switch (tree->type.node_code)
-- {
-- case '%':
-- if (expld.result.value != 0)
-- expld.result.value = ((bfd_signed_vma) lhs.value
-- % (bfd_signed_vma) expld.result.value);
-- else if (expld.phase != lang_mark_phase_enum)
-- einfo (_("%F%S %% by zero\n"));
-- break;
-+ lhs = expld.result;
-+ exp_fold_tree_1 (tree->binary.rhs);
-+ expld.result.valid_p &= lhs.valid_p;
-
-- case '/':
-- if (expld.result.value != 0)
-- expld.result.value = ((bfd_signed_vma) lhs.value
-- / (bfd_signed_vma) expld.result.value);
-- else if (expld.phase != lang_mark_phase_enum)
-- einfo (_("%F%S / by zero\n"));
-- break;
-+ if (expld.result.valid_p)
-+ {
-+ /* If the values are from different sections, or this is an
-+ absolute expression, make both the source arguments
-+ absolute. However, adding or subtracting an absolute
-+ value from a relative value is meaningful, and is an
-+ exception. */
-+ if (expld.section != bfd_abs_section_ptr
-+ && lhs.section == bfd_abs_section_ptr
-+ && tree->type.node_code == '+')
-+ {
-+ /* Keep the section of the rhs term. */
-+ expld.result.value = lhs.value + expld.result.value;
-+ return;
-+ }
-+ else if (expld.section != bfd_abs_section_ptr
-+ && expld.result.section == bfd_abs_section_ptr
-+ && (tree->type.node_code == '+'
-+ || tree->type.node_code == '-'))
-+ {
-+ /* Keep the section of the lhs term. */
-+ expld.result.section = lhs.section;
-+ }
-+ else if (expld.result.section != lhs.section
-+ || expld.section == bfd_abs_section_ptr)
-+ {
-+ make_abs ();
-+ lhs.value += lhs.section->vma;
-+ }
-+
-+ switch (tree->type.node_code)
-+ {
-+ case '%':
-+ if (expld.result.value != 0)
-+ expld.result.value = ((bfd_signed_vma) lhs.value
-+ % (bfd_signed_vma) expld.result.value);
-+ else if (expld.phase != lang_mark_phase_enum)
-+ einfo (_("%F%S %% by zero\n"));
-+ break;
-+
-+ case '/':
-+ if (expld.result.value != 0)
-+ expld.result.value = ((bfd_signed_vma) lhs.value
-+ / (bfd_signed_vma) expld.result.value);
-+ else if (expld.phase != lang_mark_phase_enum)
-+ einfo (_("%F%S / by zero\n"));
-+ break;
-
- #define BOP(x, y) \
- case x: \
- expld.result.value = lhs.value y expld.result.value; \
- break;
-
-- BOP ('+', +);
-- BOP ('*', *);
-- BOP ('-', -);
-- BOP (LSHIFT, <<);
-- BOP (RSHIFT, >>);
-- BOP (EQ, ==);
-- BOP (NE, !=);
-- BOP ('<', <);
-- BOP ('>', >);
-- BOP (LE, <=);
-- BOP (GE, >=);
-- BOP ('&', &);
-- BOP ('^', ^);
-- BOP ('|', |);
-- BOP (ANDAND, &&);
-- BOP (OROR, ||);
--
-- case MAX_K:
-- if (lhs.value > expld.result.value)
-- expld.result.value = lhs.value;
-- break;
--
-- case MIN_K:
-- if (lhs.value < expld.result.value)
-- expld.result.value = lhs.value;
-- break;
--
-- case ALIGN_K:
-- expld.result.value = align_n (lhs.value, expld.result.value);
-- break;
--
-- case DATA_SEGMENT_ALIGN:
-- expld.dataseg.relro = exp_dataseg_relro_start;
-- if (expld.phase != lang_first_phase_enum
-- && expld.section == bfd_abs_section_ptr
-- && (expld.dataseg.phase == exp_dataseg_none
-- || expld.dataseg.phase == exp_dataseg_adjust
-- || expld.dataseg.phase == exp_dataseg_relro_adjust
-- || expld.phase == lang_final_phase_enum))
-+ BOP ('+', +);
-+ BOP ('*', *);
-+ BOP ('-', -);
-+ BOP (LSHIFT, <<);
-+ BOP (RSHIFT, >>);
-+ BOP (EQ, ==);
-+ BOP (NE, !=);
-+ BOP ('<', <);
-+ BOP ('>', >);
-+ BOP (LE, <=);
-+ BOP (GE, >=);
-+ BOP ('&', &);
-+ BOP ('^', ^);
-+ BOP ('|', |);
-+ BOP (ANDAND, &&);
-+ BOP (OROR, ||);
-+
-+ case MAX_K:
-+ if (lhs.value > expld.result.value)
-+ expld.result.value = lhs.value;
-+ break;
-+
-+ case MIN_K:
-+ if (lhs.value < expld.result.value)
-+ expld.result.value = lhs.value;
-+ break;
-+
-+ case ALIGN_K:
-+ expld.result.value = align_n (lhs.value, expld.result.value);
-+ break;
-+
-+ case DATA_SEGMENT_ALIGN:
-+ expld.dataseg.relro = exp_dataseg_relro_start;
-+ if (expld.phase != lang_first_phase_enum
-+ && expld.section == bfd_abs_section_ptr
-+ && (expld.dataseg.phase == exp_dataseg_none
-+ || expld.dataseg.phase == exp_dataseg_adjust
-+ || expld.dataseg.phase == exp_dataseg_relro_adjust
-+ || expld.phase == lang_final_phase_enum))
-+ {
-+ bfd_vma maxpage = lhs.value;
-+ bfd_vma commonpage = expld.result.value;
-+
-+ expld.result.value = align_n (expld.dot, maxpage);
-+ if (expld.dataseg.phase == exp_dataseg_relro_adjust)
-+ expld.result.value = expld.dataseg.base;
-+ else if (expld.dataseg.phase != exp_dataseg_adjust)
- {
-- bfd_vma maxpage = lhs.value;
-- bfd_vma commonpage = expld.result.value;
--
-- expld.result.value = align_n (expld.dot, maxpage);
-- if (expld.dataseg.phase == exp_dataseg_relro_adjust)
-- expld.result.value = expld.dataseg.base;
-- else if (expld.dataseg.phase != exp_dataseg_adjust)
-+ expld.result.value += expld.dot & (maxpage - 1);
-+ if (expld.phase == lang_allocating_phase_enum)
- {
-- expld.result.value += expld.dot & (maxpage - 1);
-- if (expld.phase == lang_allocating_phase_enum)
-- {
-- expld.dataseg.phase = exp_dataseg_align_seen;
-- expld.dataseg.min_base = expld.dot;
-- expld.dataseg.base = expld.result.value;
-- expld.dataseg.pagesize = commonpage;
-- expld.dataseg.maxpagesize = maxpage;
-- expld.dataseg.relro_end = 0;
-- }
-+ expld.dataseg.phase = exp_dataseg_align_seen;
-+ expld.dataseg.min_base = expld.dot;
-+ expld.dataseg.base = expld.result.value;
-+ expld.dataseg.pagesize = commonpage;
-+ expld.dataseg.maxpagesize = maxpage;
-+ expld.dataseg.relro_end = 0;
- }
-- else if (commonpage < maxpage)
-- expld.result.value += ((expld.dot + commonpage - 1)
-- & (maxpage - commonpage));
- }
-- else
-- expld.result.valid_p = FALSE;
-- break;
-+ else if (commonpage < maxpage)
-+ expld.result.value += ((expld.dot + commonpage - 1)
-+ & (maxpage - commonpage));
-+ }
-+ else
-+ expld.result.valid_p = FALSE;
-+ break;
-
-- case DATA_SEGMENT_RELRO_END:
-- expld.dataseg.relro = exp_dataseg_relro_end;
-- if (expld.phase != lang_first_phase_enum
-- && (expld.dataseg.phase == exp_dataseg_align_seen
-- || expld.dataseg.phase == exp_dataseg_adjust
-- || expld.dataseg.phase == exp_dataseg_relro_adjust
-- || expld.phase == lang_final_phase_enum))
-+ case DATA_SEGMENT_RELRO_END:
-+ expld.dataseg.relro = exp_dataseg_relro_end;
-+ if (expld.phase != lang_first_phase_enum
-+ && (expld.dataseg.phase == exp_dataseg_align_seen
-+ || expld.dataseg.phase == exp_dataseg_adjust
-+ || expld.dataseg.phase == exp_dataseg_relro_adjust
-+ || expld.phase == lang_final_phase_enum))
-+ {
-+ if (expld.dataseg.phase == exp_dataseg_align_seen
-+ || expld.dataseg.phase == exp_dataseg_relro_adjust)
-+ expld.dataseg.relro_end = lhs.value + expld.result.value;
-+
-+ if (expld.dataseg.phase == exp_dataseg_relro_adjust
-+ && (expld.dataseg.relro_end
-+ & (expld.dataseg.pagesize - 1)))
- {
-- if (expld.dataseg.phase == exp_dataseg_align_seen
-- || expld.dataseg.phase == exp_dataseg_relro_adjust)
-- expld.dataseg.relro_end = lhs.value + expld.result.value;
--
-- if (expld.dataseg.phase == exp_dataseg_relro_adjust
-- && (expld.dataseg.relro_end
-- & (expld.dataseg.pagesize - 1)))
-- {
-- expld.dataseg.relro_end += expld.dataseg.pagesize - 1;
-- expld.dataseg.relro_end &= ~(expld.dataseg.pagesize - 1);
-- expld.result.value = (expld.dataseg.relro_end
-- - expld.result.value);
-- }
-- else
-- expld.result.value = lhs.value;
--
-- if (expld.dataseg.phase == exp_dataseg_align_seen)
-- expld.dataseg.phase = exp_dataseg_relro_seen;
-+ expld.dataseg.relro_end += expld.dataseg.pagesize - 1;
-+ expld.dataseg.relro_end &= ~(expld.dataseg.pagesize - 1);
-+ expld.result.value = (expld.dataseg.relro_end
-+ - expld.result.value);
- }
- else
-- expld.result.valid_p = FALSE;
-- break;
-+ expld.result.value = lhs.value;
-
-- default:
-- FAIL ();
-+ if (expld.dataseg.phase == exp_dataseg_align_seen)
-+ expld.dataseg.phase = exp_dataseg_relro_seen;
- }
-+ else
-+ expld.result.valid_p = FALSE;
-+ break;
-+
-+ default:
-+ FAIL ();
- }
-- else
-- expld.result.valid_p = FALSE;
- }
- }
-
-diff -Naur binutils-2.19.1.orig/ld/ldlang.c binutils-2.19.1/ld/ldlang.c
---- binutils-2.19.1.orig/ld/ldlang.c 2008-09-06 21:02:30.000000000 -0700
-+++ binutils-2.19.1/ld/ldlang.c 2009-03-02 05:56:19.000000000 -0800
-@@ -1,6 +1,6 @@
- /* Linker command language support.
- Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-- 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
-+ 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
- Free Software Foundation, Inc.
-
- This file is part of the GNU Binutils.
-@@ -64,6 +64,8 @@
- static const char *output_target;
- static lang_statement_list_type statement_list;
- static struct bfd_hash_table lang_definedness_table;
-+static lang_statement_list_type *stat_save[10];
-+static lang_statement_list_type **stat_save_ptr = &stat_save[0];
-
- /* Forward declarations. */
- static void exp_init_os (etree_type *);
-@@ -193,7 +195,7 @@
- return match;
- }
-
--bfd_boolean
-+static bfd_boolean
- unique_section_p (const asection *sec)
- {
- struct unique_sections *unam;
-@@ -925,6 +927,23 @@
- list->tail = &list->head;
- }
-
-+void
-+push_stat_ptr (lang_statement_list_type *new_ptr)
-+{
-+ if (stat_save_ptr >= stat_save + sizeof (stat_save) / sizeof (stat_save[0]))
-+ abort ();
-+ *stat_save_ptr++ = stat_ptr;
-+ stat_ptr = new_ptr;
-+}
-+
-+void
-+pop_stat_ptr (void)
-+{
-+ if (stat_save_ptr <= stat_save)
-+ abort ();
-+ stat_ptr = *--stat_save_ptr;
-+}
-+
- /* Build a new statement node for the parse tree. */
-
- static lang_statement_union_type *
-@@ -1278,19 +1297,25 @@
- struct out_section_hash_entry *last_ent;
- unsigned long hash = entry->root.hash;
-
-- do
-- {
-- if (entry->s.output_section_statement.constraint >= 0
-- && (constraint == 0
-- || (constraint == entry->s.output_section_statement.constraint
-- && constraint != SPECIAL)))
-- return &entry->s.output_section_statement;
-- last_ent = entry;
-- entry = (struct out_section_hash_entry *) entry->root.next;
-- }
-- while (entry != NULL
-- && entry->root.hash == hash
-- && strcmp (name, entry->s.output_section_statement.name) == 0);
-+ if (create && constraint == SPECIAL)
-+ /* Not traversing to the end reverses the order of the second
-+ and subsequent SPECIAL sections in the hash table chain,
-+ but that shouldn't matter. */
-+ last_ent = entry;
-+ else
-+ do
-+ {
-+ if (entry->s.output_section_statement.constraint >= 0
-+ && (constraint == 0
-+ || (constraint
-+ == entry->s.output_section_statement.constraint)))
-+ return &entry->s.output_section_statement;
-+ last_ent = entry;
-+ entry = (struct out_section_hash_entry *) entry->root.next;
-+ }
-+ while (entry != NULL
-+ && entry->root.hash == hash
-+ && strcmp (name, entry->s.output_section_statement.name) == 0);
-
- if (!create)
- return NULL;
-@@ -1556,28 +1581,24 @@
- lang_output_section_statement_type *
- lang_insert_orphan (asection *s,
- const char *secname,
-+ int constraint,
- lang_output_section_statement_type *after,
- struct orphan_save *place,
- etree_type *address,
- lang_statement_list_type *add_child)
- {
-- lang_statement_list_type *old;
- lang_statement_list_type add;
- const char *ps;
- lang_output_section_statement_type *os;
- lang_output_section_statement_type **os_tail;
-
-- /* Start building a list of statements for this section.
-- First save the current statement pointer. */
-- old = stat_ptr;
--
- /* If we have found an appropriate place for the output section
- statements for this orphan, add them to our own private list,
- inserting them later into the global statement list. */
- if (after != NULL)
- {
-- stat_ptr = &add;
-- lang_list_init (stat_ptr);
-+ lang_list_init (&add);
-+ push_stat_ptr (&add);
- }
-
- ps = NULL;
-@@ -1611,7 +1632,7 @@
- os_tail = ((lang_output_section_statement_type **)
- lang_output_section_statement.tail);
- os = lang_enter_output_section_statement (secname, address, 0, NULL, NULL,
-- NULL, 0);
-+ NULL, constraint);
-
- if (add_child == NULL)
- add_child = &os->children;
-@@ -1623,11 +1644,6 @@
- {
- char *symname;
-
-- /* lang_leave_ouput_section_statement resets stat_ptr.
-- Put stat_ptr back where we want it. */
-- if (after != NULL)
-- stat_ptr = &add;
--
- symname = (char *) xmalloc (ps - secname + sizeof "__stop_" + 1);
- symname[0] = bfd_get_symbol_leading_char (link_info.output_bfd);
- sprintf (symname + (symname[0] != 0), "__stop_%s", secname);
-@@ -1638,7 +1654,7 @@
-
- /* Restore the global list pointer. */
- if (after != NULL)
-- stat_ptr = old;
-+ pop_stat_ptr ();
-
- if (after != NULL && os->bfd_section != NULL)
- {
-@@ -1724,8 +1740,8 @@
-
- /* Fix the global list pointer if we happened to tack our
- new list at the tail. */
-- if (*old->tail == add.head)
-- old->tail = add.tail;
-+ if (*stat_ptr->tail == add.head)
-+ stat_ptr->tail = add.tail;
-
- /* Save the end of this list. */
- place->stmt = add.tail;
-@@ -1914,10 +1930,11 @@
- if (strcmp (s->name, DISCARD_SECTION_NAME) == 0)
- einfo (_("%P%F: Illegal use of `%s' section\n"), DISCARD_SECTION_NAME);
-
-- s->bfd_section = bfd_get_section_by_name (link_info.output_bfd, s->name);
-+ if (s->constraint != SPECIAL)
-+ s->bfd_section = bfd_get_section_by_name (link_info.output_bfd, s->name);
- if (s->bfd_section == NULL)
-- s->bfd_section = bfd_make_section_with_flags (link_info.output_bfd,
-- s->name, flags);
-+ s->bfd_section = bfd_make_section_anyway_with_flags (link_info.output_bfd,
-+ s->name, flags);
- if (s->bfd_section == NULL)
- {
- einfo (_("%P%F: output format %s cannot represent section called %s\n"),
-@@ -2455,8 +2472,6 @@
- && ! bfd_check_format_matches (entry->the_bfd, bfd_object, &matching))
- {
- bfd_error_type err;
-- lang_statement_list_type *hold;
-- bfd_boolean bad_load = TRUE;
- bfd_boolean save_ldlang_sysrooted_script;
- bfd_boolean save_as_needed, save_add_needed;
-
-@@ -2479,8 +2494,6 @@
- else if (err != bfd_error_file_not_recognized
- || place == NULL)
- einfo (_("%F%B: file not recognized: %E\n"), entry->the_bfd);
-- else
-- bad_load = FALSE;
-
- bfd_close (entry->the_bfd);
- entry->the_bfd = NULL;
-@@ -2488,8 +2501,7 @@
- /* Try to interpret the file as a linker script. */
- ldfile_open_command_file (entry->filename);
-
-- hold = stat_ptr;
-- stat_ptr = place;
-+ push_stat_ptr (place);
- save_ldlang_sysrooted_script = ldlang_sysrooted_script;
- ldlang_sysrooted_script = entry->sysrooted;
- save_as_needed = as_needed;
-@@ -2508,9 +2520,9 @@
- ldlang_sysrooted_script = save_ldlang_sysrooted_script;
- as_needed = save_as_needed;
- add_needed = save_add_needed;
-- stat_ptr = hold;
-+ pop_stat_ptr ();
-
-- return ! bad_load;
-+ return TRUE;
- }
-
- if (ldemul_recognized_file (entry))
-@@ -2982,6 +2994,7 @@
- case lang_input_statement_enum:
- if (s->input_statement.real)
- {
-+ lang_statement_union_type **os_tail;
- lang_statement_list_type add;
-
- s->input_statement.target = current_target;
-@@ -2997,6 +3010,7 @@
- bfd_archive))
- s->input_statement.loaded = FALSE;
-
-+ os_tail = lang_output_section_statement.tail;
- lang_list_init (&add);
-
- if (! load_symbols (&s->input_statement, &add))
-@@ -3004,8 +3018,25 @@
-
- if (add.head != NULL)
- {
-- *add.tail = s->header.next;
-- s->header.next = add.head;
-+ /* If this was a script with output sections then
-+ tack any added statements on to the end of the
-+ list. This avoids having to reorder the output
-+ section statement list. Very likely the user
-+ forgot -T, and whatever we do here will not meet
-+ naive user expectations. */
-+ if (os_tail != lang_output_section_statement.tail)
-+ {
-+ einfo (_("%P: warning: %s contains output sections;"
-+ " did you forget -T?\n"),
-+ s->input_statement.filename);
-+ *stat_ptr->tail = add.head;
-+ stat_ptr->tail = add.tail;
-+ }
-+ else
-+ {
-+ *add.tail = s->header.next;
-+ s->header.next = add.head;
-+ }
- }
- }
- break;
-@@ -5652,14 +5683,22 @@
- default_common_section);
- }
- }
-- else if (ldemul_place_orphan (s))
-- ;
- else
- {
-- lang_output_section_statement_type *os;
-+ const char *name = s->name;
-+ int constraint = 0;
-
-- os = lang_output_section_statement_lookup (s->name, 0, TRUE);
-- lang_add_section (&os->children, s, os);
-+ if (config.unique_orphan_sections || unique_section_p (s))
-+ constraint = SPECIAL;
-+
-+ if (!ldemul_place_orphan (s, name, constraint))
-+ {
-+ lang_output_section_statement_type *os;
-+ os = lang_output_section_statement_lookup (name,
-+ constraint,
-+ TRUE);
-+ lang_add_section (&os->children, s, os);
-+ }
- }
- }
- }
-@@ -5821,7 +5860,7 @@
- os->block_value = 1;
-
- /* Make next things chain into subchain of this. */
-- stat_ptr = &os->children;
-+ push_stat_ptr (&os->children);
-
- os->subsection_alignment =
- topower (exp_get_value_int (subalign, -1, "subsection alignment"));
-@@ -6430,7 +6469,7 @@
- current_section->addr_tree != NULL);
- current_section->fill = fill;
- current_section->phdrs = phdrs;
-- stat_ptr = &statement_list;
-+ pop_stat_ptr ();
- }
-
- /* Create an absolute symbol with the given name with the value of the
-@@ -6547,7 +6586,7 @@
-
- g = new_stat (lang_group_statement, stat_ptr);
- lang_list_init (&g->children);
-- stat_ptr = &g->children;
-+ push_stat_ptr (&g->children);
- }
-
- /* Leave a group. This just resets stat_ptr to start writing to the
-@@ -6558,7 +6597,7 @@
- void
- lang_leave_group (void)
- {
-- stat_ptr = &statement_list;
-+ pop_stat_ptr ();
- }
-
- /* Add a new program header. This is called for each entry in a PHDRS
-diff -Naur binutils-2.19.1.orig/ld/ldlang.h binutils-2.19.1/ld/ldlang.h
---- binutils-2.19.1.orig/ld/ldlang.h 2008-09-06 21:02:30.000000000 -0700
-+++ binutils-2.19.1/ld/ldlang.h 2009-03-02 05:56:19.000000000 -0800
-@@ -1,6 +1,6 @@
- /* ldlang.h - linker command language support
- Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-- 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
-+ 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
- Free Software Foundation, Inc.
-
- This file is part of the GNU Binutils.
-@@ -536,7 +536,7 @@
- (const asection *, lang_output_section_statement_type **,
- lang_match_sec_type_func);
- extern lang_output_section_statement_type *lang_insert_orphan
-- (asection *, const char *, lang_output_section_statement_type *,
-+ (asection *, const char *, int, lang_output_section_statement_type *,
- struct orphan_save *, etree_type *, lang_statement_list_type *);
- extern lang_input_statement_type *lang_add_input_file
- (const char *, lang_input_file_enum_type, const char *);
-@@ -550,6 +550,10 @@
- (const char *, const char *, const char *, int);
- extern void lang_list_init
- (lang_statement_list_type *);
-+extern void push_stat_ptr
-+ (lang_statement_list_type *);
-+extern void pop_stat_ptr
-+ (void);
- extern void lang_add_data
- (int type, union etree_union *);
- extern void lang_add_reloc
-@@ -604,8 +608,6 @@
- extern void lang_append_dynamic_list (struct bfd_elf_version_expr *);
- extern void lang_append_dynamic_list_cpp_typeinfo (void);
- extern void lang_append_dynamic_list_cpp_new (void);
--bfd_boolean unique_section_p
-- (const asection *);
- extern void lang_add_unique
- (const char *);
- extern const char *lang_get_output_target
-diff -Naur binutils-2.19.1.orig/ld/testsuite/ChangeLog binutils-2.19.1/ld/testsuite/ChangeLog
---- binutils-2.19.1.orig/ld/testsuite/ChangeLog 2009-01-14 01:04:14.000000000 -0800
-+++ binutils-2.19.1/ld/testsuite/ChangeLog 2009-03-02 05:53:31.000000000 -0800
-@@ -1,3 +1,26 @@
-+2009-03-02 Alan Modra <amodra@bigpond.net.au>
-+
-+ 2009-02-01 Jan Kratochvil <jan.kratochvil@redhat.com>
-+ * ld-elf/eh-group2.s: New `.cfi_lsda' referencing `.gcc_except_table'.
-+ * ld-elf/eh-group.exp: New test and conditional defininiton of `ELF64'.
-+
-+ 2009-01-26 Nathan Sidwell <nathan@codesourcery.com>
-+ * ld-powerpc/powerpc.exp: Add vxworks relax testcase.
-+ * ld-powerpc/vxworks-relax.s, ld-powerpc/vxworks-relax.rd: New.
-+ * ld-powerpc/vxworks1.ld: Add .pad and .far input sections.
-+ * ld-powerpc/vxworks1.rd: Correct regexp for undefined symbols.
-+
-+ 2009-01-11 Jan Kratochvil <jan.kratochvil@redhat.com>
-+ * ld-elf/linkoncerdiff.d, ld-elf/linkoncerdiff1.s,
-+ ld-elf/linkoncerdiff2.s: New.
-+
-+ 2008-10-10 Nathan Froyd <froydnj@codesourcery.com>
-+ * ld-powerpc/attr-gnu-12-1.s: New file.
-+ * ld-powerpc/attr-gnu-12-2.s: New file.
-+ * ld-powerpc/attr-gnu-12-11.d: New file.
-+ * ld-powerpc/attr-gnu-12-21.d: New file.
-+ * ld-powerpc/powerpc.exp: Run new dump tests.
-+
- 2009-01-14 Joseph Myers <joseph@codesourcery.com>
-
- * ld-arm/thumb2-bl-undefweak.d, ld-arm/thumb2-bl-undefweak.s: New.
-diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-elf/eh-group2.s binutils-2.19.1/ld/testsuite/ld-elf/eh-group2.s
---- binutils-2.19.1.orig/ld/testsuite/ld-elf/eh-group2.s 2008-10-02 03:10:26.000000000 -0700
-+++ binutils-2.19.1/ld/testsuite/ld-elf/eh-group2.s 2009-03-02 05:53:31.000000000 -0800
-@@ -1,4 +1,15 @@
- .section sect, "axG", %progbits, sectgroup, comdat
- .cfi_startproc
-+# Test intention is that LSDA must be provided by the discarded FDE.
-+# DW_EH_PE_udata8 = 4
-+# DW_EH_PE_udata4 = 3
-+ .ifdef ELF64
-+ .cfi_lsda 4, lsda
-+ .else
-+ .cfi_lsda 3, lsda
-+ .endif
- .skip 16
- .cfi_endproc
-+
-+ .section .gcc_except_table, "a", %progbits
-+lsda:
-diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-elf/eh-group.exp binutils-2.19.1/ld/testsuite/ld-elf/eh-group.exp
---- binutils-2.19.1.orig/ld/testsuite/ld-elf/eh-group.exp 2008-10-02 03:10:26.000000000 -0700
-+++ binutils-2.19.1/ld/testsuite/ld-elf/eh-group.exp 2009-03-02 05:53:31.000000000 -0800
-@@ -35,12 +35,28 @@
- return
- }
-
--set build_tests_ld {
-- {"Build eh-group1.o"
-- "-r" ""
-- {eh-group1.s eh-group2.s} {} "eh-group.o"}
-+# alpha-linux-gnu does not support 64-bit relocations:
-+# relocation truncated to fit: REFLONG against `.gcc_except_table'
-+# arm-eabi does not support 64-bit relocations:
-+# bad relocation fixup type (1)
-+set testname "Guess the target size from eh-group1size.o"
-+if [ld_assemble $as "$srcdir/$subdir/eh-group1.s" "tmpdir/eh-group1size.o"] {
-+ pass $testname
-+} else {
-+ fail $testname
- }
-
-+set as_options ""
-+if [is_elf64 "tmpdir/eh-group1size.o"] {
-+ set as_options "$as_options --defsym ELF64=1"
-+}
-+
-+set build_tests_ld [list \
-+ [list "Build eh-group1.o" \
-+ "-r" "$as_options" \
-+ {eh-group1.s eh-group2.s} {} "eh-group.o"] \
-+]
-+
- run_ld_link_tests $build_tests_ld
-
- set testname "Link eh-group.o to eh-group"
-diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-elf/linkoncerdiff1.s binutils-2.19.1/ld/testsuite/ld-elf/linkoncerdiff1.s
---- binutils-2.19.1.orig/ld/testsuite/ld-elf/linkoncerdiff1.s 1969-12-31 16:00:00.000000000 -0800
-+++ binutils-2.19.1/ld/testsuite/ld-elf/linkoncerdiff1.s 2009-03-02 05:48:42.000000000 -0800
-@@ -0,0 +1,7 @@
-+ .section .gnu.linkonce.t.foo, "a", %progbits
-+ .globl symfoo
-+symfoo:
-+
-+ .section .gnu.linkonce.t.bar, "a", %progbits
-+ .globl symbar
-+symbar:
-diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-elf/linkoncerdiff2.s binutils-2.19.1/ld/testsuite/ld-elf/linkoncerdiff2.s
---- binutils-2.19.1.orig/ld/testsuite/ld-elf/linkoncerdiff2.s 1969-12-31 16:00:00.000000000 -0800
-+++ binutils-2.19.1/ld/testsuite/ld-elf/linkoncerdiff2.s 2009-03-02 05:48:42.000000000 -0800
-@@ -0,0 +1,22 @@
-+ .section .gnu.linkonce.t.foo, "a", %progbits
-+1:
-+ .globl symfoo
-+symfoo:
-+ .long 0
-+
-+ .section .gnu.linkonce.t.bar, "a", %progbits
-+2:
-+ .globl symbar
-+symbar:
-+ .long 0
-+
-+ .section .gnu.linkonce.r.foo, "a", %progbits
-+ .long 1b
-+ .long symfoo
-+/* ld currently incorrectly silently discards this relocation. Just such
-+ relocations are never produced by g++-3.4 so this suppressed error message
-+ is not a problem:
-+ #error: `.gnu.linkonce.t.bar' referenced in section `.gnu.linkonce.r.foo' of tmpdir/dump1.o: defined in discarded section `.gnu.linkonce.t.bar' of tmpdir/dump1.o
-+ */
-+ .long 2b
-+ .long symbar
-diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-elf/linkoncerdiff.d binutils-2.19.1/ld/testsuite/ld-elf/linkoncerdiff.d
---- binutils-2.19.1.orig/ld/testsuite/ld-elf/linkoncerdiff.d 1969-12-31 16:00:00.000000000 -0800
-+++ binutils-2.19.1/ld/testsuite/ld-elf/linkoncerdiff.d 2009-03-02 05:48:42.000000000 -0800
-@@ -0,0 +1,6 @@
-+#source: linkoncerdiff1.s
-+#source: linkoncerdiff2.s
-+#ld: -r
-+#readelf: -r
-+There are no relocations in this file.
-+#pass
-diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/attr-gnu-12-11.d binutils-2.19.1/ld/testsuite/ld-powerpc/attr-gnu-12-11.d
---- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/attr-gnu-12-11.d 1969-12-31 16:00:00.000000000 -0800
-+++ binutils-2.19.1/ld/testsuite/ld-powerpc/attr-gnu-12-11.d 2009-03-02 05:37:44.000000000 -0800
-@@ -0,0 +1,10 @@
-+#source: attr-gnu-12-1.s
-+#source: attr-gnu-12-1.s
-+#as: -a32
-+#ld: -r -melf32ppc
-+#readelf: -A
-+#target: powerpc*-*-*
-+
-+Attribute Section: gnu
-+File Attributes
-+ Tag_GNU_Power_ABI_Struct_Return: r3/r4
-diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/attr-gnu-12-1.s binutils-2.19.1/ld/testsuite/ld-powerpc/attr-gnu-12-1.s
---- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/attr-gnu-12-1.s 1969-12-31 16:00:00.000000000 -0800
-+++ binutils-2.19.1/ld/testsuite/ld-powerpc/attr-gnu-12-1.s 2009-03-02 05:37:44.000000000 -0800
-@@ -0,0 +1 @@
-+.gnu_attribute 12,1
-diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/attr-gnu-12-21.d binutils-2.19.1/ld/testsuite/ld-powerpc/attr-gnu-12-21.d
---- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/attr-gnu-12-21.d 1969-12-31 16:00:00.000000000 -0800
-+++ binutils-2.19.1/ld/testsuite/ld-powerpc/attr-gnu-12-21.d 2009-03-02 05:37:44.000000000 -0800
-@@ -0,0 +1,6 @@
-+#source: attr-gnu-12-2.s
-+#source: attr-gnu-12-1.s
-+#as: -a32
-+#ld: -r -melf32ppc
-+#warning: Warning: .* uses r3/r4 for small structure returns, .* uses memory
-+#target: powerpc*-*-*
-diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/attr-gnu-12-2.s binutils-2.19.1/ld/testsuite/ld-powerpc/attr-gnu-12-2.s
---- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/attr-gnu-12-2.s 1969-12-31 16:00:00.000000000 -0800
-+++ binutils-2.19.1/ld/testsuite/ld-powerpc/attr-gnu-12-2.s 2009-03-02 05:37:44.000000000 -0800
-@@ -0,0 +1 @@
-+.gnu_attribute 12,2
-diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/powerpc.exp binutils-2.19.1/ld/testsuite/ld-powerpc/powerpc.exp
---- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/powerpc.exp 2008-07-26 06:10:48.000000000 -0700
-+++ binutils-2.19.1/ld/testsuite/ld-powerpc/powerpc.exp 2009-03-02 05:52:34.000000000 -0800
-@@ -49,6 +49,11 @@
- "-mregnames" {vxworks2.s}
- {{readelf --segments vxworks2-static.sd}}
- "vxworks2"}
-+ {"VxWorks relax test"
-+ "-Tvxworks1.ld --relax -q"
-+ "-mregnames" {vxworks-relax.s}
-+ {{readelf --relocs vxworks-relax.rd}}
-+ "vxworks-relax"}
- }
- run_ld_link_tests $ppcvxtests
- run_dump_test "vxworks1-static"
-@@ -177,3 +182,6 @@
- run_dump_test "attr-gnu-8-11"
- run_dump_test "attr-gnu-8-23"
- run_dump_test "attr-gnu-8-31"
-+
-+run_dump_test "attr-gnu-12-11"
-+run_dump_test "attr-gnu-12-21"
-diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/vxworks1.ld binutils-2.19.1/ld/testsuite/ld-powerpc/vxworks1.ld
---- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/vxworks1.ld 2007-05-15 05:22:34.000000000 -0700
-+++ binutils-2.19.1/ld/testsuite/ld-powerpc/vxworks1.ld 2009-03-02 05:52:34.000000000 -0800
-@@ -14,7 +14,7 @@
- .plt : { *(.plt) }
-
- . = ALIGN (0x400);
-- .text : { *(.text) }
-+ .text : { *(.text) *(.pad) *(.far) }
-
- . = ALIGN (0x10000);
- .dynamic : { *(.dynamic) }
-diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/vxworks1.rd binutils-2.19.1/ld/testsuite/ld-powerpc/vxworks1.rd
---- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/vxworks1.rd 2006-03-02 07:16:27.000000000 -0800
-+++ binutils-2.19.1/ld/testsuite/ld-powerpc/vxworks1.rd 2009-03-02 05:52:34.000000000 -0800
-@@ -1,8 +1,8 @@
-
- Relocation section '\.rela\.plt' at offset .* contains 2 entries:
- Offset Info Type Sym\.Value Sym\. Name \+ Addend
--0009040c .*15 R_PPC_JMP_SLOT 00080820 sglobal \+ 0
--00090410 .*15 R_PPC_JMP_SLOT 00080840 foo \+ 0
-+0009040c .*15 R_PPC_JMP_SLOT 00000000 sglobal \+ 0
-+00090410 .*15 R_PPC_JMP_SLOT 00000000 foo \+ 0
-
- Relocation section '\.rela\.text' at offset .* contains 3 entries:
- Offset Info Type Sym\.Value Sym\. Name \+ Addend
-diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/vxworks-relax.rd binutils-2.19.1/ld/testsuite/ld-powerpc/vxworks-relax.rd
---- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/vxworks-relax.rd 1969-12-31 16:00:00.000000000 -0800
-+++ binutils-2.19.1/ld/testsuite/ld-powerpc/vxworks-relax.rd 2009-03-02 05:52:34.000000000 -0800
-@@ -0,0 +1,9 @@
-+
-+Relocation section '.rela.text' at offset 0x4010150 contains 6 entries:
-+ Offset Info Type Sym.Value Sym. Name \+ Addend
-+00080012 00000106 R_PPC_ADDR16_HA 00080000 .text \+ 4000020
-+00080016 00000104 R_PPC_ADDR16_LO 00080000 .text \+ 4000020
-+00080006 00000106 R_PPC_ADDR16_HA 00080000 .text \+ 4000020
-+0008000a 00000104 R_PPC_ADDR16_LO 00080000 .text \+ 4000020
-+0408002a 00000306 R_PPC_ADDR16_HA 00080000 _start \+ 0
-+0408002e 00000304 R_PPC_ADDR16_LO 00080000 _start \+ 0
-diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/vxworks-relax.s binutils-2.19.1/ld/testsuite/ld-powerpc/vxworks-relax.s
---- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/vxworks-relax.s 1969-12-31 16:00:00.000000000 -0800
-+++ binutils-2.19.1/ld/testsuite/ld-powerpc/vxworks-relax.s 2009-03-02 05:52:34.000000000 -0800
-@@ -0,0 +1,13 @@
-+ .globl _start
-+_start:
-+ bl elsewhere
-+ lis 9,elsewhere@ha
-+ la 0,elsewhere@l(9)
-+
-+
-+ .section .far,"ax",@progbits
-+elsewhere:
-+ bl _start
-+
-+ .section .pad
-+ .space 0x4000000
-diff -Naur binutils-2.19.1.orig/opcodes/ChangeLog binutils-2.19.1/opcodes/ChangeLog
---- binutils-2.19.1.orig/opcodes/ChangeLog 2008-12-23 05:54:52.000000000 -0800
-+++ binutils-2.19.1/opcodes/ChangeLog 2009-03-03 17:08:22.000000000 -0800
-@@ -1,3 +1,93 @@
-+2009-03-03 Peter Bergner <bergner@vnet.ibm.com>
-+
-+ * ppc-opc.c (powerpc_opcodes): Reorder the opcode table so that
-+ instructions from newer processors are listed before older ones.
-+
-+2009-03-02 Alan Modra <amodra@bigpond.net.au>
-+
-+ 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
-+ * ppc-dis.c (powerpc_init_dialect): Extend -Mpower7 to disassemble
-+ the power7 and the isel instructions.
-+ * ppc-opc.c (insert_xc6, extract_xc6): New static functions.
-+ (insert_dm, extract_dm): Likewise.
-+ (XB6): Update comment to include XX2 form.
-+ (WC, XC6, SHW, DMEX, UIM, XX2, XX3RC, XX4, XX2_MASK, XX2UIM_MASK,
-+ XX2BF_MASK, XX3BF_MASK, XX3SHW_MASK, XX4_MASK, XWC_MASK, POWER7): New.
-+ (RemoveXX3DM): Delete.
-+ (powerpc_opcodes): <"lfdp", "lfdpx", "mcrxr", "mftb", "mffgpr",
-+ "mftgpr">: Deprecate for POWER7.
-+ <"fres", "fres.", "frsqrtes", "frsqrtes.", "fre", "fre.", "frsqrte",
-+ "frsqrte.">: Deprecate the three operand form and enable the two
-+ operand form for POWER7 and later.
-+ <"wait">: Extend to accept optional parameter. Enable for POWER7.
-+ <"waitsrv", "waitimpl">: Add extended opcodes.
-+ <"ldbrx", "stdbrx">: Enable for POWER7.
-+ <"cdtbcd", "cbcdtd", "addg6s">: Add POWER6 opcodes.
-+ <"bpermd", "dcbtstt", "dcbtt", "dcffix.", "dcffix", "divde.", "divde",
-+ "divdeo.", "divdeo", "divdeu.", "divdeu", "divdeuo.", "divdeuo",
-+ "divwe.", "divwe", "divweo.", "divweo", "divweu.", "divweu", "divweuo.",
-+ "divweuo", "fcfids.", "fcfids", "fcfidu.", "fcfidu", "fcfidus.",
-+ "fcfidus", "fctidu.", "fctidu", "fctiduz.", "fctiduz", "fctiwu.",
-+ "fctiwu", "fctiwuz.", "fctiwuz", "ftdiv", "ftsqrt", "lbarx", "lfiwzx",
-+ "lharx", "popcntd", "popcntw", "stbcx.", "sthcx.">: Add POWER7 opcodes.
-+ <"lxsdux", "lxsdx", "lxvdsx", "lxvw4ux", "lxvw4x", "stxsdux", "stxsdx",
-+ "stxvw4ux", "stxvw4x", "xsabsdp", "xsadddp", "xscmpodp", "xscmpudp",
-+ "xscpsgndp", "xscvdpsp", "xscvdpsxds", "xscvdpsxws", "xscvdpuxds",
-+ "xscvdpuxws", "xscvspdp", "xscvsxddp", "xscvuxddp", "xsdivdp",
-+ "xsmaddadp", "xsmaddmdp", "xsmaxdp", "xsmindp", "xsmsubadp",
-+ "xsmsubmdp", "xsmuldp", "xsnabsdp", "xsnegdp", "xsnmaddadp",
-+ "xsnmaddmdp", "xsnmsubadp", "xsnmsubmdp", "xsrdpi", "xsrdpic",
-+ "xsrdpim", "xsrdpip", "xsrdpiz", "xsredp", "xsrsqrtedp", "xssqrtdp",
-+ "xssubdp", "xstdivdp", "xstsqrtdp", "xvabsdp", "xvabssp", "xvadddp",
-+ "xvaddsp", "xvcmpeqdp.", "xvcmpeqdp", "xvcmpeqsp.", "xvcmpeqsp",
-+ "xvcmpgedp.", "xvcmpgedp", "xvcmpgesp.", "xvcmpgesp", "xvcmpgtdp.",
-+ "xvcmpgtdp", "xvcmpgtsp.", "xvcmpgtsp", "xvcpsgnsp", "xvcvdpsp",
-+ "xvcvdpsxds", "xvcvdpsxws", "xvcvdpuxds", "xvcvdpuxws", "xvcvspdp",
-+ "xvcvspsxds", "xvcvspsxws", "xvcvspuxds", "xvcvspuxws", "xvcvsxddp",
-+ "xvcvsxdsp", "xvcvsxwdp", "xvcvsxwsp", "xvcvuxddp", "xvcvuxdsp",
-+ "xvcvuxwdp", "xvcvuxwsp", "xvdivdp", "xvdivsp", "xvmaddadp",
-+ "xvmaddasp", "xvmaddmdp", "xvmaddmsp", "xvmaxdp", "xvmaxsp",
-+ "xvmindp", "xvminsp", "xvmovsp", "xvmsubadp", "xvmsubasp", "xvmsubmdp",
-+ "xvmsubmsp", "xvmuldp", "xvmulsp", "xvnabsdp", "xvnabssp", "xvnegdp",
-+ "xvnegsp", "xvnmaddadp", "xvnmaddasp", "xvnmaddmdp", "xvnmaddmsp",
-+ "xvnmsubadp", "xvnmsubasp", "xvnmsubmdp", "xvnmsubmsp", "xvrdpi",
-+ "xvrdpic", "xvrdpim", "xvrdpip", "xvrdpiz", "xvredp", "xvresp",
-+ "xvrspi", "xvrspic", "xvrspim", "xvrspip", "xvrspiz", "xvrsqrtedp",
-+ "xvrsqrtesp", "xvsqrtdp", "xvsqrtsp", "xvsubdp", "xvsubsp", "xvtdivdp",
-+ "xvtdivsp", "xvtsqrtdp", "xvtsqrtsp", "xxland", "xxlandc", "xxlnor",
-+ "xxlor", "xxlxor", "xxmrghw", "xxmrglw", "xxsel", "xxsldwi", "xxspltd",
-+ "xxspltw", "xxswapd">: Add VSX opcodes.
-+
-+ 2009-02-19 Peter Bergner <bergner@vnet.ibm.com>
-+ * ppc-opc.c (powerpc_opcodes) <"lfdepx", "stfdepx">: Fix the first
-+ operand to be a float point register (FRT/FRS).
-+
-+ 2009-02-05 Peter Bergner <bergner@vnet.ibm.com>
-+ * ppc-opc.c: Update copyright year.
-+ (powerpc_opcodes) <"dcbt", "dcbtst">: Deprecate the Embedded operand
-+ ordering for POWER4 and later and use the correct Server ordering.
-+
-+ 2009-01-14 Peter Bergner <bergner@vnet.ibm.com>
-+ * ppc-dis.c (print_insn_powerpc): Skip insn if it is deprecated.
-+ * ppc-opc.c (powerpc_opcodes) <mtfsf, mtfsf.>: Deprecate the two
-+ operand form and enable the four operand form for POWER6 and later.
-+ <mtfsfi, mtfsfi.>: Deprecate the two operand form and enable the
-+ three operand form for POWER6 and later.
-+
-+ 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
-+ * ppc-opc.c (PPCNONE): Define.
-+ (NOPOWER4): Delete.
-+ (powerpc_opcodes): Initialize the new "deprecated" field.
-+
-+ 2008-12-04 Ben Elliston <bje@au.ibm.com>
-+ * ppc-dis.c (powerpc_init_dialect): Do not set PPC_OPCODE_BOOKE
-+ for -Mbooke.
-+ (print_ppc_disassembler_options): Update usage.
-+ * ppc-opc.c (DE, DES, DEO, DE_MASK): Remove.
-+ (BOOKE64): Remove.
-+ (PPCCHLK64): Likewise.
-+ (powerpc_opcodes): Remove all BOOKE64 instructions.
-+
- 2008-11-27 Alan Modra <amodra@bigpond.net.au>
-
- * ppc-opc.c (extract_sprg): Correct operand range check.
-diff -Naur binutils-2.19.1.orig/opcodes/ppc-dis.c binutils-2.19.1/opcodes/ppc-dis.c
---- binutils-2.19.1.orig/opcodes/ppc-dis.c 2008-08-01 21:38:51.000000000 -0700
-+++ binutils-2.19.1/opcodes/ppc-dis.c 2009-03-02 05:59:36.000000000 -0800
-@@ -63,7 +63,7 @@
- dialect |= PPC_OPCODE_PPCPS;
- else if (info->disassembler_options
- && strstr (info->disassembler_options, "booke") != NULL)
-- dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
-+ dialect |= PPC_OPCODE_BOOKE;
- else if ((info->mach == bfd_mach_ppc_e500mc)
- || (info->disassembler_options
- && strstr (info->disassembler_options, "e500mc") != NULL))
-@@ -112,8 +112,9 @@
-
- if (info->disassembler_options
- && strstr (info->disassembler_options, "power7") != NULL)
-- dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
-- | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX;
-+ dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5
-+ | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7
-+ | PPC_OPCODE_ISEL | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX;
-
- if (info->disassembler_options
- && strstr (info->disassembler_options, "vsx") != NULL)
-@@ -266,7 +267,8 @@
- continue;
-
- if ((insn & opcode->mask) != opcode->opcode
-- || (opcode->flags & dialect) == 0)
-+ || (opcode->flags & dialect) == 0
-+ || (opcode->deprecated & dialect) != 0)
- continue;
-
- /* Make two passes over the operands. First see if any of them
-@@ -402,7 +404,7 @@
- The following PPC specific disassembler options are supported for use with\n\
- the -M switch:\n");
-
-- fprintf (stream, " booke|booke32|booke64 Disassemble the BookE instructions\n");
-+ fprintf (stream, " booke Disassemble the BookE instructions\n");
- fprintf (stream, " e300 Disassemble the e300 instructions\n");
- fprintf (stream, " e500|e500x2 Disassemble the e500 instructions\n");
- fprintf (stream, " e500mc Disassemble the e500mc instructions\n");
-diff -Naur binutils-2.19.1.orig/opcodes/ppc-opc.c binutils-2.19.1/opcodes/ppc-opc.c
---- binutils-2.19.1.orig/opcodes/ppc-opc.c 2008-12-23 05:54:52.000000000 -0800
-+++ binutils-2.19.1/opcodes/ppc-opc.c 2009-03-03 17:08:22.000000000 -0800
-@@ -1,6 +1,6 @@
- /* ppc-opc.c -- PowerPC opcode list
- Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
-- 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
-+ 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
- Written by Ian Lance Taylor, Cygnus Support
-
- This file is part of the GNU opcodes library.
-@@ -81,6 +81,10 @@
- static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
- static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
- static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
-+static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
-+static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
-+static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
-+static long extract_dm (unsigned long, ppc_cpu_t, int *);
- \f
- /* The operands table.
-
-@@ -223,19 +227,9 @@
- #define D CT + 1
- { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
-
-- /* The DE field in a DE form instruction. This is like D, but is 12
-- bits only. */
--#define DE D + 1
-- { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
--
-- /* The DES field in a DES form instruction. This is like DS, but is 14
-- bits only (12 stored.) */
--#define DES DE + 1
-- { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
--
- /* The DQ field in a DQ form instruction. This is like D, but the
- lower four bits are forced to zero. */
--#define DQ DES + 1
-+#define DQ D + 1
- { 0xfff0, 0, NULL, NULL,
- PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
-
-@@ -320,8 +314,9 @@
- #define LIA LI + 1
- { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
-
-- /* The LS field in an X (sync) form instruction. */
-+ /* The LS or WC field in an X (sync or wait) form instruction. */
- #define LS LIA + 1
-+#define WC LS
- { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
-
- /* The ME field in an M form instruction. */
-@@ -617,7 +612,7 @@
- #define XA6 XT6 + 1
- { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
-
-- /* The XB field in an XX3 form instruction. This is split. */
-+ /* The XB field in an XX2 or XX3 form instruction. This is split. */
- #define XB6 XA6 + 1
- { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
-
-@@ -627,9 +622,22 @@
- #define XB6S XB6 + 1
- { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
-
-- /* The DM field in an XX3 form instruction. */
--#define DM XB6S + 1
-+ /* The XC field in an XX4 form instruction. This is split. */
-+#define XC6 XB6S + 1
-+ { 0x3f, -1, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
-+
-+ /* The DM or SHW field in an XX3 form instruction. */
-+#define DM XC6 + 1
-+#define SHW DM
- { 0x3, 8, NULL, NULL, 0 },
-+
-+ /* The DM field in an extended mnemonic XX3 form instruction. */
-+#define DMEX DM + 1
-+ { 0x3, 8, insert_dm, extract_dm, 0 },
-+
-+ /* The UIM field in an XX2 form instruction. */
-+#define UIM DMEX + 1
-+ { 0x3, 16, NULL, NULL, 0 },
- };
-
- const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
-@@ -1405,6 +1413,49 @@
- *invalid = 1;
- return 0;
- }
-+
-+/* The XC field in an XX4 form instruction. This is split. */
-+
-+static unsigned long
-+insert_xc6 (unsigned long insn,
-+ long value,
-+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
-+ const char **errmsg ATTRIBUTE_UNUSED)
-+{
-+ return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
-+}
-+
-+static long
-+extract_xc6 (unsigned long insn,
-+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
-+ int *invalid ATTRIBUTE_UNUSED)
-+{
-+ return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
-+}
-+
-+static unsigned long
-+insert_dm (unsigned long insn,
-+ long value,
-+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
-+ const char **errmsg)
-+{
-+ if (value != 0 && value != 1)
-+ *errmsg = _("invalid constant");
-+ return insn | (((value) ? 3 : 0) << 8);
-+}
-+
-+static long
-+extract_dm (unsigned long insn,
-+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
-+ int *invalid)
-+{
-+ long value;
-+
-+ value = (insn >> 8) & 3;
-+ if (value != 0 && value != 3)
-+ *invalid = 1;
-+ return (value) ? 1 : 0;
-+}
- \f
- /* Macros used to form opcodes. */
-
-@@ -1487,10 +1538,6 @@
- #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
- #define DS_MASK DSO (0x3f, 3)
-
--/* A DE form instruction. */
--#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
--#define DE_MASK DEO (0x3e, 0xf)
--
- /* An EVSEL form instruction. */
- #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
- #define EVSEL_MASK EVSEL(0x3f, 0xff)
-@@ -1550,11 +1597,17 @@
- /* An X form instruction. */
- #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
-
-+/* An XX2 form instruction. */
-+#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
-+
- /* An XX3 form instruction. */
- #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
-
--#define XX3DM(op, xop, dm) (XX3 (op, ((unsigned long)(xop) & 0x1f)) \
-- | ((((unsigned long)(dm)) & 0x3) << 8))
-+/* An XX3 form instruction with the RC bit specified. */
-+#define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
-+
-+/* An XX4 form instruction. */
-+#define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
-
- /* A Z form instruction. */
- #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
-@@ -1571,11 +1624,30 @@
- /* The mask for an XX1 form instruction. */
- #define XX1_MASK X (0x3f, 0x3ff)
-
-+/* The mask for an XX2 form instruction. */
-+#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
-+
-+/* The mask for an XX2 form instruction with the UIM bits specified. */
-+#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
-+
-+/* The mask for an XX2 form instruction with the BF bits specified. */
-+#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
-+
- /* The mask for an XX3 form instruction. */
- #define XX3_MASK XX3 (0x3f, 0xff)
-
--/* The mask for an XX3 form instruction with the DM bits specified. */
-+/* The mask for an XX3 form instruction with the BF bits specified. */
-+#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
-+
-+/* The mask for an XX3 form instruction with the DM or SHW bits specified. */
- #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
-+#define XX3SHW_MASK XX3DM_MASK
-+
-+/* The mask for an XX4 form instruction. */
-+#define XX4_MASK XX4 (0x3f, 0x3)
-+
-+/* An X form wait instruction with everything filled in except the WC field. */
-+#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
-
- /* The mask for a Z form instruction. */
- #define Z_MASK ZRC (0x3f, 0x1ff, 1)
-@@ -1810,13 +1882,14 @@
- \f
- /* Smaller names for the flags so each entry in the opcodes table will
- fit on a single line. */
-+#define PPCNONE 0
- #undef PPC
- #define PPC PPC_OPCODE_PPC
- #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
--#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
- #define POWER4 PPC_OPCODE_POWER4
- #define POWER5 PPC_OPCODE_POWER5
- #define POWER6 PPC_OPCODE_POWER6
-+#define POWER7 PPC_OPCODE_POWER7
- #define CELL PPC_OPCODE_CELL
- #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
- #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
-@@ -1841,7 +1914,6 @@
- #define MFDEC1 PPC_OPCODE_POWER
- #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
- #define BOOKE PPC_OPCODE_BOOKE
--#define BOOKE64 PPC_OPCODE_BOOKE64
- #define CLASSIC PPC_OPCODE_CLASSIC
- #define PPCE300 PPC_OPCODE_E300
- #define PPCSPE PPC_OPCODE_SPE
-@@ -1850,7 +1922,6 @@
- #define PPCBRLK PPC_OPCODE_BRLOCK
- #define PPCPMR PPC_OPCODE_PMR
- #define PPCCHLK PPC_OPCODE_CACHELCK
--#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
- #define PPCRFMCI PPC_OPCODE_RFMCI
- #define E500MC PPC_OPCODE_E500MC
- \f
-@@ -1876,3253 +1947,3347 @@
- constrained otherwise by disassembler operation. */
-
- const struct powerpc_opcode powerpc_opcodes[] = {
--{"attn", X(0,256), X_MASK, POWER4, {0}},
--{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, {RA, SI}},
--{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, {RA, SI}},
--{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, {RA, SI}},
--{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, {RA, SI}},
--{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, {RA, SI}},
--{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, {RA, SI}},
--{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, {RA, SI}},
--{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, {RA, SI}},
--{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, {RA, SI}},
--{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, {RA, SI}},
--{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, {RA, SI}},
--{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, {RA, SI}},
--{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, {RA, SI}},
--{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, {RA, SI}},
--{"tdi", OP(2), OP_MASK, PPC64, {TO, RA, SI}},
--
--{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, {RA, SI}},
--{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, {RA, SI}},
--{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, {RA, SI}},
--{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, {RA, SI}},
--{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, {RA, SI}},
--{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, {RA, SI}},
--{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, {RA, SI}},
--{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, {RA, SI}},
--{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, {RA, SI}},
--{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, {RA, SI}},
--{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, {RA, SI}},
--{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, {RA, SI}},
--{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, {RA, SI}},
--{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, {RA, SI}},
--{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, {RA, SI}},
--{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, {RA, SI}},
--{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, {RA, SI}},
--{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, {RA, SI}},
--{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, {RA, SI}},
--{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, {RA, SI}},
--{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, {RA, SI}},
--{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, {RA, SI}},
--{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, {RA, SI}},
--{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, {RA, SI}},
--{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, {RA, SI}},
--{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, {RA, SI}},
--{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, {RA, SI}},
--{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, {RA, SI}},
--{"twi", OP(3), OP_MASK, PPCCOM, {TO, RA, SI}},
--{"ti", OP(3), OP_MASK, PWRCOM, {TO, RA, SI}},
--
--{"ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}},
--{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vrlb", VX (4, 4), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, {FRT,RA,RB,PSWM,PSQM}},
--{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, {FRS,RA,RB,PSWM,PSQM}},
--{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"mulhhwu", XRC(4, 8,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"mulhhwu.", XRC(4, 8,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
--{"machhwu", XO (4, 12,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
--{"machhwu.", XO (4, 12,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
--{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
--{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
--{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
--{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
--{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
--{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
--{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
--{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
--{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
--{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
--{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
--{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
--{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
--{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
--{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
--{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
--{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
--{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
--{"vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, {VD, VA, VB, SHB}},
--{"ps_sel", A (4, 23,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, {VD, VA, VC, VB}},
--{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, {VD, VA, VC, VB}},
--{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, {FRT, FRB}},
--{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, {FRT, FRB}},
--{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
--{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
--{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, {FRT, FRB}},
--{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, {FRT, FRB}},
--{"ps_msub", A (4, 28,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"ps_madd", A (4, 29,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
--{"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}},
--{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vrlh", VX (4, 68), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, {FRT,RA,RB,PSWM,PSQM}},
--{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, {FRS,RA,RB,PSWM,PSQM}},
--{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, {FRT, FRB}},
--{"mulhhw", XRC(4, 40,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, {FRT, FRB}},
--{"mulhhw.", XRC(4, 40,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"machhw", XO (4, 44,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"machhw.", XO (4, 44,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmachhw", XO (4, 46,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmachhw.", XO (4, 46,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}},
--{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vrlw", VX (4, 132), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, {FRT, FRB}},
--{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, {FRT, FRB}},
--{"machhwsu", XO (4, 76,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"machhwsu.", XO (4, 76,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}},
--{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"machhws", XO (4, 108,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"machhws.", XO (4, 108,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmachhws", XO (4, 110,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmachhws.", XO (4, 110,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vslb", VX (4, 260), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vrefp", VX (4, 266), VX_MASK, PPCVEC, {VD, VB}},
--{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, {FRT, FRB}},
--{"mulchwu", XRC(4, 136,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, {FRT, FRB}},
--{"mulchwu.", XRC(4, 136,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"macchwu", XO (4, 140,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"macchwu.", XO (4, 140,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vslh", VX (4, 324), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vrsqrtefp", VX (4, 330), VX_MASK, PPCVEC, {VD, VB}},
--{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"mulchw", XRC(4, 168,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"mulchw.", XRC(4, 168,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"macchw", XO (4, 172,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"macchw.", XO (4, 172,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmacchw", XO (4, 174,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmacchw.", XO (4, 174,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vslw", VX (4, 388), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vexptefp", VX (4, 394), VX_MASK, PPCVEC, {VD, VB}},
--{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"macchwsu", XO (4, 204,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"macchwsu.", XO (4, 204,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"vsl", VX (4, 452), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"vlogefp", VX (4, 458), VX_MASK, PPCVEC, {VD, VB}},
--{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"macchws", XO (4, 236,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"macchws.", XO (4, 236,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmacchws", XO (4, 238,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmacchws.", XO (4, 238,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"evaddw", VX (4, 512), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, {RS, RB, UIMM}},
--{"vminub", VX (4, 514), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evsubw", VX (4, 516), VX_MASK, PPCSPE, {RS, RB, RA}},
--{"vsrb", VX (4, 516), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, {RS, UIMM, RB}},
--{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, {RS, RB, UIMM}},
--{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"evabs", VX (4, 520), VX_MASK, PPCSPE, {RS, RA}},
--{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evneg", VX (4, 521), VX_MASK, PPCSPE, {RS, RA}},
--{"evextsb", VX (4, 522), VX_MASK, PPCSPE, {RS, RA}},
--{"vrfin", VX (4, 522), VX_MASK, PPCVEC, {VD, VB}},
--{"evextsh", VX (4, 523), VX_MASK, PPCSPE, {RS, RA}},
--{"evrndw", VX (4, 524), VX_MASK, PPCSPE, {RS, RA}},
--{"vspltb", VX (4, 524), VX_MASK, PPCVEC, {VD, VB, UIMM}},
--{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, {RS, RA}},
--{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, {RS, RA}},
--{"vupkhsb", VX (4, 526), VX_MASK, PPCVEC, {VD, VB}},
--{"brinc", VX (4, 527), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, {FRT, FRB}},
--{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, {FRT, FRB}},
--{"evand", VX (4, 529), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evandc", VX (4, 530), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evxor", VX (4, 534), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmr", VX (4, 535), VX_MASK, PPCSPE, {RS, RA, BBA}},
--{"evor", VX (4, 535), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evnor", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evnot", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, BBA}},
--{"get", APU(4, 268,0), APU_RA_MASK, PPC405, {RT, FSL}},
--{"eveqv", VX (4, 537), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evorc", VX (4, 539), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evnand", VX (4, 542), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evsrws", VX (4, 545), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, {RS, RA, EVUIMM}},
--{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, {RS, RA, EVUIMM}},
--{"evslw", VX (4, 548), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evslwi", VX (4, 550), VX_MASK, PPCSPE, {RS, RA, EVUIMM}},
--{"evrlw", VX (4, 552), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evsplati", VX (4, 553), VX_MASK, PPCSPE, {RS, SIMM}},
--{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, {RS, RA, EVUIMM}},
--{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, {RS, SIMM}},
--{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, {CRFD, RA, RB}},
--{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, {CRFD, RA, RB}},
--{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, {CRFD, RA, RB}},
--{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, {CRFD, RA, RB}},
--{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, {CRFD, RA, RB}},
--{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, {RT, FSL}},
--{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vminuh", VX (4, 578), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vsrh", VX (4, 580), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vrfiz", VX (4, 586), VX_MASK, PPCVEC, {VD, VB}},
--{"vsplth", VX (4, 588), VX_MASK, PPCVEC, {VD, VB, UIMM}},
--{"vupkhsh", VX (4, 590), VX_MASK, PPCVEC, {VD, VB}},
--{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, {RT, FSL}},
--{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, {RS, RA, RB, CRFS}},
--{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, {RT, FSL}},
--{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vadduws", VX (4, 640), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evfssub", VX (4, 641), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vminuw", VX (4, 642), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, {RS, RA}},
--{"vsrw", VX (4, 644), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, {RS, RA}},
--{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, {RS, RA}},
--{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vrfip", VX (4, 650), VX_MASK, PPCVEC, {VD, VB}},
--{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, {CRFD, RA, RB}},
--{"vspltw", VX (4, 652), VX_MASK, PPCVEC, {VD, VB, UIMM}},
--{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, {CRFD, RA, RB}},
--{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, {CRFD, RA, RB}},
--{"vupklsb", VX (4, 654), VX_MASK, PPCVEC, {VD, VB}},
--{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, {RS, RB}},
--{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, {RS, RB}},
--{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, {RS, RB}},
--{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, {RS, RB}},
--{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, {RS, RB}},
--{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, {RS, RB}},
--{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, {RS, RB}},
--{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, {RS, RB}},
--{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, {RS, RB}},
--{"put", APU(4, 332,0), APU_RT_MASK, PPC405, {RA, FSL}},
--{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, {RS, RB}},
--{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, {CRFD, RA, RB}},
--{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, {CRFD, RA, RB}},
--{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, {CRFD, RA, RB}},
--{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, {RA, FSL}},
--{"efsadd", VX (4, 704), VX_MASK, PPCEFS, {RS, RA, RB}},
--{"efssub", VX (4, 705), VX_MASK, PPCEFS, {RS, RA, RB}},
--{"efsabs", VX (4, 708), VX_MASK, PPCEFS, {RS, RA}},
--{"vsr", VX (4, 708), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, {RS, RA}},
--{"efsneg", VX (4, 710), VX_MASK, PPCEFS, {RS, RA}},
--{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"efsmul", VX (4, 712), VX_MASK, PPCEFS, {RS, RA, RB}},
--{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, {RS, RA, RB}},
--{"vrfim", VX (4, 714), VX_MASK, PPCVEC, {VD, VB}},
--{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, {CRFD, RA, RB}},
--{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, {CRFD, RA, RB}},
--{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, {CRFD, RA, RB}},
--{"vupklsh", VX (4, 718), VX_MASK, PPCVEC, {VD, VB}},
--{"efscfd", VX (4, 719), VX_MASK, PPCEFS, {RS, RB}},
--{"efscfui", VX (4, 720), VX_MASK, PPCEFS, {RS, RB}},
--{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, {RS, RB}},
--{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, {RS, RB}},
--{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, {RS, RB}},
--{"efsctui", VX (4, 724), VX_MASK, PPCEFS, {RS, RB}},
--{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, {RS, RB}},
--{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, {RS, RB}},
--{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, {RS, RB}},
--{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, {RS, RB}},
--{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, {RA, FSL}},
--{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, {RS, RB}},
--{"efststgt", VX (4, 732), VX_MASK, PPCEFS, {CRFD, RA, RB}},
--{"efststlt", VX (4, 733), VX_MASK, PPCEFS, {CRFD, RA, RB}},
--{"efststeq", VX (4, 734), VX_MASK, PPCEFS, {CRFD, RA, RB}},
--{"efdadd", VX (4, 736), VX_MASK, PPCEFS, {RS, RA, RB}},
--{"efdsub", VX (4, 737), VX_MASK, PPCEFS, {RS, RA, RB}},
--{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, {RS, RB}},
--{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, {RS, RB}},
--{"efdabs", VX (4, 740), VX_MASK, PPCEFS, {RS, RA}},
--{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, {RS, RA}},
--{"efdneg", VX (4, 742), VX_MASK, PPCEFS, {RS, RA}},
--{"efdmul", VX (4, 744), VX_MASK, PPCEFS, {RS, RA, RB}},
--{"efddiv", VX (4, 745), VX_MASK, PPCEFS, {RS, RA, RB}},
--{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, {RS, RB}},
--{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, {RS, RB}},
--{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, {CRFD, RA, RB}},
--{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, {CRFD, RA, RB}},
--{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, {CRFD, RA, RB}},
--{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, {RS, RB}},
--{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, {RS, RB}},
--{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, {RS, RB}},
--{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, {RS, RB}},
--{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, {RS, RB}},
--{"efdctui", VX (4, 756), VX_MASK, PPCEFS, {RS, RB}},
--{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, {RS, RB}},
--{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, {RS, RB}},
--{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, {RS, RB}},
--{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, {RS, RB}},
--{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, {RA, FSL}},
--{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, {RS, RB}},
--{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, {CRFD, RA, RB}},
--{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, {CRFD, RA, RB}},
--{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, {CRFD, RA, RB}},
--{"evlddx", VX (4, 768), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evldd", VX (4, 769), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
--{"evldwx", VX (4, 770), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vminsb", VX (4, 770), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evldw", VX (4, 771), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
--{"evldhx", VX (4, 772), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vsrab", VX (4, 772), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evldh", VX (4, 773), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
--{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}},
--{"vcfux", VX (4, 778), VX_MASK, PPCVEC, {VD, VB, UIMM}},
--{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vspltisb", VX (4, 780), VX_MASK, PPCVEC, {VD, SIMM}},
--{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}},
--{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}},
--{"mullhwu", XRC(4, 392,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"mullhwu.", XRC(4, 392,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
--{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
--{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
--{"maclhwu", XO (4, 396,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"maclhwu.", XO (4, 396,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
--{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
--{"evstddx", VX (4, 800), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evstdd", VX (4, 801), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
--{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evstdw", VX (4, 803), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
--{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evstdh", VX (4, 805), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
--{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
--{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evstwho", VX (4, 821), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
--{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
--{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
--{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vminsh", VX (4, 834), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vsrah", VX (4, 836), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, {VD, VB, UIMM}},
--{"vspltish", VX (4, 844), VX_MASK, PPCVEC, {VD, SIMM}},
--{"vupkhpx", VX (4, 846), VX_MASK, PPCVEC, {VD, VB}},
--{"mullhw", XRC(4, 424,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"mullhw.", XRC(4, 424,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"maclhw", XO (4, 428,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"maclhw.", XO (4, 428,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmaclhw", XO (4, 430,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmaclhw.", XO (4, 430,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vminsw", VX (4, 898), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vsraw", VX (4, 900), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, {VD, VB, UIMM}},
--{"vspltisw", VX (4, 908), VX_MASK, PPCVEC, {VD, SIMM}},
--{"maclhwsu", XO (4, 460,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"maclhwsu.", XO (4, 460,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, {VD, VB, UIMM}},
--{"vupklpx", VX (4, 974), VX_MASK, PPCVEC, {VD, VB}},
--{"maclhws", XO (4, 492,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"maclhws.", XO (4, 492,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmaclhws", XO (4, 494,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmaclhws.", XO (4, 494,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"vsububm", VX (4,1024), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vavgub", VX (4,1026), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vand", VX (4,1028), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
--{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
--{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vslo", VX (4,1036), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"machhwuo", XO (4, 12,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"machhwuo.", XO (4, 12,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
--{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
--{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vavguh", VX (4,1090), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vandc", VX (4,1092), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
--{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
--{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vminfp", VX (4,1098), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vsro", VX (4,1100), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"machhwo", XO (4, 44,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"machhwo.", XO (4, 44,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"nmachhwo", XO (4, 46,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmachhwo.", XO (4, 46,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
--{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
--{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vavguw", VX (4,1154), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vor", VX (4,1156), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
--{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
--{"machhwsuo", XO (4, 76,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"machhwsuo.", XO (4, 76,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
--{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
--{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, {RS, RA}},
--{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, {RS, RA}},
--{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, {RS, RA}},
--{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, {RS, RA}},
--{"evmra", VX (4,1220), VX_MASK, PPCSPE, {RS, RA}},
--{"vxor", VX (4,1220), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evdivws", VX (4,1222), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
--{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
--{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, {RS, RA}},
--{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, {RS, RA}},
--{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, {RS, RA}},
--{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, {RS, RA}},
--{"machhwso", XO (4, 108,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"machhwso.", XO (4, 108,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmachhwso", XO (4, 110,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmachhwso.", XO (4, 110,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
--{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
--{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vnor", VX (4,1284), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
--{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
--{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"macchwuo", XO (4, 140,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"macchwuo.", XO (4, 140,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
--{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
--{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"macchwo", XO (4, 172,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"macchwo.", XO (4, 172,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"nmacchwo", XO (4, 174,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmacchwo.", XO (4, 174,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
--{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
--{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"macchwsuo", XO (4, 204,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"macchwsuo.", XO (4, 204,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
--{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
--{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"macchwso", XO (4, 236,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"macchwso.", XO (4, 236,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, {RS, RA, RB}},
--{"nmacchwso", XO (4, 238,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmacchwso.", XO (4, 238,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"vsububs", VX (4,1536), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"mfvscr", VX (4,1540), VX_MASK, PPCVEC, {VD}},
--{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, {URT, URA, URB}},
--{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, {URT, URA, URB}},
--{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"mtvscr", VX (4,1604), VX_MASK, PPCVEC, {VB}},
--{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, {URT, URA, URB}},
--{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, {URT, URA, URB}},
--{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, {URT, URA, URB}},
--{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, {URT, URA, URB}},
--{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, {URT, URA, URB}},
--{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, {URT, URA, URB}},
--{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, {URT, URA, URB}},
--{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, {URT, URA, URB}},
--{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"maclhwuo", XO (4, 396,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"maclhwuo.", XO (4, 396,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, {URT, URA, URB}},
--{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, {URT, URA, URB}},
--{"maclhwo", XO (4, 428,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"maclhwo.", XO (4, 428,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmaclhwo", XO (4, 430,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmaclhwo.", XO (4, 430,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, {URT, URA, URB}},
--{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, {URT, URA, URB}},
--{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, {VD, VA, VB}},
--{"maclhwsuo", XO (4, 460,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"maclhwsuo.", XO (4, 460,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
--{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, {URT, URA, URB}},
--{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, {URT, URA, URB}},
--{"maclhwso", XO (4, 492,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"maclhwso.", XO (4, 492,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmaclhwso", XO (4, 494,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
--{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, {RA, RB}},
--
--{"mulli", OP(7), OP_MASK, PPCCOM, {RT, RA, SI}},
--{"muli", OP(7), OP_MASK, PWRCOM, {RT, RA, SI}},
--
--{"subfic", OP(8), OP_MASK, PPCCOM, {RT, RA, SI}},
--{"sfi", OP(8), OP_MASK, PWRCOM, {RT, RA, SI}},
--
--{"dozi", OP(9), OP_MASK, M601, {RT, RA, SI}},
--
--{"bce", B(9,0,0), B_MASK, BOOKE64, {BO, BI, BD}},
--{"bcel", B(9,0,1), B_MASK, BOOKE64, {BO, BI, BD}},
--{"bcea", B(9,1,0), B_MASK, BOOKE64, {BO, BI, BDA}},
--{"bcela", B(9,1,1), B_MASK, BOOKE64, {BO, BI, BDA}},
--
--{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, {OBF, RA, UI}},
--{"cmpldi", OPL(10,1), OPL_MASK, PPC64, {OBF, RA, UI}},
--{"cmpli", OP(10), OP_MASK, PPC, {BF, L, RA, UI}},
--{"cmpli", OP(10), OP_MASK, PWRCOM, {BF, RA, UI}},
--
--{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, {OBF, RA, SI}},
--{"cmpdi", OPL(11,1), OPL_MASK, PPC64, {OBF, RA, SI}},
--{"cmpi", OP(11), OP_MASK, PPC, {BF, L, RA, SI}},
--{"cmpi", OP(11), OP_MASK, PWRCOM, {BF, RA, SI}},
--
--{"addic", OP(12), OP_MASK, PPCCOM, {RT, RA, SI}},
--{"ai", OP(12), OP_MASK, PWRCOM, {RT, RA, SI}},
--{"subic", OP(12), OP_MASK, PPCCOM, {RT, RA, NSI}},
--
--{"addic.", OP(13), OP_MASK, PPCCOM, {RT, RA, SI}},
--{"ai.", OP(13), OP_MASK, PWRCOM, {RT, RA, SI}},
--{"subic.", OP(13), OP_MASK, PPCCOM, {RT, RA, NSI}},
--
--{"li", OP(14), DRA_MASK, PPCCOM, {RT, SI}},
--{"lil", OP(14), DRA_MASK, PWRCOM, {RT, SI}},
--{"addi", OP(14), OP_MASK, PPCCOM, {RT, RA0, SI}},
--{"cal", OP(14), OP_MASK, PWRCOM, {RT, D, RA0}},
--{"subi", OP(14), OP_MASK, PPCCOM, {RT, RA0, NSI}},
--{"la", OP(14), OP_MASK, PPCCOM, {RT, D, RA0}},
--
--{"lis", OP(15), DRA_MASK, PPCCOM, {RT, SISIGNOPT}},
--{"liu", OP(15), DRA_MASK, PWRCOM, {RT, SISIGNOPT}},
--{"addis", OP(15), OP_MASK, PPCCOM, {RT, RA0, SISIGNOPT}},
--{"cau", OP(15), OP_MASK, PWRCOM, {RT, RA0, SISIGNOPT}},
--{"subis", OP(15), OP_MASK, PPCCOM, {RT, RA0, NSI}},
--
--{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BDM}},
--{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BDP}},
--{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BD}},
--{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, {BD}},
--{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BDM}},
--{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BDP}},
--{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BD}},
--{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, {BD}},
--{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDMA}},
--{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDPA}},
--{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDA}},
--{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, {BDA}},
--{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDMA}},
--{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDPA}},
--{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDA}},
--{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, {BDA}},
--{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, {BDM}},
--{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, {BDP}},
--{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, {BD}},
--{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, {BDM}},
--{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, {BDP}},
--{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, {BD}},
--{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, {BDMA}},
--{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, {BDPA}},
--{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, {BDA}},
--{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, {BDMA}},
--{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, {BDPA}},
--{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, {BDA}},
--
--{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}},
--{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}},
--{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}},
--{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}},
--{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
--{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
--{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
--{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
--{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}},
--{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}},
--{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}},
--{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}},
--{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
--{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
--{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
--{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
--{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, {CR, BD}},
--{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, {CR, BD}},
--{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, {CR, BDA}},
--{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, {CR, BDA}},
--{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, {CR, BD}},
--{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BD}},
--{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, {CR, BD}},
--{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BD}},
--{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, {CR, BDA}},
--{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDA}},
--{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, {CR, BDA}},
--{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDA}},
--
--{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}},
--{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}},
--{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
--{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
--{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}},
--{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}},
--{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
--{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
--{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, {CR, BD}},
--{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, {CR, BD}},
--{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, {CR, BDA}},
--{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, {CR, BDA}},
--{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, {CR, BD}},
--{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BD}},
--{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, {CR, BD}},
--{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
--{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
--{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BD}},
--{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, {CR, BDA}},
--{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDA}},
--{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, {CR, BDA}},
--{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
--{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
--{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDA}},
--
--{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}},
--{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}},
--{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, {BI, BD}},
--{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}},
--{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}},
--{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, {BI, BD}},
--{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}},
--{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}},
--{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, {BI, BDA}},
--{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}},
--{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}},
--{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, {BI, BDA}},
--{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}},
--{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}},
--{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, {BI, BD}},
--{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}},
--{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}},
--{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, {BI, BD}},
--{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}},
--{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}},
--{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, {BI, BDA}},
--{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}},
--{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}},
--{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, {BI, BDA}},
--
--{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BDM}},
--{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BDP}},
--{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BD}},
--{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, {BI, BD}},
--{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BDM}},
--{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BDP}},
--{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BD}},
--{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, {BI, BD}},
--{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDMA}},
--{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDPA}},
--{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDA}},
--{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, {BI, BDA}},
--{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDMA}},
--{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDPA}},
--{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDA}},
--{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, {BI, BDA}},
--
--{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}},
--{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}},
--{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, {BI, BD}},
--{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}},
--{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}},
--{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, {BI, BD}},
--{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}},
--{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}},
--{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, {BI, BDA}},
--{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}},
--{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}},
--{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, {BI, BDA}},
--{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}},
--{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}},
--{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, {BI, BD}},
--{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}},
--{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}},
--{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, {BI, BD}},
--{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}},
--{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}},
--{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, {BI, BDA}},
--{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}},
--{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}},
--{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, {BI, BDA}},
--
--{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BDM}},
--{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BDP}},
--{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BD}},
--{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, {BI, BD}},
--{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BDM}},
--{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BDP}},
--{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BD}},
--{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, {BI, BD}},
--{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDMA}},
--{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDPA}},
--{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDA}},
--{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, {BI, BDA}},
--{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDMA}},
--{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDPA}},
--{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDA}},
--{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, {BI, BDA}},
--
--{"bc-", B(16,0,0), B_MASK, PPCCOM, {BOE, BI, BDM}},
--{"bc+", B(16,0,0), B_MASK, PPCCOM, {BOE, BI, BDP}},
--{"bc", B(16,0,0), B_MASK, COM, {BO, BI, BD}},
--{"bcl-", B(16,0,1), B_MASK, PPCCOM, {BOE, BI, BDM}},
--{"bcl+", B(16,0,1), B_MASK, PPCCOM, {BOE, BI, BDP}},
--{"bcl", B(16,0,1), B_MASK, COM, {BO, BI, BD}},
--{"bca-", B(16,1,0), B_MASK, PPCCOM, {BOE, BI, BDMA}},
--{"bca+", B(16,1,0), B_MASK, PPCCOM, {BOE, BI, BDPA}},
--{"bca", B(16,1,0), B_MASK, COM, {BO, BI, BDA}},
--{"bcla-", B(16,1,1), B_MASK, PPCCOM, {BOE, BI, BDMA}},
--{"bcla+", B(16,1,1), B_MASK, PPCCOM, {BOE, BI, BDPA}},
--{"bcla", B(16,1,1), B_MASK, COM, {BO, BI, BDA}},
--
--{"svc", SC(17,0,0), SC_MASK, POWER, {SVC_LEV, FL1, FL2}},
--{"svcl", SC(17,0,1), SC_MASK, POWER, {SVC_LEV, FL1, FL2}},
--{"sc", SC(17,1,0), SC_MASK, PPC, {LEV}},
--{"svca", SC(17,1,0), SC_MASK, PWRCOM, {SV}},
--{"svcla", SC(17,1,1), SC_MASK, POWER, {SV}},
--
--{"b", B(18,0,0), B_MASK, COM, {LI}},
--{"bl", B(18,0,1), B_MASK, COM, {LI}},
--{"ba", B(18,1,0), B_MASK, COM, {LIA}},
--{"bla", B(18,1,1), B_MASK, COM, {LIA}},
--
--{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, {BF, BFA}},
--
--{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, {0}},
--{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, {0}},
--{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, {0}},
--{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, {0}},
--{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, {0}},
--{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, {0}},
--{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, {0}},
--{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, {0}},
--{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, {0}},
--{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, {0}},
--{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, {0}},
--{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, {0}},
--{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, {0}},
--{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, {0}},
--{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, {0}},
--{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, {0}},
--{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, {0}},
--{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, {0}},
--{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, {0}},
--{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, {0}},
--{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, {0}},
--{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, {0}},
--{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, {0}},
--{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, {0}},
--
--{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
--{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
--
--{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, {BI}},
--{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, {BI}},
--{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, {BI}},
--{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, {BI}},
--{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, {BI}},
--{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, {BI}},
--{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, {BI}},
--{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, {BI}},
--{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, {BI}},
--{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, {BI}},
--{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, {BI}},
--{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, {BI}},
--{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, {BI}},
--{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, {BI}},
--{"bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, {BI}},
--{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, {BI}},
--{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
--{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, {BI}},
--{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, {BI}},
--{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, {BI}},
--{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, {BI}},
--{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
--{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
--{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, {BI}},
--{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, {BI}},
--{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, {BI}},
--{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, {BI}},
--
--{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, {BOE, BI}},
--{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, {BOE, BI}},
--{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, {BOE, BI}},
--{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, {BOE, BI}},
--{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, {BO, BI, BH}},
--{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, {BO, BI}},
--{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, {BO, BI, BH}},
--{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, {BO, BI}},
--
--{"bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, {BO, BI}},
--{"bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, {BO, BI}},
--
--{"rfid", XL(19,18), 0xffffffff, PPC64, {0}},
--
--{"crnot", XL(19,33), XL_MASK, PPCCOM, {BT, BA, BBA}},
--{"crnor", XL(19,33), XL_MASK, COM, {BT, BA, BB}},
--{"rfmci", X(19,38), 0xffffffff, PPCRFMCI, {0}},
--
--{"rfdi", XL(19,39), 0xffffffff, E500MC, {0}},
--{"rfi", XL(19,50), 0xffffffff, COM, {0}},
--{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300, {0}},
--
--{"rfsvc", XL(19,82), 0xffffffff, POWER, {0}},
--
--{"rfgi", XL(19,102), 0xffffffff, E500MC, {0}},
--
--{"crandc", XL(19,129), XL_MASK, COM, {BT, BA, BB}},
--
--{"isync", XL(19,150), 0xffffffff, PPCCOM, {0}},
--{"ics", XL(19,150), 0xffffffff, PWRCOM, {0}},
--
--{"crclr", XL(19,193), XL_MASK, PPCCOM, {BT, BAT, BBA}},
--{"crxor", XL(19,193), XL_MASK, COM, {BT, BA, BB}},
--
--{"dnh", X(19,198), X_MASK, E500MC, {DUI, DUIS}},
--
--{"crnand", XL(19,225), XL_MASK, COM, {BT, BA, BB}},
--
--{"crand", XL(19,257), XL_MASK, COM, {BT, BA, BB}},
--
--{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, {0}},
--
--{"crset", XL(19,289), XL_MASK, PPCCOM, {BT, BAT, BBA}},
--{"creqv", XL(19,289), XL_MASK, COM, {BT, BA, BB}},
--
--{"doze", XL(19,402), 0xffffffff, POWER6, {0}},
--
--{"crorc", XL(19,417), XL_MASK, COM, {BT, BA, BB}},
--
--{"nap", XL(19,434), 0xffffffff, POWER6, {0}},
--
--{"crmove", XL(19,449), XL_MASK, PPCCOM, {BT, BA, BBA}},
--{"cror", XL(19,449), XL_MASK, COM, {BT, BA, BB}},
--
--{"sleep", XL(19,466), 0xffffffff, POWER6, {0}},
--{"rvwinkle", XL(19,498), 0xffffffff, POWER6, {0}},
--
--{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, {0}},
--{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, {0}},
--
--{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
--{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
--{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
--{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
--
--{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, {BI}},
--{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, {BI}},
--{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, {BI}},
--{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, {BI}},
--{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, {BI}},
--{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, {BI}},
--{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, {BI}},
--{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, {BI}},
--{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, {BI}},
--{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, {BI}},
--{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, {BI}},
--{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, {BI}},
--{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, {BI}},
--{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, {BI}},
--{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, {BI}},
--{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, {BI}},
--{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, {BI}},
--
--{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, {BOE, BI}},
--{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, {BOE, BI}},
--{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, {BOE, BI}},
--{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, {BOE, BI}},
--{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, {BO, BI, BH}},
--{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, {BO, BI}},
--{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, {BO, BI, BH}},
--{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, {BO, BI}},
--
--{"bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, {BO, BI}},
--{"bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, {BO, BI}},
--
--{"rlwimi", M(20,0), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}},
--{"rlimi", M(20,0), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}},
--
--{"rlwimi.", M(20,1), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}},
--{"rlimi.", M(20,1), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}},
--
--{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, {RA, RS, SH}},
--{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, {RA, RS, MB}},
--{"rlwinm", M(21,0), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}},
--{"rlinm", M(21,0), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}},
--{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, {RA, RS, SH}},
--{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, {RA, RS, MB}},
--{"rlwinm.", M(21,1), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}},
--{"rlinm.", M(21,1), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}},
--
--{"rlmi", M(22,0), M_MASK, M601, {RA, RS, RB, MBE, ME}},
--{"be", B(22,0,0), B_MASK, BOOKE64, {LI}},
--{"bel", B(22,0,1), B_MASK, BOOKE64, {LI}},
--{"rlmi.", M(22,1), M_MASK, M601, {RA, RS, RB, MBE, ME}},
--{"bea", B(22,1,0), B_MASK, BOOKE64, {LIA}},
--{"bela", B(22,1,1), B_MASK, BOOKE64, {LIA}},
--
--{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, {RA, RS, RB}},
--{"rlwnm", M(23,0), M_MASK, PPCCOM, {RA, RS, RB, MBE, ME}},
--{"rlnm", M(23,0), M_MASK, PWRCOM, {RA, RS, RB, MBE, ME}},
--{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, {RA, RS, RB}},
--{"rlwnm.", M(23,1), M_MASK, PPCCOM, {RA, RS, RB, MBE, ME}},
--{"rlnm.", M(23,1), M_MASK, PWRCOM, {RA, RS, RB, MBE, ME}},
--
--{"nop", OP(24), 0xffffffff, PPCCOM, {0}},
--{"ori", OP(24), OP_MASK, PPCCOM, {RA, RS, UI}},
--{"oril", OP(24), OP_MASK, PWRCOM, {RA, RS, UI}},
--
--{"oris", OP(25), OP_MASK, PPCCOM, {RA, RS, UI}},
--{"oriu", OP(25), OP_MASK, PWRCOM, {RA, RS, UI}},
--
--{"xori", OP(26), OP_MASK, PPCCOM, {RA, RS, UI}},
--{"xoril", OP(26), OP_MASK, PWRCOM, {RA, RS, UI}},
--
--{"xoris", OP(27), OP_MASK, PPCCOM, {RA, RS, UI}},
--{"xoriu", OP(27), OP_MASK, PWRCOM, {RA, RS, UI}},
--
--{"andi.", OP(28), OP_MASK, PPCCOM, {RA, RS, UI}},
--{"andil.", OP(28), OP_MASK, PWRCOM, {RA, RS, UI}},
--
--{"andis.", OP(29), OP_MASK, PPCCOM, {RA, RS, UI}},
--{"andiu.", OP(29), OP_MASK, PWRCOM, {RA, RS, UI}},
--
--{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, {RA, RS, SH6}},
--{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, {RA, RS, MB6}},
--{"rldicl", MD(30,0,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
--{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, {RA, RS, SH6}},
--{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, {RA, RS, MB6}},
--{"rldicl.", MD(30,0,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
--
--{"rldicr", MD(30,1,0), MD_MASK, PPC64, {RA, RS, SH6, ME6}},
--{"rldicr.", MD(30,1,1), MD_MASK, PPC64, {RA, RS, SH6, ME6}},
--
--{"rldic", MD(30,2,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
--{"rldic.", MD(30,2,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
--
--{"rldimi", MD(30,3,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
--{"rldimi.", MD(30,3,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
--
--{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, {RA, RS, RB}},
--{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, {RA, RS, RB, MB6}},
--{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, {RA, RS, RB}},
--{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, {RA, RS, RB, MB6}},
--
--{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, {RA, RS, RB, ME6}},
--{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, {RA, RS, RB, ME6}},
--
--{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, {OBF, RA, RB}},
--{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, {OBF, RA, RB}},
--{"cmp", X(31,0), XCMP_MASK, PPC, {BF, L, RA, RB}},
--{"cmp", X(31,0), XCMPL_MASK, PWRCOM, {BF, RA, RB}},
--
--{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, {RA, RB}},
--{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, {RA, RB}},
--{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, {RA, RB}},
--{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, {RA, RB}},
--{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, {RA, RB}},
--{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, {RA, RB}},
--{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, {RA, RB}},
--{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, {RA, RB}},
--{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, {RA, RB}},
--{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, {RA, RB}},
--{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, {RA, RB}},
--{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, {RA, RB}},
--{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, {RA, RB}},
--{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, {RA, RB}},
--{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, {RA, RB}},
--{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, {RA, RB}},
--{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, {RA, RB}},
--{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, {RA, RB}},
--{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, {RA, RB}},
--{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, {RA, RB}},
--{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, {RA, RB}},
--{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, {RA, RB}},
--{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, {RA, RB}},
--{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, {RA, RB}},
--{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, {RA, RB}},
--{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, {RA, RB}},
--{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, {RA, RB}},
--{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, {RA, RB}},
--{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, {0}},
--{"tw", X(31,4), X_MASK, PPCCOM, {TO, RA, RB}},
--{"t", X(31,4), X_MASK, PWRCOM, {TO, RA, RB}},
--
--{"lvsl", X(31,6), X_MASK, PPCVEC, {VD, RA, RB}},
--{"lvebx", X(31,7), X_MASK, PPCVEC, {VD, RA, RB}},
--{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
--{"subc", XO(31,8,0,0), XO_MASK, PPC, {RT, RB, RA}},
--{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
--{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, {RT, RB, RA}},
--
--{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, {RT, RA, RB}},
--{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, {RT, RA, RB}},
--
--{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"a", XO(31,10,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
--{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
--
--{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, {RT, RA, RB}},
--{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, {RT, RA, RB}},
--
--{"isellt", X(31,15), X_MASK, PPCISEL, {RT, RA, RB}},
--
--{"mfcr", XFXM(31,19,0,0), XRARB_MASK, NOPOWER4|COM, {RT}},
--{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, {RT, FXM4}},
--{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, {RT, FXM}},
--
--{"lwarx", X(31,20), XEH_MASK, PPC, {RT, RA0, RB, EH}},
--
--{"ldx", X(31,21), X_MASK, PPC64, {RT, RA0, RB}},
--
--{"icbt", X(31,22), X_MASK, BOOKE|PPCE300, {CT, RA, RB}},
--
--{"lwzx", X(31,23), X_MASK, PPCCOM, {RT, RA0, RB}},
--{"lx", X(31,23), X_MASK, PWRCOM, {RT, RA, RB}},
--
--{"slw", XRC(31,24,0), X_MASK, PPCCOM, {RA, RS, RB}},
--{"sl", XRC(31,24,0), X_MASK, PWRCOM, {RA, RS, RB}},
--{"slw.", XRC(31,24,1), X_MASK, PPCCOM, {RA, RS, RB}},
--{"sl.", XRC(31,24,1), X_MASK, PWRCOM, {RA, RS, RB}},
--
--{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, {RA, RS}},
--{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, {RA, RS}},
--{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, {RA, RS}},
--{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, {RA, RS}},
--
--{"sld", XRC(31,27,0), X_MASK, PPC64, {RA, RS, RB}},
--{"sld.", XRC(31,27,1), X_MASK, PPC64, {RA, RS, RB}},
--
--{"and", XRC(31,28,0), X_MASK, COM, {RA, RS, RB}},
--{"and.", XRC(31,28,1), X_MASK, COM, {RA, RS, RB}},
--
--{"maskg", XRC(31,29,0), X_MASK, M601, {RA, RS, RB}},
--{"maskg.", XRC(31,29,1), X_MASK, M601, {RA, RS, RB}},
--
--{"ldepx", X(31,29), X_MASK, E500MC, {RT, RA, RB}},
--
--{"icbte", X(31,30), X_MASK, BOOKE64, {CT, RA, RB}},
--
--{"lwzxe", X(31,31), X_MASK, BOOKE64, {RT, RA0, RB}},
--{"lwepx", X(31,31), X_MASK, E500MC, {RT, RA, RB}},
--
--{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, {OBF, RA, RB}},
--{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, {OBF, RA, RB}},
--{"cmpl", X(31,32), XCMP_MASK, PPC, {BF, L, RA, RB}},
--{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, {BF, RA, RB}},
--
--{"lvsr", X(31,38), X_MASK, PPCVEC, {VD, RA, RB}},
--{"lvehx", X(31,39), X_MASK, PPCVEC, {VD, RA, RB}},
--{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"iselgt", X(31,47), X_MASK, PPCISEL, {RT, RA, RB}},
--
--{"lvewx", X(31,71), X_MASK, PPCVEC, {VD, RA, RB}},
--
--{"iseleq", X(31,79), X_MASK, PPCISEL, {RT, RA, RB}},
--
--{"isel", XISEL(31,15), XISEL_MASK, PPCISEL, {RT, RA, RB, CRB}},
--
--{"subf", XO(31,40,0,0), XO_MASK, PPC, {RT, RA, RB}},
--{"sub", XO(31,40,0,0), XO_MASK, PPC, {RT, RB, RA}},
--{"subf.", XO(31,40,0,1), XO_MASK, PPC, {RT, RA, RB}},
--{"sub.", XO(31,40,0,1), XO_MASK, PPC, {RT, RB, RA}},
--
--{"ldux", X(31,53), X_MASK, PPC64, {RT, RAL, RB}},
--
--{"dcbst", X(31,54), XRT_MASK, PPC, {RA, RB}},
--
--{"lwzux", X(31,55), X_MASK, PPCCOM, {RT, RAL, RB}},
--{"lux", X(31,55), X_MASK, PWRCOM, {RT, RA, RB}},
--
--{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, {RA, RS}},
--{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, {RA, RS}},
--
--{"andc", XRC(31,60,0), X_MASK, COM, {RA, RS, RB}},
--{"andc.", XRC(31,60,1), X_MASK, COM, {RA, RS, RB}},
--
--{"dcbste", X(31,62), XRT_MASK, BOOKE64, {RA, RB}},
--
--{"wait", X(31,62), 0xffffffff, E500MC, {0}},
--
--{"lwzuxe", X(31,63), X_MASK, BOOKE64, {RT, RAL, RB}},
--
--{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC, {RA, RB}},
--
--{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, {RA, RB}},
--{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, {RA, RB}},
--{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, {RA, RB}},
--{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, {RA, RB}},
--{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, {RA, RB}},
--{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, {RA, RB}},
--{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, {RA, RB}},
--{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, {RA, RB}},
--{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, {RA, RB}},
--{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, {RA, RB}},
--{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, {RA, RB}},
--{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, {RA, RB}},
--{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, {RA, RB}},
--{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, {RA, RB}},
--{"td", X(31,68), X_MASK, PPC64, {TO, RA, RB}},
--
--{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, {RT, RA, RB}},
--{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, {RT, RA, RB}},
--
--{"mulhw", XO(31,75,0,0), XO_MASK, PPC, {RT, RA, RB}},
--{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, {RT, RA, RB}},
--
--{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, {RA, RS, RB}},
--{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, {RA, RS, RB}},
--
--{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, {SR, RS}},
--
--{"mfmsr", X(31,83), XRARB_MASK, COM, {RT}},
--
--{"ldarx", X(31,84), XEH_MASK, PPC64, {RT, RA0, RB, EH}},
--
--{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, {RA, RB}},
--{"dcbf", X(31,86), XLRT_MASK, PPC, {RA, RB, L}},
--
--{"lbzx", X(31,87), X_MASK, COM, {RT, RA0, RB}},
--
--{"dcbfe", X(31,94), XRT_MASK, BOOKE64, {RA, RB}},
--
--{"lbzxe", X(31,95), X_MASK, BOOKE64, {RT, RA0, RB}},
--{"lbepx", X(31,95), X_MASK, E500MC, {RT, RA, RB}},
--
--{"lvx", X(31,103), X_MASK, PPCVEC, {VD, RA, RB}},
--{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"neg", XO(31,104,0,0), XORB_MASK, COM, {RT, RA}},
--{"neg.", XO(31,104,0,1), XORB_MASK, COM, {RT, RA}},
--
--{"mul", XO(31,107,0,0), XO_MASK, M601, {RT, RA, RB}},
--{"mul.", XO(31,107,0,1), XO_MASK, M601, {RT, RA, RB}},
--
--{"mtsrdin", X(31,114), XRA_MASK, PPC64, {RS, RB}},
--
--{"clf", X(31,118), XTO_MASK, POWER, {RA, RB}},
--
--{"lbzux", X(31,119), X_MASK, COM, {RT, RAL, RB}},
--
--{"popcntb", X(31,122), XRB_MASK, POWER5, {RA, RS}},
--
--{"not", XRC(31,124,0), X_MASK, COM, {RA, RS, RBS}},
--{"nor", XRC(31,124,0), X_MASK, COM, {RA, RS, RB}},
--{"not.", XRC(31,124,1), X_MASK, COM, {RA, RS, RBS}},
--{"nor.", XRC(31,124,1), X_MASK, COM, {RA, RS, RB}},
--
--{"lwarxe", X(31,126), X_MASK, BOOKE64, {RT, RA0, RB}},
--
--{"lbzuxe", X(31,127), X_MASK, BOOKE64, {RT, RAL, RB}},
--
--{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC, {RA, RB}},
--
--{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE, {RS}},
--
--{"dcbtstls", X(31,134), X_MASK, PPCCHLK, {CT, RA, RB}},
--
--{"stvebx", X(31,135), X_MASK, PPCVEC, {VS, RA, RB}},
--{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
--{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
--
--{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
--{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
--
--{"dcbtstlse", X(31,142), X_MASK, PPCCHLK64, {CT, RA, RB}},
--
--{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, {RS}},
--{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, {FXM, RS}},
--{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, {FXM, RS}},
--
--{"mtmsr", X(31,146), XRLARB_MASK, COM, {RS, A_L}},
--
--{"stdx", X(31,149), X_MASK, PPC64, {RS, RA0, RB}},
--
--{"stwcx.", XRC(31,150,1), X_MASK, PPC, {RS, RA0, RB}},
--
--{"stwx", X(31,151), X_MASK, PPCCOM, {RS, RA0, RB}},
--{"stx", X(31,151), X_MASK, PWRCOM, {RS, RA, RB}},
--
--{"slq", XRC(31,152,0), X_MASK, M601, {RA, RS, RB}},
--{"slq.", XRC(31,152,1), X_MASK, M601, {RA, RS, RB}},
--
--{"sle", XRC(31,153,0), X_MASK, M601, {RA, RS, RB}},
--{"sle.", XRC(31,153,1), X_MASK, M601, {RA, RS, RB}},
--
--{"prtyw", X(31,154), XRB_MASK, POWER6, {RA, RS}},
--
--{"stdepx", X(31,157), X_MASK, E500MC, {RS, RA, RB}},
--
--{"stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, {RS, RA0, RB}},
--
--{"stwxe", X(31,159), X_MASK, BOOKE64, {RS, RA0, RB}},
--{"stwepx", X(31,159), X_MASK, E500MC, {RS, RA, RB}},
--
--{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE, {E}},
--
--{"dcbtls", X(31,166), X_MASK, PPCCHLK, {CT, RA, RB}},
--
--{"stvehx", X(31,167), X_MASK, PPCVEC, {VS, RA, RB}},
--{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"dcbtlse", X(31,174), X_MASK, PPCCHLK64, {CT, RA, RB}},
--
--{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, {RS, A_L}},
--
--{"stdux", X(31,181), X_MASK, PPC64, {RS, RAS, RB}},
--
--{"stwux", X(31,183), X_MASK, PPCCOM, {RS, RAS, RB}},
--{"stux", X(31,183), X_MASK, PWRCOM, {RS, RA0, RB}},
--
--{"sliq", XRC(31,184,0), X_MASK, M601, {RA, RS, SH}},
--{"sliq.", XRC(31,184,1), X_MASK, M601, {RA, RS, SH}},
--
--{"prtyd", X(31,186), XRB_MASK, POWER6, {RA, RS}},
--
--{"stwuxe", X(31,191), X_MASK, BOOKE64, {RS, RAS, RB}},
--
--{"stvewx", X(31,199), X_MASK, PPCVEC, {VS, RA, RB}},
--{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, {RT, RA}},
--{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, {RT, RA}},
--{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, {RT, RA}},
--{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, {RT, RA}},
--
--{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, {RT, RA}},
--{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, {RT, RA}},
--{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, {RT, RA}},
--{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, {RT, RA}},
--
--{"msgsnd", XRTRA(31,206,0,0),XRTRA_MASK,E500MC, {RB}},
--
--{"mtsr", X(31,210), XRB_MASK|(1<<20), COM32, {SR, RS}},
--
--{"stdcx.", XRC(31,214,1), X_MASK, PPC64, {RS, RA0, RB}},
--
--{"stbx", X(31,215), X_MASK, COM, {RS, RA0, RB}},
--
--{"sllq", XRC(31,216,0), X_MASK, M601, {RA, RS, RB}},
--{"sllq.", XRC(31,216,1), X_MASK, M601, {RA, RS, RB}},
--
--{"sleq", XRC(31,217,0), X_MASK, M601, {RA, RS, RB}},
--{"sleq.", XRC(31,217,1), X_MASK, M601, {RA, RS, RB}},
--
--{"stbxe", X(31,223), X_MASK, BOOKE64, {RS, RA0, RB}},
--{"stbepx", X(31,223), X_MASK, E500MC, {RS, RA, RB}},
--
--{"icblc", X(31,230), X_MASK, PPCCHLK, {CT, RA, RB}},
--
--{"stvx", X(31,231), X_MASK, PPCVEC, {VS, RA, RB}},
--{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, {RT, RA}},
--{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, {RT, RA}},
--{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, {RT, RA}},
--{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, {RT, RA}},
--
--{"mulld", XO(31,233,0,0), XO_MASK, PPC64, {RT, RA, RB}},
--{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, {RT, RA, RB}},
--
--{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, {RT, RA}},
--{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, {RT, RA}},
--{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, {RT, RA}},
--{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, {RT, RA}},
--
--{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
--{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
--
--{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC, {RB}},
--{"icblce", X(31,238), X_MASK, PPCCHLK64, {CT, RA, RB}},
--{"mtsrin", X(31,242), XRA_MASK, PPC32, {RS, RB}},
--{"mtsri", X(31,242), XRA_MASK, POWER32, {RS, RB}},
--
--{"dcbtst", X(31,246), X_MASK, PPC, {CT, RA, RB}},
--
--{"stbux", X(31,247), X_MASK, COM, {RS, RAS, RB}},
--
--{"slliq", XRC(31,248,0), X_MASK, M601, {RA, RS, SH}},
--{"slliq.", XRC(31,248,1), X_MASK, M601, {RA, RS, SH}},
--
--{"dcbtste", X(31,253), X_MASK, BOOKE64, {CT, RA, RB}},
--
--{"stbuxe", X(31,255), X_MASK, BOOKE64, {RS, RAS, RB}},
--
--{"dcbtstep", XRT(31,255,0), X_MASK, E500MC, {RT, RA, RB}},
--
--{"mfdcrx", X(31,259), X_MASK, BOOKE, {RS, RA}},
--
--{"icbt", X(31,262), XRT_MASK, PPC403, {RA, RB}},
--
--{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--{"doz", XO(31,264,0,0), XO_MASK, M601, {RT, RA, RB}},
--{"doz.", XO(31,264,0,1), XO_MASK, M601, {RT, RA, RB}},
--
--{"add", XO(31,266,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
--{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
--
--{"ehpriv", X(31,270), 0xffffffff, E500MC, {0}},
--
--{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, {RB, L}},
--
--{"mfapidi", X(31,275), X_MASK, BOOKE, {RT, RA}},
--
--{"lscbx", XRC(31,277,0), X_MASK, M601, {RT, RA, RB}},
--{"lscbx.", XRC(31,277,1), X_MASK, M601, {RT, RA, RB}},
--
--{"dcbt", X(31,278), X_MASK, PPC, {CT, RA, RB}},
--
--{"lhzx", X(31,279), X_MASK, COM, {RT, RA0, RB}},
--
--{"eqv", XRC(31,284,0), X_MASK, COM, {RA, RS, RB}},
--{"eqv.", XRC(31,284,1), X_MASK, COM, {RA, RS, RB}},
--
--{"dcbte", X(31,286), X_MASK, BOOKE64, {CT, RA, RB}},
--
--{"lhzxe", X(31,287), X_MASK, BOOKE64, {RT, RA0, RB}},
--{"lhepx", X(31,287), X_MASK, E500MC, {RT, RA, RB}},
--
--{"mfdcrux", X(31,291), X_MASK, PPC464, {RS, RA}},
--
--{"tlbie", X(31,306), XRTLRA_MASK, PPC, {RB, L}},
--{"tlbi", X(31,306), XRT_MASK, POWER, {RA0, RB}},
--
--{"eciwx", X(31,310), X_MASK, PPC, {RT, RA, RB}},
--
--{"lhzux", X(31,311), X_MASK, COM, {RT, RAL, RB}},
--
--{"xor", XRC(31,316,0), X_MASK, COM, {RA, RS, RB}},
--{"xor.", XRC(31,316,1), X_MASK, COM, {RA, RS, RB}},
--
--{"lhzuxe", X(31,319), X_MASK, BOOKE64, {RT, RAL, RB}},
--
--{"dcbtep", XRT(31,319,0), X_MASK, E500MC, {RT, RA, RB}},
--
--{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, {RT}},
--{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, {RT}},
--{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, {RT}},
--{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, {RT}},
--{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, {RT}},
--{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, {RT}},
--{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, {RT}},
--{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, {RT}},
--{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, {RT}},
--{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, {RT}},
--{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, {RT}},
--{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, {RT}},
--{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, {RT}},
--{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, {RT}},
--{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, {RT}},
--{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, {RT}},
--{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, {RT}},
--{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, {RT}},
--{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, {RT}},
--{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, {RT}},
--{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, {RT}},
--{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, {RT}},
--{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, {RT}},
--{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, {RT}},
--{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, {RT}},
--{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, {RT}},
--{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, {RT}},
--{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, {RT}},
--{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, {RT}},
--{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, {RT}},
--{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, {RT}},
--{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, {RT}},
--{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, {RT}},
--{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, {RT}},
--{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE, {RT, SPR}},
--
--{"div", XO(31,331,0,0), XO_MASK, M601, {RT, RA, RB}},
--{"div.", XO(31,331,0,1), XO_MASK, M601, {RT, RA, RB}},
--
--{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, {RT, PMR}},
--
--{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, {RT}},
--{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, {RT}},
--{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, {RT}},
--{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, {RT}},
--{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, {RT}},
--{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, {RT}},
--{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, {RT}},
--{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, {RT}},
--{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, {RT}},
--{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, {RT}},
--{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, {RT}},
--{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, {RT}},
--{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, {RT}},
--{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, {RT}},
--{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, {RT}},
--{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, {RT}},
--{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, {RT}},
--{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, {RT}},
--{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, {RT}},
--{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, {RT}},
--{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, {RT}},
--{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, {RT}},
--{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, {RT}},
--{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, {RT}},
--{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, {RT}},
--{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, {RT}},
--{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, {RT}},
--{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, {RT}},
--{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, {RT}},
--{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, {RT}},
--{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, {RT}},
--{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, {RT}},
--{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, {RT}},
--{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, {RT}},
--{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, {RT}},
--{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, {RT}},
--{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, {RT}},
--{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, {RT}},
--{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, {RT}},
--{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, {RT}},
--{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, {RT, SPRG}},
--{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, {RT}},
--{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, {RT}},
--{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, {RT}},
--{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, {RT}},
--{"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, {RT}},
--{"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, {RT}},
--{"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, {RT}},
--{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, {RT}},
--{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, {RT}},
--{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, {RT}},
--{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, {RT}},
--{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, {RT}},
--{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, {RT}},
--{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, {RT}},
--{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, {RT}},
--{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, {RT}},
--{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, {RT}},
--{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, {RT}},
--{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, {RT}},
--{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, {RT}},
--{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, {RT}},
--{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, {RT}},
--{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, {RT}},
--{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, {RT}},
--{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, {RT}},
--{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, {RT}},
--{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, {RT}},
--{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, {RT}},
--{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, {RT}},
--{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, {RT}},
--{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, {RT}},
--{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, {RT}},
--{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, {RT}},
--{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, {RT}},
--{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, {RT}},
--{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, {RT}},
--{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, {RT}},
--{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, {RT}},
--{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, {RT}},
--{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, {RT}},
--{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, {RT}},
--{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, {RT}},
--{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, {RT}},
--{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, {RT}},
--{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, {RT}},
--{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, {RT}},
--{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, {RT}},
--{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, {RT}},
--{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, {RT}},
--{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, {RT, SPRBAT}},
--{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, {RT}},
--{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, {RT, SPRBAT}},
--{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, {RT}},
--{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, {RT}},
--{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, {RT, SPRBAT}},
--{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, {RT, SPRBAT}},
--{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, {RT}},
--{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, {RT}},
--{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, {RT}},
--{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, {RT}},
--{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, {RT}},
--{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, {RT}},
--{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, {RT}},
--{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, {RT}},
--{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, {RT}},
--{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, {RT}},
--{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, {RT}},
--{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, {RT}},
--{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, {RT}},
--{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, {RT}},
--{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, {RT}},
--{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, {RT}},
--{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, {RT}},
--{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, {RT}},
--{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, {RT}},
--{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, {RT}},
--{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, {RT}},
--{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, {RT}},
--{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, {RT}},
--{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, {RT}},
--{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, {RT}},
--{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, {RT}},
--{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, {RT}},
--{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, {RT}},
--{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, {RT}},
--{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, {RT}},
--{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, {RT}},
--{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, {RT}},
--{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, {RT}},
--{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, {RT}},
--{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, {RT}},
--{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, {RT}},
--{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, {RT}},
--{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, {RT}},
--{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, {RT}},
--{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, {RT}},
--{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, {RT}},
--{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, {RT}},
--{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, {RT}},
--{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, {RT}},
--{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, {RT}},
--{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, {RT}},
--{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, {RT}},
--{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, {RT}},
--{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, {RT}},
--{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, {RT}},
--{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, {RT}},
--{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, {RT}},
--{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, {RT}},
--{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, {RT}},
--{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, {RT}},
--{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, {RT}},
--{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, {RT}},
--{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, {RT}},
--{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, {RT}},
--{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, {RT}},
--{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, {RT}},
--{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, {RT}},
--{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, {RT}},
--{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, {RT}},
--{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, {RT}},
--{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, {RT}},
--{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, {RT}},
--{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, {RT}},
--{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, {RT}},
--{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, {RT}},
--{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, {RT}},
--{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, {RT}},
--{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, {RT}},
--{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, {RT}},
--{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, {RT}},
--{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, {RT}},
--{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, {RT}},
--{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, {RT}},
--{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, {RT}},
--{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, {RT}},
--{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, {RT}},
--{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, {RT}},
--{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, {RT}},
--{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, {RT}},
--{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, {RT}},
--{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, {RT}},
--{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, {RT}},
--{"mfspr", X(31,339), X_MASK, COM, {RT, SPR}},
--
--{"lwax", X(31,341), X_MASK, PPC64, {RT, RA0, RB}},
--
--{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, {RA, RB, STRM}},
--
--{"lhax", X(31,343), X_MASK, COM, {RT, RA0, RB}},
--
--{"lhaxe", X(31,351), X_MASK, BOOKE64, {RT, RA0, RB}},
--
--{"lvxl", X(31,359), X_MASK, PPCVEC, {VD, RA, RB}},
--
--{"abs", XO(31,360,0,0), XORB_MASK, M601, {RT, RA}},
--{"abs.", XO(31,360,0,1), XORB_MASK, M601, {RT, RA}},
--
--{"divs", XO(31,363,0,0), XO_MASK, M601, {RT, RA, RB}},
--{"divs.", XO(31,363,0,1), XO_MASK, M601, {RT, RA, RB}},
--
--{"tlbia", X(31,370), 0xffffffff, PPC, {0}},
--
--{"mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, {RT}},
--{"mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, {RT}},
--{"mftb", X(31,371), X_MASK, CLASSIC, {RT, TBR}},
--
--{"lwaux", X(31,373), X_MASK, PPC64, {RT, RAL, RB}},
--
--{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, {RA, RB, STRM}},
--
--{"lhaux", X(31,375), X_MASK, COM, {RT, RAL, RB}},
--
--{"lhauxe", X(31,383), X_MASK, BOOKE64, {RT, RAL, RB}},
--
--{"mtdcrx", X(31,387), X_MASK, BOOKE, {RA, RS}},
--
--{"dcblc", X(31,390), X_MASK, PPCCHLK, {CT, RA, RB}},
--{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, {RT, RA, RB}},
--
--{"adde64", XO(31,394,0,0), XO_MASK, BOOKE64, {RT, RA, RB}},
--
--{"dcblce", X(31,398), X_MASK, PPCCHLK64, {CT, RA, RB}},
--
--{"slbmte", X(31,402), XRA_MASK, PPC64, {RS, RB}},
--
--{"sthx", X(31,407), X_MASK, COM, {RS, RA0, RB}},
--
--{"orc", XRC(31,412,0), X_MASK, COM, {RA, RS, RB}},
--{"orc.", XRC(31,412,1), X_MASK, COM, {RA, RS, RB}},
--
--{"sthxe", X(31,415), X_MASK, BOOKE64, {RS, RA0, RB}},
--{"sthepx", X(31,415), X_MASK, E500MC, {RS, RA, RB}},
--
--{"mtdcrux", X(31,419), X_MASK, PPC464, {RA, RS}},
--
--{"slbie", X(31,434), XRTRA_MASK, PPC64, {RB}},
--
--{"ecowx", X(31,438), X_MASK, PPC, {RT, RA, RB}},
--
--{"sthux", X(31,439), X_MASK, COM, {RS, RAS, RB}},
--
--{"mdors", 0x7f9ce378, 0xffffffff, E500MC, {0}},
--
--{"mr", XRC(31,444,0), X_MASK, COM, {RA, RS, RBS}},
--{"or", XRC(31,444,0), X_MASK, COM, {RA, RS, RB}},
--{"mr.", XRC(31,444,1), X_MASK, COM, {RA, RS, RBS}},
--{"or.", XRC(31,444,1), X_MASK, COM, {RA, RS, RB}},
--
--{"sthuxe", X(31,447), X_MASK, BOOKE64, {RS, RAS, RB}},
--
--{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, {RS}},
--{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, {RS}},
--{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, {RS}},
--{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, {RS}},
--{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, {RS}},
--{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, {RS}},
--{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, {RS}},
--{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, {RS}},
--{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, {RS}},
--{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, {RS}},
--{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, {RS}},
--{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, {RS}},
--{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, {RS}},
--{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, {RS}},
--{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, {RS}},
--{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, {RS}},
--{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, {RS}},
--{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, {RS}},
--{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, {RS}},
--{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, {RS}},
--{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, {RS}},
--{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, {RS}},
--{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, {RS}},
--{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, {RS}},
--{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, {RS}},
--{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, {RS}},
--{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, {RS}},
--{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, {RS}},
--{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, {RS}},
--{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, {RS}},
--{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, {RS}},
--{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, {RS}},
--{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, {RS}},
--{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, {RS}},
--{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE, {SPR, RS}},
--
--{"dccci", X(31,454), XRT_MASK, PPC403|PPC440, {RA, RB}},
--
--{"subfze64", XO(31,456,0,0), XORB_MASK, BOOKE64, {RT, RA}},
--
--{"divdu", XO(31,457,0,0), XO_MASK, PPC64, {RT, RA, RB}},
--{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, {RT, RA, RB}},
--
--{"addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, {RT, RA}},
--
--{"divwu", XO(31,459,0,0), XO_MASK, PPC, {RT, RA, RB}},
--{"divwu.", XO(31,459,0,1), XO_MASK, PPC, {RT, RA, RB}},
--
--{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, {PMR, RS}},
--
--{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, {RS}},
--{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, {RS}},
--{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, {RS}},
--{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, {RS}},
--{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, {RS}},
--{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, {RS}},
--{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, {RS}},
--{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, {RS}},
--{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, {RS}},
--{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, {RS}},
--{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, {RS}},
--{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, {RS}},
--{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, {RS}},
--{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, {RS}},
--{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, {RS}},
--{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, {RS}},
--{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, {RS}},
--{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, {RS}},
--{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, {RS}},
--{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, {RS}},
--{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, {RS}},
--{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, {RS}},
--{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, {RS}},
--{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, {RS}},
--{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, {RS}},
--{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, {RS}},
--{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, {RS}},
--{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, {RS}},
--{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, {RS}},
--{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, {RS}},
--{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, {RS}},
--{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, {RS}},
--{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, {RS}},
--{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, {RS}},
--{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, {RS}},
--{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, {RS}},
--{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, {RS}},
--{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, {RS}},
--{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, {RS}},
--{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, {RS}},
--{"mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, {SPRG, RS}},
--{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, {RS}},
--{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, {RS}},
--{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, {RS}},
--{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, {RS}},
--{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, {RS}},
--{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, {RS}},
--{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, {RS}},
--{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, {RS}},
--{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, {RS}},
--{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, {RS}},
--{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, {RS}},
--{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, {RS}},
--{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, {RS}},
--{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, {RS}},
--{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, {RS}},
--{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, {RS}},
--{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, {RS}},
--{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, {RS}},
--{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, {RS}},
--{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, {RS}},
--{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, {RS}},
--{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, {RS}},
--{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, {RS}},
--{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, {RS}},
--{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, {RS}},
--{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, {RS}},
--{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, {RS}},
--{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, {RS}},
--{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, {RS}},
--{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, {RS}},
--{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, {RS}},
--{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, {RS}},
--{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, {RS}},
--{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, {RS}},
--{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, {RS}},
--{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, {RS}},
--{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, {RS}},
--{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, {RS}},
--{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, {RS}},
--{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, {RS}},
--{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, {RS}},
--{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, {RS}},
--{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, {RS}},
--{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, {RS}},
--{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, {RS}},
--{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, {RS}},
--{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, {SPRBAT, RS}},
--{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, {RS}},
--{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, {SPRBAT, RS}},
--{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, {RS}},
--{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, {RS}},
--{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, {SPRBAT, RS}},
--{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, {SPRBAT, RS}},
--{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, {RS}},
--{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, {RS}},
--{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, {RS}},
--{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, {RS}},
--{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, {RS}},
--{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, {RS}},
--{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, {RS}},
--{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, {RS}},
--{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, {RS}},
--{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, {RS}},
--{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, {RS}},
--{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, {RS}},
--{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, {RS}},
--{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, {RS}},
--{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, {RS}},
--{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, {RS}},
--{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, {RS}},
--{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, {RS}},
--{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, {RS}},
--{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, {RS}},
--{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, {RS}},
--{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, {RS}},
--{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, {RS}},
--{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, {RS}},
--{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, {RS}},
--{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, {RS}},
--{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, {RS}},
--{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, {RS}},
--{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, {RS}},
--{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, {RS}},
--{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, {RS}},
--{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, {RS}},
--{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, {RS}},
--{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, {RS}},
--{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, {RS}},
--{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, {RS}},
--{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, {RS}},
--{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, {RS}},
--{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, {RS}},
--{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, {RS}},
--{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, {RS}},
--{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, {RS}},
--{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, {RS}},
--{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, {RS}},
--{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, {RS}},
--{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, {RS}},
--{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, {RS}},
--{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, {RS}},
--{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, {RS}},
--{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, {RS}},
--{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, {RS}},
--{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, {RS}},
--{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, {RS}},
--{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, {RS}},
--{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, {RS}},
--{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, {RS}},
--{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, {RS}},
--{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, {RS}},
--{"mtspr", X(31,467), X_MASK, COM, {SPR, RS}},
--
--{"dcbi", X(31,470), XRT_MASK, PPC, {RA, RB}},
--
--{"nand", XRC(31,476,0), X_MASK, COM, {RA, RS, RB}},
--{"nand.", XRC(31,476,1), X_MASK, COM, {RA, RS, RB}},
--
--{"dcbie", X(31,478), XRT_MASK, BOOKE64, {RA, RB}},
--
--{"dsn", X(31,483), XRT_MASK, E500MC, {RA, RB}},
--
--{"dcread", X(31,486), X_MASK, PPC403|PPC440, {RT, RA, RB}},
--
--{"icbtls", X(31,486), X_MASK, PPCCHLK, {CT, RA, RB}},
--
--{"stvxl", X(31,487), X_MASK, PPCVEC, {VS, RA, RB}},
--
--{"nabs", XO(31,488,0,0), XORB_MASK, M601, {RT, RA}},
--{"subfme64", XO(31,488,0,0), XORB_MASK, BOOKE64, {RT, RA}},
--{"nabs.", XO(31,488,0,1), XORB_MASK, M601, {RT, RA}},
--
--{"divd", XO(31,489,0,0), XO_MASK, PPC64, {RT, RA, RB}},
--{"divd.", XO(31,489,0,1), XO_MASK, PPC64, {RT, RA, RB}},
--
--{"addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, {RT, RA}},
--
--{"divw", XO(31,491,0,0), XO_MASK, PPC, {RT, RA, RB}},
--{"divw.", XO(31,491,0,1), XO_MASK, PPC, {RT, RA, RB}},
--
--{"icbtlse", X(31,494), X_MASK, PPCCHLK64, {CT, RA, RB}},
--
--{"slbia", X(31,498), 0xffffffff, PPC64, {0}},
--
--{"cli", X(31,502), XRB_MASK, POWER, {RT, RA}},
--
--{"cmpb", X(31,508), X_MASK, POWER6, {RA, RS, RB}},
--
--{"stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, {RS, RA, RB}},
--
--{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, {BF}},
--
--{"lbdx", X(31,515), X_MASK, E500MC, {RT, RA, RB}},
--
--{"bblels", X(31,518), X_MASK, PPCBRLK, {0}},
--
--{"lvlx", X(31,519), X_MASK, CELL, {VD, RA0, RB}},
--{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
--{"subco", XO(31,8,1,0), XO_MASK, PPC, {RT, RB, RA}},
--{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
--{"subco.", XO(31,8,1,1), XO_MASK, PPC, {RT, RB, RA}},
--
--{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
--{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
--
--{"clcs", X(31,531), XRB_MASK, M601, {RT, RA}},
--
--{"ldbrx", X(31,532), X_MASK, CELL, {RT, RA0, RB}},
--
--{"lswx", X(31,533), X_MASK, PPCCOM, {RT, RA0, RB}},
--{"lsx", X(31,533), X_MASK, PWRCOM, {RT, RA, RB}},
--
--{"lwbrx", X(31,534), X_MASK, PPCCOM, {RT, RA0, RB}},
--{"lbrx", X(31,534), X_MASK, PWRCOM, {RT, RA, RB}},
--
--{"lfsx", X(31,535), X_MASK, COM, {FRT, RA0, RB}},
--
--{"srw", XRC(31,536,0), X_MASK, PPCCOM, {RA, RS, RB}},
--{"sr", XRC(31,536,0), X_MASK, PWRCOM, {RA, RS, RB}},
--{"srw.", XRC(31,536,1), X_MASK, PPCCOM, {RA, RS, RB}},
--{"sr.", XRC(31,536,1), X_MASK, PWRCOM, {RA, RS, RB}},
--
--{"rrib", XRC(31,537,0), X_MASK, M601, {RA, RS, RB}},
--{"rrib.", XRC(31,537,1), X_MASK, M601, {RA, RS, RB}},
--
--{"srd", XRC(31,539,0), X_MASK, PPC64, {RA, RS, RB}},
--{"srd.", XRC(31,539,1), X_MASK, PPC64, {RA, RS, RB}},
--
--{"maskir", XRC(31,541,0), X_MASK, M601, {RA, RS, RB}},
--{"maskir.", XRC(31,541,1), X_MASK, M601, {RA, RS, RB}},
--
--{"lwbrxe", X(31,542), X_MASK, BOOKE64, {RT, RA0, RB}},
--
--{"lfsxe", X(31,543), X_MASK, BOOKE64, {FRT, RA0, RB}},
--
--{"mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, {BF}},
--
--{"lhdx", X(31,547), X_MASK, E500MC, {RT, RA, RB}},
--
--{"bbelr", X(31,550), X_MASK, PPCBRLK, {0}},
--
--{"lvrx", X(31,551), X_MASK, CELL, {VD, RA0, RB}},
--{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"subfo", XO(31,40,1,0), XO_MASK, PPC, {RT, RA, RB}},
--{"subo", XO(31,40,1,0), XO_MASK, PPC, {RT, RB, RA}},
--{"subfo.", XO(31,40,1,1), XO_MASK, PPC, {RT, RA, RB}},
--{"subo.", XO(31,40,1,1), XO_MASK, PPC, {RT, RB, RA}},
--
--{"tlbsync", X(31,566), 0xffffffff, PPC, {0}},
--
--{"lfsux", X(31,567), X_MASK, COM, {FRT, RAS, RB}},
--
--{"lfsuxe", X(31,575), X_MASK, BOOKE64, {FRT, RAS, RB}},
--
--{"lwdx", X(31,579), X_MASK, E500MC, {RT, RA, RB}},
--
--{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"mfsr", X(31,595), XRB_MASK|(1<<20), COM32, {RT, SR}},
--
--{"lswi", X(31,597), X_MASK, PPCCOM, {RT, RA0, NB}},
--{"lsi", X(31,597), X_MASK, PWRCOM, {RT, RA0, NB}},
--
--{"msync", X(31,598), 0xffffffff, BOOKE, {0}},
--{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, {0}},
--{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, {0}},
--{"sync", X(31,598), XSYNC_MASK, PPCCOM, {LS}},
--{"dcs", X(31,598), 0xffffffff, PWRCOM, {0}},
--
--{"lfdx", X(31,599), X_MASK, COM, {FRT, RA0, RB}},
--
--{"lfdxe", X(31,607), X_MASK, BOOKE64, {FRT, RA0, RB}},
--{"lfdepx", X(31,607), X_MASK, E500MC, {RT, RA, RB}},
--{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, {FRT, RB}},
--
--{"lddx", X(31,611), X_MASK, E500MC, {RT, RA, RB}},
--
--{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"nego", XO(31,104,1,0), XORB_MASK, COM, {RT, RA}},
--{"nego.", XO(31,104,1,1), XORB_MASK, COM, {RT, RA}},
--
--{"mulo", XO(31,107,1,0), XO_MASK, M601, {RT, RA, RB}},
--{"mulo.", XO(31,107,1,1), XO_MASK, M601, {RT, RA, RB}},
--
--{"mfsri", X(31,627), X_MASK, PWRCOM, {RT, RA, RB}},
--
--{"dclst", X(31,630), XRB_MASK, PWRCOM, {RS, RA}},
--
--{"lfdux", X(31,631), X_MASK, COM, {FRT, RAS, RB}},
--
--{"lfduxe", X(31,639), X_MASK, BOOKE64, {FRT, RAS, RB}},
--
--{"stbdx", X(31,643), X_MASK, E500MC, {RS, RA, RB}},
--
--{"stvlx", X(31,647), X_MASK, CELL, {VS, RA0, RB}},
--{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
--{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
--
--{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
--{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
--
--{"mfsrin", X(31,659), XRA_MASK, PPC32, {RT, RB}},
--
--{"stdbrx", X(31,660), X_MASK, CELL, {RS, RA0, RB}},
--
--{"stswx", X(31,661), X_MASK, PPCCOM, {RS, RA0, RB}},
--{"stsx", X(31,661), X_MASK, PWRCOM, {RS, RA0, RB}},
--
--{"stwbrx", X(31,662), X_MASK, PPCCOM, {RS, RA0, RB}},
--{"stbrx", X(31,662), X_MASK, PWRCOM, {RS, RA0, RB}},
--
--{"stfsx", X(31,663), X_MASK, COM, {FRS, RA0, RB}},
--
--{"srq", XRC(31,664,0), X_MASK, M601, {RA, RS, RB}},
--{"srq.", XRC(31,664,1), X_MASK, M601, {RA, RS, RB}},
--
--{"sre", XRC(31,665,0), X_MASK, M601, {RA, RS, RB}},
--{"sre.", XRC(31,665,1), X_MASK, M601, {RA, RS, RB}},
--
--{"stwbrxe", X(31,670), X_MASK, BOOKE64, {RS, RA0, RB}},
--
--{"stfsxe", X(31,671), X_MASK, BOOKE64, {FRS, RA0, RB}},
--
--{"sthdx", X(31,675), X_MASK, E500MC, {RS, RA, RB}},
--
--{"stvrx", X(31,679), X_MASK, CELL, {VS, RA0, RB}},
--{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"stfsux", X(31,695), X_MASK, COM, {FRS, RAS, RB}},
--
--{"sriq", XRC(31,696,0), X_MASK, M601, {RA, RS, SH}},
--{"sriq.", XRC(31,696,1), X_MASK, M601, {RA, RS, SH}},
--
--{"stfsuxe", X(31,703), X_MASK, BOOKE64, {FRS, RAS, RB}},
--
--{"stwdx", X(31,707), X_MASK, E500MC, {RS, RA, RB}},
--
--{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, {RT, RA}},
--{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, {RT, RA}},
--{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, {RT, RA}},
--{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, {RT, RA}},
--
--{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, {RT, RA}},
--{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, {RT, RA}},
--{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, {RT, RA}},
--{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, {RT, RA}},
--
--{"stswi", X(31,725), X_MASK, PPCCOM, {RS, RA0, NB}},
--{"stsi", X(31,725), X_MASK, PWRCOM, {RS, RA0, NB}},
--
--{"stfdx", X(31,727), X_MASK, COM, {FRS, RA0, RB}},
--
--{"srlq", XRC(31,728,0), X_MASK, M601, {RA, RS, RB}},
--{"srlq.", XRC(31,728,1), X_MASK, M601, {RA, RS, RB}},
--
--{"sreq", XRC(31,729,0), X_MASK, M601, {RA, RS, RB}},
--{"sreq.", XRC(31,729,1), X_MASK, M601, {RA, RS, RB}},
--
--{"stfdxe", X(31,735), X_MASK, BOOKE64, {FRS, RA0, RB}},
--{"stfdepx", X(31,735), X_MASK, E500MC, {RS, RA, RB}},
--{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, {RT, FRB}},
--
--{"stddx", X(31,739), X_MASK, E500MC, {RS, RA, RB}},
--
--{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, {RT, RA}},
--{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, {RT, RA}},
--{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, {RT, RA}},
--{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, {RT, RA}},
--
--{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, {RT, RA, RB}},
--{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, {RT, RA, RB}},
--
--{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, {RT, RA}},
--{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, {RT, RA}},
--{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, {RT, RA}},
--{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, {RT, RA}},
--
--{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
--{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
--
--{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE, {RA, RB}},
--{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, {RA, RB}},
--
--{"stfdux", X(31,759), X_MASK, COM, {FRS, RAS, RB}},
--
--{"srliq", XRC(31,760,0), X_MASK, M601, {RA, RS, SH}},
--{"srliq.", XRC(31,760,1), X_MASK, M601, {RA, RS, SH}},
--
--{"dcbae", X(31,766), XRT_MASK, BOOKE64, {RA, RB}},
--
--{"stfduxe", X(31,767), X_MASK, BOOKE64, {FRS, RAS, RB}},
--
--{"lvlxl", X(31,775), X_MASK, CELL, {VD, RA0, RB}},
--{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"dozo", XO(31,264,1,0), XO_MASK, M601, {RT, RA, RB}},
--{"dozo.", XO(31,264,1,1), XO_MASK, M601, {RT, RA, RB}},
--
--{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
--{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
--{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
--
--{"tlbivax", X(31,786), XRT_MASK, BOOKE, {RA, RB}},
--{"tlbivaxe", X(31,787), XRT_MASK, BOOKE64, {RA, RB}},
--{"tlbilx", X(31,787), X_MASK, E500MC, {T, RA0, RB}},
--{"tlbilxlpid", XTO(31,787,0), XTO_MASK, E500MC, {0}},
--{"tlbilxpid", XTO(31,787,1), XTO_MASK, E500MC, {0}},
--{"tlbilxva", XTO(31,787,3), XTO_MASK, E500MC, {RA0, RB}},
--
--{"lwzcix", X(31,789), X_MASK, POWER6, {RT, RA0, RB}},
--
--{"lhbrx", X(31,790), X_MASK, COM, {RT, RA0, RB}},
--
--{"lfqx", X(31,791), X_MASK, POWER2, {FRT, RA, RB}},
--{"lfdpx", X(31,791), X_MASK, POWER6, {FRT, RA, RB}},
--
--{"sraw", XRC(31,792,0), X_MASK, PPCCOM, {RA, RS, RB}},
--{"sra", XRC(31,792,0), X_MASK, PWRCOM, {RA, RS, RB}},
--{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, {RA, RS, RB}},
--{"sra.", XRC(31,792,1), X_MASK, PWRCOM, {RA, RS, RB}},
--
--{"srad", XRC(31,794,0), X_MASK, PPC64, {RA, RS, RB}},
--{"srad.", XRC(31,794,1), X_MASK, PPC64, {RA, RS, RB}},
--
--{"lhbrxe", X(31,798), X_MASK, BOOKE64, {RT, RA0, RB}},
--
--{"ldxe", X(31,799), X_MASK, BOOKE64, {RT, RA0, RB}},
--
--{"lfddx", X(31,803), X_MASK, E500MC, {FRT, RA, RB}},
--
--{"lvrxl", X(31,807), X_MASK, CELL, {VD, RA0, RB}},
--
--{"rac", X(31,818), X_MASK, PWRCOM, {RT, RA, RB}},
--
--{"lhzcix", X(31,821), X_MASK, POWER6, {RT, RA0, RB}},
--
--{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, {STRM}},
--
--{"lfqux", X(31,823), X_MASK, POWER2, {FRT, RA, RB}},
--
--{"srawi", XRC(31,824,0), X_MASK, PPCCOM, {RA, RS, SH}},
--{"srai", XRC(31,824,0), X_MASK, PWRCOM, {RA, RS, SH}},
--{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, {RA, RS, SH}},
--{"srai.", XRC(31,824,1), X_MASK, PWRCOM, {RA, RS, SH}},
--
--{"sradi", XS(31,413,0), XS_MASK, PPC64, {RA, RS, SH6}},
--{"sradi.", XS(31,413,1), XS_MASK, PPC64, {RA, RS, SH6}},
--
--{"divo", XO(31,331,1,0), XO_MASK, M601, {RT, RA, RB}},
--{"divo.", XO(31,331,1,1), XO_MASK, M601, {RT, RA, RB}},
--{"lduxe", X(31,831), X_MASK, BOOKE64, {RT, RA0, RB}},
--
--{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, {XT6, RA, RB}},
--
--{"slbmfev", X(31,851), XRA_MASK, PPC64, {RT, RB}},
--
--{"lbzcix", X(31,853), X_MASK, POWER6, {RT, RA0, RB}},
--
--{"mbar", X(31,854), X_MASK, BOOKE, {MO}},
--{"eieio", X(31,854), 0xffffffff, PPC, {0}},
--
--{"lfiwax", X(31,855), X_MASK, POWER6, {FRT, RA0, RB}},
--
--{"abso", XO(31,360,1,0), XORB_MASK, M601, {RT, RA}},
--{"abso.", XO(31,360,1,1), XORB_MASK, M601, {RT, RA}},
--
--{"divso", XO(31,363,1,0), XO_MASK, M601, {RT, RA, RB}},
--{"divso.", XO(31,363,1,1), XO_MASK, M601, {RT, RA, RB}},
--
--{"lxvd2ux", X(31,876), XX1_MASK, PPCVSX, {XT6, RA, RB}},
--
--{"ldcix", X(31,885), X_MASK, POWER6, {RT, RA0, RB}},
--
--{"stvlxl", X(31,903), X_MASK, CELL, {VS, RA0, RB}},
--{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, {FCRT, RA, RB}},
--
--{"subfe64o", XO(31,392,1,0), XO_MASK, BOOKE64, {RT, RA, RB}},
--
--{"adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, {RT, RA, RB}},
--
--{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, {RTO, RA, RB}},
--{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, {RTO, RA, RB}},
--
--{"tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, {RTO, RA, RB}},
--{"tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, {RTO, RA, RB}},
--{"slbmfee", X(31,915), XRA_MASK, PPC64, {RT, RB}},
--
--{"stwcix", X(31,917), X_MASK, POWER6, {RS, RA0, RB}},
--
--{"sthbrx", X(31,918), X_MASK, COM, {RS, RA0, RB}},
--
--{"stfqx", X(31,919), X_MASK, POWER2, {FRS, RA, RB}},
--{"stfdpx", X(31,919), X_MASK, POWER6, {FRS, RA, RB}},
--
--{"sraq", XRC(31,920,0), X_MASK, M601, {RA, RS, RB}},
--{"sraq.", XRC(31,920,1), X_MASK, M601, {RA, RS, RB}},
--
--{"srea", XRC(31,921,0), X_MASK, M601, {RA, RS, RB}},
--{"srea.", XRC(31,921,1), X_MASK, M601, {RA, RS, RB}},
--
--{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, {RA, RS}},
--{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, {RA, RS}},
--{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, {RA, RS}},
--{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, {RA, RS}},
--
--{"sthbrxe", X(31,926), X_MASK, BOOKE64, {RS, RA0, RB}},
--
--{"stdxe", X(31,927), X_MASK, BOOKE64, {RS, RA0, RB}},
--
--{"stfddx", X(31,931), X_MASK, E500MC, {FRS, RA, RB}},
--
--{"stvrxl", X(31,935), X_MASK, CELL, {VS, RA0, RB}},
--
--{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, {RT, RA}},
--{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, {RT, RA}},
--{"tlbre", X(31,946), X_MASK, PPC403|BOOKE, {RSO, RAOPT, SHO}},
--
--{"sthcix", X(31,949), X_MASK, POWER6, {RS, RA0, RB}},
--
--{"stfqux", X(31,951), X_MASK, POWER2, {FRS, RA, RB}},
--
--{"sraiq", XRC(31,952,0), X_MASK, M601, {RA, RS, SH}},
--{"sraiq.", XRC(31,952,1), X_MASK, M601, {RA, RS, SH}},
--
--{"extsb", XRC(31,954,0), XRB_MASK, PPC, {RA, RS}},
--{"extsb.", XRC(31,954,1), XRB_MASK, PPC, {RA, RS}},
--
--{"stduxe", X(31,959), X_MASK, BOOKE64, {RS, RAS, RB}},
--
--{"iccci", X(31,966), XRT_MASK, PPC403|PPC440, {RA, RB}},
--
--{"subfze64o", XO(31,456,1,0), XORB_MASK, BOOKE64, {RT, RA}},
--
--{"divduo", XO(31,457,1,0), XO_MASK, PPC64, {RT, RA, RB}},
--{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, {RT, RA, RB}},
--
--{"addze64o", XO(31,458,1,0), XORB_MASK, BOOKE64, {RT, RA}},
--
--{"divwuo", XO(31,459,1,0), XO_MASK, PPC, {RT, RA, RB}},
--{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, {RT, RA, RB}},
--
--{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, {XS6, RA, RB}},
--
--{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, {RT, RA}},
--{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, {RT, RA}},
--{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE, {RSO, RAOPT, SHO}},
--{"tlbld", X(31,978), XRTRA_MASK, PPC, {RB}},
--
--{"stbcix", X(31,981), X_MASK, POWER6, {RS, RA0, RB}},
--
--{"icbi", X(31,982), XRT_MASK, PPC, {RA, RB}},
--
--{"stfiwx", X(31,983), X_MASK, PPC, {FRS, RA0, RB}},
--
--{"extsw", XRC(31,986,0), XRB_MASK, PPC64|BOOKE64, {RA, RS}},
--{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, {RA, RS}},
--
--{"icbie", X(31,990), XRT_MASK, BOOKE64, {RA, RB}},
--{"stfiwxe", X(31,991), X_MASK, BOOKE64, {FRS, RA0, RB}},
--
--{"icbiep", XRT(31,991,0), XRT_MASK, E500MC, {RA, RB}},
--
--{"icread", X(31,998), XRT_MASK, PPC403|PPC440, {RA, RB}},
--
--{"nabso", XO(31,488,1,0), XORB_MASK, M601, {RT, RA}},
--{"subfme64o", XO(31,488,1,0), XORB_MASK, BOOKE64, {RT, RA}},
--{"nabso.", XO(31,488,1,1), XORB_MASK, M601, {RT, RA}},
--
--{"divdo", XO(31,489,1,0), XO_MASK, PPC64, {RT, RA, RB}},
--{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, {RT, RA, RB}},
--
--{"addme64o", XO(31,490,1,0), XORB_MASK, BOOKE64, {RT, RA}},
--
--{"divwo", XO(31,491,1,0), XO_MASK, PPC, {RT, RA, RB}},
--{"divwo.", XO(31,491,1,1), XO_MASK, PPC, {RT, RA, RB}},
--
--{"stxvd2ux", X(31,1004), XX1_MASK, PPCVSX, {XS6, RA, RB}},
--
--{"tlbli", X(31,1010), XRTRA_MASK, PPC, {RB}},
--
--{"stdcix", X(31,1013), X_MASK, POWER6, {RS, RA0, RB}},
--
--{"dcbz", X(31,1014), XRT_MASK, PPC, {RA, RB}},
--{"dclz", X(31,1014), XRT_MASK, PPC, {RA, RB}},
--
--{"dcbze", X(31,1022), XRT_MASK, BOOKE64, {RA, RB}},
--{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC, {RA, RB}},
--
--{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4, {RA, RB}},
--{"dcbzl", XOPL(31,1014,1), XRT_MASK, NOPOWER4|E500MC,{RA, RB}},
--
--{"cctpl", 0x7c210b78, 0xffffffff, CELL, {0}},
--{"cctpm", 0x7c421378, 0xffffffff, CELL, {0}},
--{"cctph", 0x7c631b78, 0xffffffff, CELL, {0}},
--
--{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, {RA, RB, STRM}},
--{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, {RA, RB, STRM}},
--{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, {0}},
--
--{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, {0}},
--{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, {0}},
--{"db12cyc", 0x7fdef378, 0xffffffff, CELL, {0}},
--{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, {0}},
--
--{"lwz", OP(32), OP_MASK, PPCCOM, {RT, D, RA0}},
--{"l", OP(32), OP_MASK, PWRCOM, {RT, D, RA0}},
--
--{"lwzu", OP(33), OP_MASK, PPCCOM, {RT, D, RAL}},
--{"lu", OP(33), OP_MASK, PWRCOM, {RT, D, RA0}},
--
--{"lbz", OP(34), OP_MASK, COM, {RT, D, RA0}},
--
--{"lbzu", OP(35), OP_MASK, COM, {RT, D, RAL}},
--
--{"stw", OP(36), OP_MASK, PPCCOM, {RS, D, RA0}},
--{"st", OP(36), OP_MASK, PWRCOM, {RS, D, RA0}},
--
--{"stwu", OP(37), OP_MASK, PPCCOM, {RS, D, RAS}},
--{"stu", OP(37), OP_MASK, PWRCOM, {RS, D, RA0}},
--
--{"stb", OP(38), OP_MASK, COM, {RS, D, RA0}},
--
--{"stbu", OP(39), OP_MASK, COM, {RS, D, RAS}},
--
--{"lhz", OP(40), OP_MASK, COM, {RT, D, RA0}},
--
--{"lhzu", OP(41), OP_MASK, COM, {RT, D, RAL}},
--
--{"lha", OP(42), OP_MASK, COM, {RT, D, RA0}},
--
--{"lhau", OP(43), OP_MASK, COM, {RT, D, RAL}},
--
--{"sth", OP(44), OP_MASK, COM, {RS, D, RA0}},
--
--{"sthu", OP(45), OP_MASK, COM, {RS, D, RAS}},
--
--{"lmw", OP(46), OP_MASK, PPCCOM, {RT, D, RAM}},
--{"lm", OP(46), OP_MASK, PWRCOM, {RT, D, RA0}},
--
--{"stmw", OP(47), OP_MASK, PPCCOM, {RS, D, RA0}},
--{"stm", OP(47), OP_MASK, PWRCOM, {RS, D, RA0}},
--
--{"lfs", OP(48), OP_MASK, COM, {FRT, D, RA0}},
--
--{"lfsu", OP(49), OP_MASK, COM, {FRT, D, RAS}},
--
--{"lfd", OP(50), OP_MASK, COM, {FRT, D, RA0}},
--
--{"lfdu", OP(51), OP_MASK, COM, {FRT, D, RAS}},
--
--{"stfs", OP(52), OP_MASK, COM, {FRS, D, RA0}},
--
--{"stfsu", OP(53), OP_MASK, COM, {FRS, D, RAS}},
--
--{"stfd", OP(54), OP_MASK, COM, {FRS, D, RA0}},
--
--{"stfdu", OP(55), OP_MASK, COM, {FRS, D, RAS}},
--
--{"lq", OP(56), OP_MASK, POWER4, {RTQ, DQ, RAQ}},
--
--{"lfq", OP(56), OP_MASK, POWER2, {FRT, D, RA0}},
--
--{"psq_l", OP(56), OP_MASK, PPCPS, {FRT,PSD,RA,PSW,PSQ}},
--
--{"lfqu", OP(57), OP_MASK, POWER2, {FRT, D, RA0}},
--
--{"psq_lu", OP(57), OP_MASK, PPCPS, {FRT,PSD,RA,PSW,PSQ}},
--
--{"lfdp", OP(57), OP_MASK, POWER6, {FRT, D, RA0}},
--
--{"lbze", DEO(58,0), DE_MASK, BOOKE64, {RT, DE, RA0}},
--{"lbzue", DEO(58,1), DE_MASK, BOOKE64, {RT, DE, RAL}},
--{"lhze", DEO(58,2), DE_MASK, BOOKE64, {RT, DE, RA0}},
--{"lhzue", DEO(58,3), DE_MASK, BOOKE64, {RT, DE, RAL}},
--{"lhae", DEO(58,4), DE_MASK, BOOKE64, {RT, DE, RA0}},
--{"lhaue", DEO(58,5), DE_MASK, BOOKE64, {RT, DE, RAL}},
--{"lwze", DEO(58,6), DE_MASK, BOOKE64, {RT, DE, RA0}},
--{"lwzue", DEO(58,7), DE_MASK, BOOKE64, {RT, DE, RAL}},
--{"stbe", DEO(58,8), DE_MASK, BOOKE64, {RS, DE, RA0}},
--{"stbue", DEO(58,9), DE_MASK, BOOKE64, {RS, DE, RAS}},
--{"sthe", DEO(58,10), DE_MASK, BOOKE64, {RS, DE, RA0}},
--{"sthue", DEO(58,11), DE_MASK, BOOKE64, {RS, DE, RAS}},
--{"stwe", DEO(58,14), DE_MASK, BOOKE64, {RS, DE, RA0}},
--{"stwue", DEO(58,15), DE_MASK, BOOKE64, {RS, DE, RAS}},
--
--{"ld", DSO(58,0), DS_MASK, PPC64, {RT, DS, RA0}},
--{"ldu", DSO(58,1), DS_MASK, PPC64, {RT, DS, RAL}},
--{"lwa", DSO(58,2), DS_MASK, PPC64, {RT, DS, RA0}},
--
--{"dadd", XRC(59,2,0), X_MASK, POWER6, {FRT, FRA, FRB}},
--{"dadd.", XRC(59,2,1), X_MASK, POWER6, {FRT, FRA, FRB}},
--
--{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, {FRT,FRA,FRB,RMC}},
--{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, {FRT,FRA,FRB,RMC}},
--
--{"fdivs", A(59,18,0), AFRC_MASK, PPC, {FRT, FRA, FRB}},
--{"fdivs.", A(59,18,1), AFRC_MASK, PPC, {FRT, FRA, FRB}},
--
--{"fsubs", A(59,20,0), AFRC_MASK, PPC, {FRT, FRA, FRB}},
--{"fsubs.", A(59,20,1), AFRC_MASK, PPC, {FRT, FRA, FRB}},
--
--{"fadds", A(59,21,0), AFRC_MASK, PPC, {FRT, FRA, FRB}},
--{"fadds.", A(59,21,1), AFRC_MASK, PPC, {FRT, FRA, FRB}},
--
--{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, {FRT, FRB}},
--{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, {FRT, FRB}},
--
--{"fres", A(59,24,0), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}},
--{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}},
--
--{"fmuls", A(59,25,0), AFRB_MASK, PPC, {FRT, FRA, FRC}},
--{"fmuls.", A(59,25,1), AFRB_MASK, PPC, {FRT, FRA, FRC}},
--
--{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}},
--{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}},
--
--{"fmsubs", A(59,28,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
--{"fmsubs.", A(59,28,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
--
--{"fmadds", A(59,29,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
--{"fmadds.", A(59,29,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
--
--{"fnmsubs", A(59,30,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
--{"fnmsubs.", A(59,30,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
--
--{"fnmadds", A(59,31,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
--{"fnmadds.", A(59,31,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
--
--{"dmul", XRC(59,34,0), X_MASK, POWER6, {FRT, FRA, FRB}},
--{"dmul.", XRC(59,34,1), X_MASK, POWER6, {FRT, FRA, FRB}},
--
--{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
--{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
--
--{"dscli", ZRC(59,66,0), Z_MASK, POWER6, {FRT, FRA, SH16}},
--{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, {FRT, FRA, SH16}},
--
--{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, {TE, FRT,FRB,RMC}},
--{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, {TE, FRT,FRB,RMC}},
--
--{"dscri", ZRC(59,98,0), Z_MASK, POWER6, {FRT, FRA, SH16}},
--{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, {FRT, FRA, SH16}},
--
--{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
--{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
--
--{"dcmpo", X(59,130), X_MASK, POWER6, {BF, FRA, FRB}},
--
--{"dtstex", X(59,162), X_MASK, POWER6, {BF, FRA, FRB}},
--{"dtstdc", Z(59,194), Z_MASK, POWER6, {BF, FRA, DCM}},
--{"dtstdg", Z(59,226), Z_MASK, POWER6, {BF, FRA, DGM}},
--
--{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
--{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
--
--{"dctdp", XRC(59,258,0), X_MASK, POWER6, {FRT, FRB}},
--{"dctdp.", XRC(59,258,1), X_MASK, POWER6, {FRT, FRB}},
--
--{"dctfix", XRC(59,290,0), X_MASK, POWER6, {FRT, FRB}},
--{"dctfix.", XRC(59,290,1), X_MASK, POWER6, {FRT, FRB}},
--
--{"ddedpd", XRC(59,322,0), X_MASK, POWER6, {SP, FRT, FRB}},
--{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, {SP, FRT, FRB}},
--
--{"dxex", XRC(59,354,0), X_MASK, POWER6, {FRT, FRB}},
--{"dxex.", XRC(59,354,1), X_MASK, POWER6, {FRT, FRB}},
--
--{"dsub", XRC(59,514,0), X_MASK, POWER6, {FRT, FRA, FRB}},
--{"dsub.", XRC(59,514,1), X_MASK, POWER6, {FRT, FRA, FRB}},
--
--{"ddiv", XRC(59,546,0), X_MASK, POWER6, {FRT, FRA, FRB}},
--{"ddiv.", XRC(59,546,1), X_MASK, POWER6, {FRT, FRA, FRB}},
--
--{"dcmpu", X(59,642), X_MASK, POWER6, {BF, FRA, FRB}},
--
--{"dtstsf", X(59,674), X_MASK, POWER6, {BF, FRA, FRB}},
--
--{"drsp", XRC(59,770,0), X_MASK, POWER6, {FRT, FRB}},
--{"drsp.", XRC(59,770,1), X_MASK, POWER6, {FRT, FRB}},
--
--{"denbcd", XRC(59,834,0), X_MASK, POWER6, {S, FRT, FRB}},
--{"denbcd.", XRC(59,834,1), X_MASK, POWER6, {S, FRT, FRB}},
--
--{"diex", XRC(59,866,0), X_MASK, POWER6, {FRT, FRA, FRB}},
--{"diex.", XRC(59,866,1), X_MASK, POWER6, {FRT, FRA, FRB}},
--
--{"stfq", OP(60), OP_MASK, POWER2, {FRS, D, RA}},
--
--{"psq_st", OP(60), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}},
--
--{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, {XT6, XA6, XB6}},
--{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, {XT6, XA6, XB6}},
--{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, {XT6, XA6, XB6, DM}},
--{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, {XT6, XA6, XB6S}},
--{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, {XT6, XA6, XB6}},
--
--{"psq_stu", OP(61), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}},
--
--{"stfqu", OP(61), OP_MASK, POWER2, {FRS, D, RA}},
--
--{"stfdp", OP(61), OP_MASK, POWER6, {FRT, D, RA0}},
--
--{"lde", DEO(62,0), DE_MASK, BOOKE64, {RT, DES, RA0}},
--{"ldue", DEO(62,1), DE_MASK, BOOKE64, {RT, DES, RA0}},
--{"lfse", DEO(62,4), DE_MASK, BOOKE64, {FRT, DES, RA0}},
--{"lfsue", DEO(62,5), DE_MASK, BOOKE64, {FRT, DES, RAS}},
--{"lfde", DEO(62,6), DE_MASK, BOOKE64, {FRT, DES, RA0}},
--{"lfdue", DEO(62,7), DE_MASK, BOOKE64, {FRT, DES, RAS}},
--{"stde", DEO(62,8), DE_MASK, BOOKE64, {RS, DES, RA0}},
--{"stdue", DEO(62,9), DE_MASK, BOOKE64, {RS, DES, RAS}},
--{"stfse", DEO(62,12), DE_MASK, BOOKE64, {FRS, DES, RA0}},
--{"stfsue", DEO(62,13), DE_MASK, BOOKE64, {FRS, DES, RAS}},
--{"stfde", DEO(62,14), DE_MASK, BOOKE64, {FRS, DES, RA0}},
--{"stfdue", DEO(62,15), DE_MASK, BOOKE64, {FRS, DES, RAS}},
--
--{"std", DSO(62,0), DS_MASK, PPC64, {RS, DS, RA0}},
--{"stdu", DSO(62,1), DS_MASK, PPC64, {RS, DS, RAS}},
--{"stq", DSO(62,2), DS_MASK, POWER4, {RSQ, DS, RA0}},
--
--{"fcmpu", X(63,0), X_MASK|(3<<21), COM, {BF, FRA, FRB}},
--
--{"daddq", XRC(63,2,0), X_MASK, POWER6, {FRT, FRA, FRB}},
--{"daddq.", XRC(63,2,1), X_MASK, POWER6, {FRT, FRA, FRB}},
--
--{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
--{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
--
--{"fcpsgn", XRC(63,8,0), X_MASK, POWER6, {FRT, FRA, FRB}},
--{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6, {FRT, FRA, FRB}},
--
--{"frsp", XRC(63,12,0), XRA_MASK, COM, {FRT, FRB}},
--{"frsp.", XRC(63,12,1), XRA_MASK, COM, {FRT, FRB}},
--
--{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, {FRT, FRB}},
--{"fcir", XRC(63,14,0), XRA_MASK, POWER2, {FRT, FRB}},
--{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, {FRT, FRB}},
--{"fcir.", XRC(63,14,1), XRA_MASK, POWER2, {FRT, FRB}},
--
--{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, {FRT, FRB}},
--{"fcirz", XRC(63,15,0), XRA_MASK, POWER2, {FRT, FRB}},
--{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, {FRT, FRB}},
--{"fcirz.", XRC(63,15,1), XRA_MASK, POWER2, {FRT, FRB}},
--
--{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
--{"fd", A(63,18,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
--{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
--{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
--
--{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
--{"fs", A(63,20,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
--{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
--{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
--
--{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
--{"fa", A(63,21,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
--{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
--{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
--
--{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, {FRT, FRB}},
--{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, {FRT, FRB}},
--
--{"fsel", A(63,23,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
--{"fsel.", A(63,23,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
--
--{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}},
--{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}},
--
--{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, {FRT, FRA, FRC}},
--{"fm", A(63,25,0), AFRB_MASK, PWRCOM, {FRT, FRA, FRC}},
--{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, {FRT, FRA, FRC}},
--{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, {FRT, FRA, FRC}},
--
--{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}},
--{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}},
--
--{"fmsub", A(63,28,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
--{"fms", A(63,28,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
--{"fmsub.", A(63,28,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
--{"fms.", A(63,28,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
--
--{"fmadd", A(63,29,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
--{"fma", A(63,29,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
--{"fmadd.", A(63,29,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
--{"fma.", A(63,29,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
--
--{"fnmsub", A(63,30,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
--{"fnms", A(63,30,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
--{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
--{"fnms.", A(63,30,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
--
--{"fnmadd", A(63,31,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
--{"fnma", A(63,31,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
--{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
--{"fnma.", A(63,31,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
--
--{"fcmpo", X(63,32), X_MASK|(3<<21), COM, {BF, FRA, FRB}},
--
--{"dmulq", XRC(63,34,0), X_MASK, POWER6, {FRT, FRA, FRB}},
--{"dmulq.", XRC(63,34,1), X_MASK, POWER6, {FRT, FRA, FRB}},
--
--{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
--{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
--
--{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, {BT}},
--{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, {BT}},
--
--{"fneg", XRC(63,40,0), XRA_MASK, COM, {FRT, FRB}},
--{"fneg.", XRC(63,40,1), XRA_MASK, COM, {FRT, FRB}},
--
--{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, {BF, BFA}},
--
--{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, {FRT, FRA, SH16}},
--{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, {FRT, FRA, SH16}},
--
--{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, {TE, FRT, FRB, RMC}},
--{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, {TE, FRT, FRB, RMC}},
--
--{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, {BT}},
--{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, {BT}},
--
--{"fmr", XRC(63,72,0), XRA_MASK, COM, {FRT, FRB}},
--{"fmr.", XRC(63,72,1), XRA_MASK, COM, {FRT, FRB}},
--
--{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, {FRT, FRA, SH16}},
--{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, {FRT, FRA, SH16}},
--
--{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
--{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
--
--{"dcmpoq", X(63,130), X_MASK, POWER6, {BF, FRA, FRB}},
--
--{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, {BFF, U, W}},
--{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, {BFF, U, W}},
--
--{"fnabs", XRC(63,136,0), XRA_MASK, COM, {FRT, FRB}},
--{"fnabs.", XRC(63,136,1), XRA_MASK, COM, {FRT, FRB}},
--
--{"dtstexq", X(63,162), X_MASK, POWER6, {BF, FRA, FRB}},
--{"dtstdcq", Z(63,194), Z_MASK, POWER6, {BF, FRA, DCM}},
--{"dtstdgq", Z(63,226), Z_MASK, POWER6, {BF, FRA, DGM}},
--
--{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
--{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
--
--{"dctqpq", XRC(63,258,0), X_MASK, POWER6, {FRT, FRB}},
--{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, {FRT, FRB}},
--
--{"fabs", XRC(63,264,0), XRA_MASK, COM, {FRT, FRB}},
--{"fabs.", XRC(63,264,1), XRA_MASK, COM, {FRT, FRB}},
--
--{"dctfixq", XRC(63,290,0), X_MASK, POWER6, {FRT, FRB}},
--{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, {FRT, FRB}},
--
--{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, {SP, FRT, FRB}},
--{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, {SP, FRT, FRB}},
--
--{"dxexq", XRC(63,354,0), X_MASK, POWER6, {FRT, FRB}},
--{"dxexq.", XRC(63,354,1), X_MASK, POWER6, {FRT, FRB}},
--
--{"frin", XRC(63,392,0), XRA_MASK, POWER5, {FRT, FRB}},
--{"frin.", XRC(63,392,1), XRA_MASK, POWER5, {FRT, FRB}},
--{"friz", XRC(63,424,0), XRA_MASK, POWER5, {FRT, FRB}},
--{"friz.", XRC(63,424,1), XRA_MASK, POWER5, {FRT, FRB}},
--{"frip", XRC(63,456,0), XRA_MASK, POWER5, {FRT, FRB}},
--{"frip.", XRC(63,456,1), XRA_MASK, POWER5, {FRT, FRB}},
--{"frim", XRC(63,488,0), XRA_MASK, POWER5, {FRT, FRB}},
--{"frim.", XRC(63,488,1), XRA_MASK, POWER5, {FRT, FRB}},
--
--{"dsubq", XRC(63,514,0), X_MASK, POWER6, {FRT, FRA, FRB}},
--{"dsubq.", XRC(63,514,1), X_MASK, POWER6, {FRT, FRA, FRB}},
--
--{"ddivq", XRC(63,546,0), X_MASK, POWER6, {FRT, FRA, FRB}},
--{"ddivq.", XRC(63,546,1), X_MASK, POWER6, {FRT, FRA, FRB}},
--
--{"mffs", XRC(63,583,0), XRARB_MASK, COM, {FRT}},
--{"mffs.", XRC(63,583,1), XRARB_MASK, COM, {FRT}},
--
--{"dcmpuq", X(63,642), X_MASK, POWER6, {BF, FRA, FRB}},
--
--{"dtstsfq", X(63,674), X_MASK, POWER6, {BF, FRA, FRB}},
--
--{"mtfsf", XFL(63,711,0), XFL_MASK, COM, {FLM, FRB, XFL_L, W}},
--{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, {FLM, FRB, XFL_L, W}},
--
--{"drdpq", XRC(63,770,0), X_MASK, POWER6, {FRT, FRB}},
--{"drdpq.", XRC(63,770,1), X_MASK, POWER6, {FRT, FRB}},
--
--{"dcffixq", XRC(63,802,0), X_MASK, POWER6, {FRT, FRB}},
--{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, {FRT, FRB}},
--
--{"fctid", XRC(63,814,0), XRA_MASK, PPC64, {FRT, FRB}},
--{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, {FRT, FRB}},
--
--{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, {FRT, FRB}},
--{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, {FRT, FRB}},
--
--{"denbcdq", XRC(63,834,0), X_MASK, POWER6, {S, FRT, FRB}},
--{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, {S, FRT, FRB}},
-+{"attn", X(0,256), X_MASK, POWER4, PPCNONE, {0}},
-+{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
-+{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
-+{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
-+{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
-+{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
-+{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
-+{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
-+{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
-+{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
-+{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
-+{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
-+{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
-+{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
-+{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
-+{"tdi", OP(2), OP_MASK, PPC64, PPCNONE, {TO, RA, SI}},
-+
-+{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
-+{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
-+{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
-+{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
-+{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
-+{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
-+{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
-+{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
-+{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
-+{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
-+{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
-+{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
-+{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
-+{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
-+{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
-+{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
-+{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
-+{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
-+{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
-+{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
-+{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
-+{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
-+{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
-+{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
-+{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
-+{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
-+{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
-+{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
-+{"twi", OP(3), OP_MASK, PPCCOM, PPCNONE, {TO, RA, SI}},
-+{"ti", OP(3), OP_MASK, PWRCOM, PPCNONE, {TO, RA, SI}},
-+
-+{"ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
-+{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vrlb", VX (4, 4), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}},
-+{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}},
-+{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"mulhhwu", XRC(4, 8,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"mulhhwu.", XRC(4, 8,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
-+{"machhwu", XO (4, 12,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
-+{"machhwu.", XO (4, 12,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
-+{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
-+{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
-+{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
-+{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
-+{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
-+{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
-+{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
-+{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
-+{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
-+{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
-+{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
-+{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
-+{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
-+{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
-+{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
-+{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
-+{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
-+{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}},
-+{"vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, SHB}},
-+{"ps_sel", A (4, 23,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VC, VB}},
-+{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VC, VB}},
-+{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
-+{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
-+{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
-+{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
-+{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
-+{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
-+{"ps_msub", A (4, 28,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"ps_madd", A (4, 29,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
-+{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vrlh", VX (4, 68), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}},
-+{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}},
-+{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
-+{"mulhhw", XRC(4, 40,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
-+{"mulhhw.", XRC(4, 40,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"machhw", XO (4, 44,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"machhw.", XO (4, 44,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmachhw", XO (4, 46,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmachhw.", XO (4, 46,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
-+{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vrlw", VX (4, 132), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
-+{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
-+{"machhwsu", XO (4, 76,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"machhwsu.", XO (4, 76,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
-+{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"machhws", XO (4, 108,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"machhws.", XO (4, 108,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmachhws", XO (4, 110,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmachhws.", XO (4, 110,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vslb", VX (4, 260), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vrefp", VX (4, 266), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
-+{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
-+{"mulchwu", XRC(4, 136,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
-+{"mulchwu.", XRC(4, 136,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"macchwu", XO (4, 140,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"macchwu.", XO (4, 140,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vslh", VX (4, 324), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vrsqrtefp", VX (4, 330), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
-+{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"mulchw", XRC(4, 168,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"mulchw.", XRC(4, 168,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"macchw", XO (4, 172,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"macchw.", XO (4, 172,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmacchw", XO (4, 174,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmacchw.", XO (4, 174,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vslw", VX (4, 388), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vexptefp", VX (4, 394), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
-+{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"macchwsu", XO (4, 204,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"macchwsu.", XO (4, 204,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"vsl", VX (4, 452), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vlogefp", VX (4, 458), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
-+{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"macchws", XO (4, 236,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"macchws.", XO (4, 236,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmacchws", XO (4, 238,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmacchws.", XO (4, 238,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"evaddw", VX (4, 512), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}},
-+{"vminub", VX (4, 514), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evsubw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RB, RA}},
-+{"vsrb", VX (4, 516), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, UIMM, RB}},
-+{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}},
-+{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evabs", VX (4, 520), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evneg", VX (4, 521), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"evextsb", VX (4, 522), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"vrfin", VX (4, 522), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
-+{"evextsh", VX (4, 523), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"evrndw", VX (4, 524), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"vspltb", VX (4, 524), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
-+{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"vupkhsb", VX (4, 526), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
-+{"brinc", VX (4, 527), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
-+{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
-+{"evand", VX (4, 529), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evandc", VX (4, 530), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evxor", VX (4, 534), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmr", VX (4, 535), VX_MASK, PPCSPE, PPCNONE, {RS, RA, BBA}},
-+{"evor", VX (4, 535), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evnor", VX (4, 536), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evnot", VX (4, 536), VX_MASK, PPCSPE, PPCNONE, {RS, RA, BBA}},
-+{"get", APU(4, 268,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
-+{"eveqv", VX (4, 537), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evorc", VX (4, 539), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evnand", VX (4, 542), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evsrws", VX (4, 545), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}},
-+{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}},
-+{"evslw", VX (4, 548), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evslwi", VX (4, 550), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}},
-+{"evrlw", VX (4, 552), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evsplati", VX (4, 553), VX_MASK, PPCSPE, PPCNONE, {RS, SIMM}},
-+{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}},
-+{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, PPCNONE, {RS, SIMM}},
-+{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
-+{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
-+{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
-+{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
-+{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
-+{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
-+{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vminuh", VX (4, 578), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vsrh", VX (4, 580), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vrfiz", VX (4, 586), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
-+{"vsplth", VX (4, 588), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
-+{"vupkhsh", VX (4, 590), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
-+{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
-+{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, PPCNONE, {RS, RA, RB, CRFS}},
-+{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
-+{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vadduws", VX (4, 640), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evfssub", VX (4, 641), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vminuw", VX (4, 642), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"vsrw", VX (4, 644), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vrfip", VX (4, 650), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
-+{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
-+{"vspltw", VX (4, 652), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
-+{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
-+{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
-+{"vupklsb", VX (4, 654), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
-+{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
-+{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
-+{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
-+{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
-+{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
-+{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
-+{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
-+{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
-+{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
-+{"put", APU(4, 332,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
-+{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, PPCNONE, {RS, RB}},
-+{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
-+{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
-+{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}},
-+{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
-+{"efsadd", VX (4, 704), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
-+{"efssub", VX (4, 705), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
-+{"efsabs", VX (4, 708), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
-+{"vsr", VX (4, 708), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
-+{"efsneg", VX (4, 710), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
-+{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"efsmul", VX (4, 712), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
-+{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
-+{"vrfim", VX (4, 714), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
-+{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
-+{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
-+{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
-+{"vupklsh", VX (4, 718), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
-+{"efscfd", VX (4, 719), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efscfui", VX (4, 720), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efsctui", VX (4, 724), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
-+{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efststgt", VX (4, 732), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
-+{"efststlt", VX (4, 733), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
-+{"efststeq", VX (4, 734), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
-+{"efdadd", VX (4, 736), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
-+{"efdsub", VX (4, 737), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
-+{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efdabs", VX (4, 740), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
-+{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
-+{"efdneg", VX (4, 742), VX_MASK, PPCEFS, PPCNONE, {RS, RA}},
-+{"efdmul", VX (4, 744), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
-+{"efddiv", VX (4, 745), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}},
-+{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
-+{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
-+{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
-+{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efdctui", VX (4, 756), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
-+{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, PPCNONE, {RS, RB}},
-+{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
-+{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
-+{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}},
-+{"evlddx", VX (4, 768), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evldd", VX (4, 769), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
-+{"evldwx", VX (4, 770), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vminsb", VX (4, 770), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evldw", VX (4, 771), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
-+{"evldhx", VX (4, 772), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vsrab", VX (4, 772), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evldh", VX (4, 773), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
-+{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}},
-+{"vcfux", VX (4, 778), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
-+{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vspltisb", VX (4, 780), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}},
-+{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}},
-+{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}},
-+{"mullhwu", XRC(4, 392,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"mullhwu.", XRC(4, 392,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
-+{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
-+{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
-+{"maclhwu", XO (4, 396,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"maclhwu.", XO (4, 396,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
-+{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
-+{"evstddx", VX (4, 800), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evstdd", VX (4, 801), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
-+{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evstdw", VX (4, 803), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
-+{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evstdh", VX (4, 805), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}},
-+{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
-+{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evstwho", VX (4, 821), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
-+{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
-+{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}},
-+{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vminsh", VX (4, 834), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vsrah", VX (4, 836), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
-+{"vspltish", VX (4, 844), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}},
-+{"vupkhpx", VX (4, 846), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
-+{"mullhw", XRC(4, 424,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"mullhw.", XRC(4, 424,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"maclhw", XO (4, 428,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"maclhw.", XO (4, 428,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmaclhw", XO (4, 430,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmaclhw.", XO (4, 430,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vminsw", VX (4, 898), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vsraw", VX (4, 900), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
-+{"vspltisw", VX (4, 908), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}},
-+{"maclhwsu", XO (4, 460,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"maclhwsu.", XO (4, 460,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}},
-+{"vupklpx", VX (4, 974), VX_MASK, PPCVEC, PPCNONE, {VD, VB}},
-+{"maclhws", XO (4, 492,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"maclhws.", XO (4, 492,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmaclhws", XO (4, 494,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmaclhws.", XO (4, 494,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"vsububm", VX (4,1024), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vavgub", VX (4,1026), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vand", VX (4,1028), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
-+{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
-+{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vslo", VX (4,1036), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"machhwuo", XO (4, 12,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"machhwuo.", XO (4, 12,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
-+{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
-+{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vavguh", VX (4,1090), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vandc", VX (4,1092), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
-+{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
-+{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vminfp", VX (4,1098), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vsro", VX (4,1100), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"machhwo", XO (4, 44,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"machhwo.", XO (4, 44,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"nmachhwo", XO (4, 46,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmachhwo.", XO (4, 46,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
-+{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
-+{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vavguw", VX (4,1154), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vor", VX (4,1156), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
-+{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
-+{"machhwsuo", XO (4, 76,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"machhwsuo.", XO (4, 76,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
-+{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
-+{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"evmra", VX (4,1220), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"vxor", VX (4,1220), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evdivws", VX (4,1222), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
-+{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
-+{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, PPCNONE, {RS, RA}},
-+{"machhwso", XO (4, 108,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"machhwso.", XO (4, 108,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmachhwso", XO (4, 110,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmachhwso.", XO (4, 110,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
-+{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
-+{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vnor", VX (4,1284), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
-+{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
-+{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"macchwuo", XO (4, 140,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"macchwuo.", XO (4, 140,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
-+{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
-+{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"macchwo", XO (4, 172,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"macchwo.", XO (4, 172,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"nmacchwo", XO (4, 174,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmacchwo.", XO (4, 174,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
-+{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
-+{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"macchwsuo", XO (4, 204,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"macchwsuo.", XO (4, 204,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
-+{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}},
-+{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"macchwso", XO (4, 236,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"macchwso.", XO (4, 236,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
-+{"nmacchwso", XO (4, 238,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmacchwso.", XO (4, 238,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"vsububs", VX (4,1536), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"mfvscr", VX (4,1540), VX_MASK, PPCVEC, PPCNONE, {VD}},
-+{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
-+{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
-+{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"mtvscr", VX (4,1604), VX_MASK, PPCVEC, PPCNONE, {VB}},
-+{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
-+{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
-+{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
-+{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
-+{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
-+{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
-+{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
-+{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
-+{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"maclhwuo", XO (4, 396,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"maclhwuo.", XO (4, 396,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
-+{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
-+{"maclhwo", XO (4, 428,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"maclhwo.", XO (4, 428,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmaclhwo", XO (4, 430,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmaclhwo.", XO (4, 430,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
-+{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
-+{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"maclhwsuo", XO (4, 460,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"maclhwsuo.", XO (4, 460,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
-+{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
-+{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}},
-+{"maclhwso", XO (4, 492,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"maclhwso.", XO (4, 492,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmaclhwso", XO (4, 494,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}},
-+{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, PPCNONE, {RA, RB}},
-+
-+{"mulli", OP(7), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
-+{"muli", OP(7), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
-+
-+{"subfic", OP(8), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
-+{"sfi", OP(8), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
-+
-+{"dozi", OP(9), OP_MASK, M601, PPCNONE, {RT, RA, SI}},
-+
-+{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UI}},
-+{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UI}},
-+{"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UI}},
-+{"cmpli", OP(10), OP_MASK, PWRCOM, PPCNONE, {BF, RA, UI}},
-+
-+{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, SI}},
-+{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, SI}},
-+{"cmpi", OP(11), OP_MASK, PPC, PPCNONE, {BF, L, RA, SI}},
-+{"cmpi", OP(11), OP_MASK, PWRCOM, PPCNONE, {BF, RA, SI}},
-+
-+{"addic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
-+{"ai", OP(12), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
-+{"subic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}},
-+
-+{"addic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
-+{"ai.", OP(13), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
-+{"subic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}},
-+
-+{"li", OP(14), DRA_MASK, PPCCOM, PPCNONE, {RT, SI}},
-+{"lil", OP(14), DRA_MASK, PWRCOM, PPCNONE, {RT, SI}},
-+{"addi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SI}},
-+{"cal", OP(14), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
-+{"subi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}},
-+{"la", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}},
-+
-+{"lis", OP(15), DRA_MASK, PPCCOM, PPCNONE, {RT, SISIGNOPT}},
-+{"liu", OP(15), DRA_MASK, PWRCOM, PPCNONE, {RT, SISIGNOPT}},
-+{"addis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SISIGNOPT}},
-+{"cau", OP(15), OP_MASK, PWRCOM, PPCNONE, {RT, RA0, SISIGNOPT}},
-+{"subis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}},
-+
-+{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
-+{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
-+{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}},
-+{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}},
-+{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
-+{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
-+{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}},
-+{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}},
-+{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
-+{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
-+{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}},
-+{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}},
-+{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
-+{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
-+{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}},
-+{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}},
-+{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
-+{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
-+{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCNONE, {BD}},
-+{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
-+{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
-+{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCNONE, {BD}},
-+{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
-+{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
-+{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCNONE, {BDA}},
-+{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
-+{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
-+{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCNONE, {BDA}},
-+
-+{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
-+{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
-+{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
-+{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
-+
-+{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
-+{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
-+{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
-+{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
-+{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
-+{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
-+{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
-+{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
-+{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
-+{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
-+
-+{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}},
-+{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}},
-+{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
-+{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}},
-+{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}},
-+{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
-+{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}},
-+{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}},
-+{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
-+{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}},
-+{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}},
-+{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
-+{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}},
-+{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}},
-+{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
-+{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}},
-+{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}},
-+{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
-+{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}},
-+{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}},
-+{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
-+{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}},
-+{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}},
-+{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
-+
-+{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
-+{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
-+{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
-+{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
-+{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
-+{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
-+{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
-+{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
-+{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
-+{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
-+{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
-+{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
-+{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
-+{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
-+{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
-+{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
-+
-+{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}},
-+{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}},
-+{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
-+{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}},
-+{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}},
-+{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
-+{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}},
-+{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}},
-+{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
-+{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}},
-+{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}},
-+{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
-+{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}},
-+{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}},
-+{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
-+{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}},
-+{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}},
-+{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
-+{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}},
-+{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}},
-+{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
-+{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}},
-+{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}},
-+{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
-+
-+{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
-+{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
-+{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
-+{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
-+{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
-+{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
-+{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
-+{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
-+{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
-+{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
-+{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
-+{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
-+{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
-+{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
-+{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
-+{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
-+
-+{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}},
-+{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}},
-+{"bc", B(16,0,0), B_MASK, COM, PPCNONE, {BO, BI, BD}},
-+{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}},
-+{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}},
-+{"bcl", B(16,0,1), B_MASK, COM, PPCNONE, {BO, BI, BD}},
-+{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}},
-+{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}},
-+{"bca", B(16,1,0), B_MASK, COM, PPCNONE, {BO, BI, BDA}},
-+{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}},
-+{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}},
-+{"bcla", B(16,1,1), B_MASK, COM, PPCNONE, {BO, BI, BDA}},
-+
-+{"svc", SC(17,0,0), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
-+{"svcl", SC(17,0,1), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
-+{"sc", SC(17,1,0), SC_MASK, PPC, PPCNONE, {LEV}},
-+{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCNONE, {SV}},
-+{"svcla", SC(17,1,1), SC_MASK, POWER, PPCNONE, {SV}},
-+
-+{"b", B(18,0,0), B_MASK, COM, PPCNONE, {LI}},
-+{"bl", B(18,0,1), B_MASK, COM, PPCNONE, {LI}},
-+{"ba", B(18,1,0), B_MASK, COM, PPCNONE, {LIA}},
-+{"bla", B(18,1,1), B_MASK, COM, PPCNONE, {LIA}},
-+
-+{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}},
-+
-+{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
-+{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}},
-+{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
-+{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}},
-+{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}},
-+{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}},
-+{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
-+{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}},
-+{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
-+{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}},
-+{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}},
-+{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}},
-+{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
-+{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}},
-+{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
-+{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}},
-+{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}},
-+{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}},
-+{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}},
-+{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}},
-+{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}},
-+{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}},
-+{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}},
-+{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}},
-+
-+{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
-+{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+
-+{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
-+{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
-+{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
-+{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
-+{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
-+{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
-+{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
-+{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
-+{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
-+{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
-+{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
-+{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
-+{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
-+{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
-+{"bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
-+{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
-+{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
-+{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
-+{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
-+{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
-+{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
-+{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
-+{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
-+{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
-+
-+{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
-+{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
-+{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
-+{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
-+{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
-+{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
-+{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
-+{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
-+
-+{"rfid", XL(19,18), 0xffffffff, PPC64, PPCNONE, {0}},
-+
-+{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}},
-+{"crnor", XL(19,33), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
-+{"rfmci", X(19,38), 0xffffffff, PPCRFMCI, PPCNONE, {0}},
-+
-+{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCNONE, {0}},
-+{"rfi", XL(19,50), 0xffffffff, COM, PPCNONE, {0}},
-+{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300, PPCNONE, {0}},
-+
-+{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCNONE, {0}},
-+
-+{"rfgi", XL(19,102), 0xffffffff, E500MC, PPCNONE, {0}},
-+
-+{"crandc", XL(19,129), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
-+
-+{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCNONE, {0}},
-+{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCNONE, {0}},
-+
-+{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}},
-+{"crxor", XL(19,193), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
-+
-+{"dnh", X(19,198), X_MASK, E500MC, PPCNONE, {DUI, DUIS}},
-+
-+{"crnand", XL(19,225), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
-+
-+{"crand", XL(19,257), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
-+
-+{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPCNONE, {0}},
-+
-+{"crset", XL(19,289), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}},
-+{"creqv", XL(19,289), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
-+
-+{"doze", XL(19,402), 0xffffffff, POWER6, PPCNONE, {0}},
-+
-+{"crorc", XL(19,417), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
-+
-+{"nap", XL(19,434), 0xffffffff, POWER6, PPCNONE, {0}},
-+
-+{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}},
-+{"cror", XL(19,449), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
-+
-+{"sleep", XL(19,466), 0xffffffff, POWER6, PPCNONE, {0}},
-+{"rvwinkle", XL(19,498), 0xffffffff, POWER6, PPCNONE, {0}},
-+
-+{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCNONE, {0}},
-+{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCNONE, {0}},
-+
-+{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
-+{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}},
-+{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}},
-+
-+{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
-+{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
-+{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
-+{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
-+{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
-+{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
-+{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
-+{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
-+{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}},
-+{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
-+{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
-+{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
-+{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}},
-+
-+{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
-+{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
-+{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
-+{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
-+{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
-+{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
-+{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
-+{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
-+
-+{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
-+{"rlimi", M(20,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
-+
-+{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
-+{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
-+
-+{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
-+{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}},
-+{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
-+{"rlinm", M(21,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
-+{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
-+{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}},
-+{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
-+{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
-+
-+{"rlmi", M(22,0), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}},
-+{"rlmi.", M(22,1), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}},
-+
-+{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
-+{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
-+{"rlnm", M(23,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
-+{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
-+{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
-+{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
-+
-+{"nop", OP(24), 0xffffffff, PPCCOM, PPCNONE, {0}},
-+{"ori", OP(24), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
-+{"oril", OP(24), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
-+
-+{"oris", OP(25), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
-+{"oriu", OP(25), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
-+
-+{"xori", OP(26), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
-+{"xoril", OP(26), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
-+
-+{"xoris", OP(27), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
-+{"xoriu", OP(27), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
-+
-+{"andi.", OP(28), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
-+{"andil.", OP(28), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
-+
-+{"andis.", OP(29), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
-+{"andiu.", OP(29), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
-+
-+{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
-+{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}},
-+{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
-+{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
-+{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}},
-+{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
-+
-+{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}},
-+{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}},
-+
-+{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
-+{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
-+
-+{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
-+{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
-+
-+{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}},
-+{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}},
-+{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}},
-+{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}},
-+
-+{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}},
-+{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}},
-+
-+{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
-+{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
-+{"cmp", X(31,0), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}},
-+{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPCNONE, {BF, RA, RB}},
-+
-+{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
-+{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-+{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
-+{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-+{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
-+{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-+{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
-+{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-+{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
-+{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-+{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
-+{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-+{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
-+{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-+{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
-+{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-+{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
-+{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-+{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
-+{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-+{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
-+{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-+{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
-+{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-+{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
-+{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-+{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
-+{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-+{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, PPCNONE, {0}},
-+{"tw", X(31,4), X_MASK, PPCCOM, PPCNONE, {TO, RA, RB}},
-+{"t", X(31,4), X_MASK, PWRCOM, PPCNONE, {TO, RA, RB}},
-+
-+{"lvsl", X(31,6), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
-+{"lvebx", X(31,7), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
-+{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+{"subc", XO(31,8,0,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
-+{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
-+
-+{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-+{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-+
-+{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"a", XO(31,10,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+
-+{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+
-+{"isellt", X(31,15), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}},
-+
-+{"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM, POWER4, {RT}},
-+{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}},
-+{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, PPCNONE, {RT, FXM}},
-+
-+{"lwarx", X(31,20), XEH_MASK, PPC, PPCNONE, {RT, RA0, RB, EH}},
-+
-+{"ldx", X(31,21), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}},
-+
-+{"icbt", X(31,22), X_MASK, BOOKE|PPCE300, PPCNONE, {CT, RA, RB}},
-+
-+{"lwzx", X(31,23), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
-+{"lx", X(31,23), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+
-+{"slw", XRC(31,24,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
-+{"sl", XRC(31,24,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
-+{"slw.", XRC(31,24,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
-+{"sl.", XRC(31,24,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
-+
-+{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
-+{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
-+{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
-+{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
-+
-+{"sld", XRC(31,27,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
-+{"sld.", XRC(31,27,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
-+
-+{"and", XRC(31,28,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-+{"and.", XRC(31,28,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-+
-+{"maskg", XRC(31,29,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+{"maskg.", XRC(31,29,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+
-+{"ldepx", X(31,29), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
-+{"lwepx", X(31,31), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
-+
-+{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
-+{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
-+{"cmpl", X(31,32), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}},
-+{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPCNONE, {BF, RA, RB}},
-+
-+{"lvsr", X(31,38), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
-+{"lvehx", X(31,39), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
-+{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"iselgt", X(31,47), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}},
-+
-+{"lvewx", X(31,71), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
-+
-+{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, PPCNONE, {RT, RA, RB}},
-+
-+{"iseleq", X(31,79), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}},
-+
-+{"isel", XISEL(31,15), XISEL_MASK, PPCISEL, PPCNONE, {RT, RA, RB, CRB}},
-+
-+{"subf", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+{"sub", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
-+{"subf.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+{"sub.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
-+
-+{"lbarx", X(31,52), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}},
-+
-+{"ldux", X(31,53), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}},
-+
-+{"dcbst", X(31,54), XRT_MASK, PPC, PPCNONE, {RA, RB}},
-+
-+{"lwzux", X(31,55), X_MASK, PPCCOM, PPCNONE, {RT, RAL, RB}},
-+{"lux", X(31,55), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+
-+{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
-+{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
-+
-+{"andc", XRC(31,60,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-+{"andc.", XRC(31,60,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-+
-+{"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC, PPCNONE, {0}},
-+{"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC, PPCNONE, {0}},
-+{"wait", X(31,62), XWC_MASK, POWER7|E500MC, PPCNONE, {WC}},
-+
-+{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
-+
-+{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
-+{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
-+{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
-+{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
-+{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
-+{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
-+{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
-+{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
-+{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
-+{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
-+{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
-+{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
-+{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
-+{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
-+{"td", X(31,68), X_MASK, PPC64, PPCNONE, {TO, RA, RB}},
-+
-+{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-+{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-+
-+{"mulhw", XO(31,75,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+
-+{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, PPCNONE, {RA, RS, RB}},
-+{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, PPCNONE, {RA, RS, RB}},
-+
-+{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, PPCNONE, {SR, RS}},
-+
-+{"mfmsr", X(31,83), XRARB_MASK, COM, PPCNONE, {RT}},
-+
-+{"ldarx", X(31,84), XEH_MASK, PPC64, PPCNONE, {RT, RA0, RB, EH}},
-+
-+{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPCNONE, {RA, RB}},
-+{"dcbf", X(31,86), XLRT_MASK, PPC, PPCNONE, {RA, RB, L}},
-+
-+{"lbzx", X(31,87), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
-+
-+{"lbepx", X(31,95), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
-+
-+{"lvx", X(31,103), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
-+{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"neg", XO(31,104,0,0), XORB_MASK, COM, PPCNONE, {RT, RA}},
-+{"neg.", XO(31,104,0,1), XORB_MASK, COM, PPCNONE, {RT, RA}},
-+
-+{"mul", XO(31,107,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-+{"mul.", XO(31,107,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-+
-+{"mtsrdin", X(31,114), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
-+
-+{"lharx", X(31,116), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}},
-+
-+{"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}},
-+
-+{"lbzux", X(31,119), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
-+
-+{"popcntb", X(31,122), XRB_MASK, POWER5, PPCNONE, {RA, RS}},
-+
-+{"not", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
-+{"nor", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-+{"not.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
-+{"nor.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-+
-+{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
-+
-+{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE, PPCNONE, {RS}},
-+
-+{"dcbtstls", X(31,134), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
-+
-+{"stvebx", X(31,135), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
-+{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+
-+{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+
-+{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
-+
-+{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}},
-+{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}},
-+{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}},
-+
-+{"mtmsr", X(31,146), XRLARB_MASK, COM, PPCNONE, {RS, A_L}},
-+
-+{"stdx", X(31,149), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}},
-+
-+{"stwcx.", XRC(31,150,1), X_MASK, PPC, PPCNONE, {RS, RA0, RB}},
-+
-+{"stwx", X(31,151), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}},
-+{"stx", X(31,151), X_MASK, PWRCOM, PPCNONE, {RS, RA, RB}},
-+
-+{"slq", XRC(31,152,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+{"slq.", XRC(31,152,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+
-+{"sle", XRC(31,153,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+{"sle.", XRC(31,153,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+
-+{"prtyw", X(31,154), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
-+
-+{"stdepx", X(31,157), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
-+
-+{"stwepx", X(31,159), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
-+
-+{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE, PPCNONE, {E}},
-+
-+{"dcbtls", X(31,166), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
-+
-+{"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
-+{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"dcbtlse", X(31,174), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
-+
-+{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, PPCNONE, {RS, A_L}},
-+
-+{"stdux", X(31,181), X_MASK, PPC64, PPCNONE, {RS, RAS, RB}},
-+
-+{"stwux", X(31,183), X_MASK, PPCCOM, PPCNONE, {RS, RAS, RB}},
-+{"stux", X(31,183), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
-+
-+{"sliq", XRC(31,184,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
-+{"sliq.", XRC(31,184,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
-+
-+{"prtyd", X(31,186), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
-+
-+{"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
-+{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
-+{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-+{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
-+{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-+
-+{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
-+{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-+{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
-+{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-+
-+{"msgsnd", XRTRA(31,206,0,0),XRTRA_MASK,E500MC, PPCNONE, {RB}},
-+
-+{"mtsr", X(31,210), XRB_MASK|(1<<20), COM32, PPCNONE, {SR, RS}},
-+
-+{"stdcx.", XRC(31,214,1), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}},
-+
-+{"stbx", X(31,215), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
-+
-+{"sllq", XRC(31,216,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+{"sllq.", XRC(31,216,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+
-+{"sleq", XRC(31,217,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+{"sleq.", XRC(31,217,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+
-+{"stbepx", X(31,223), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
-+
-+{"icblc", X(31,230), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
-+
-+{"stvx", X(31,231), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
-+{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
-+{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-+{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
-+{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-+
-+{"mulld", XO(31,233,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-+{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-+
-+{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
-+{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-+{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
-+{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-+
-+{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+
-+{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC, PPCNONE, {RB}},
-+{"icblce", X(31,238), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
-+{"mtsrin", X(31,242), XRA_MASK, PPC32, PPCNONE, {RS, RB}},
-+{"mtsri", X(31,242), XRA_MASK, POWER32, PPCNONE, {RS, RB}},
-+
-+{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}},
-+{"dcbtst", X(31,246), X_MASK, PPC, POWER4, {CT, RA, RB}},
-+{"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA, RB, CT}},
-+
-+{"stbux", X(31,247), X_MASK, COM, PPCNONE, {RS, RAS, RB}},
-+
-+{"slliq", XRC(31,248,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
-+{"slliq.", XRC(31,248,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
-+
-+{"bpermd", X(31,252), X_MASK, POWER7, PPCNONE, {RA, RS, RB}},
-+
-+{"dcbtstep", XRT(31,255,0), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
-+
-+{"mfdcrx", X(31,259), X_MASK, BOOKE, PPCNONE, {RS, RA}},
-+
-+{"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}},
-+
-+{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+{"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-+{"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-+
-+{"add", XO(31,266,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+
-+{"ehpriv", X(31,270), 0xffffffff, E500MC, PPCNONE, {0}},
-+
-+{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPCNONE, {RB, L}},
-+
-+{"mfapidi", X(31,275), X_MASK, BOOKE, PPCNONE, {RT, RA}},
-+
-+{"lscbx", XRC(31,277,0), X_MASK, M601, PPCNONE, {RT, RA, RB}},
-+{"lscbx.", XRC(31,277,1), X_MASK, M601, PPCNONE, {RT, RA, RB}},
-+
-+{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}},
-+{"dcbt", X(31,278), X_MASK, PPC, POWER4, {CT, RA, RB}},
-+{"dcbt", X(31,278), X_MASK, POWER4, PPCNONE, {RA, RB, CT}},
-+
-+{"lhzx", X(31,279), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
-+
-+{"cdtbcd", X(31,282), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
-+
-+{"eqv", XRC(31,284,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-+{"eqv.", XRC(31,284,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-+
-+{"lhepx", X(31,287), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
-+
-+{"mfdcrux", X(31,291), X_MASK, PPC464, PPCNONE, {RS, RA}},
-+
-+{"tlbie", X(31,306), XRTLRA_MASK, PPC, PPCNONE, {RB, L}},
-+{"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}},
-+
-+{"eciwx", X(31,310), X_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+
-+{"lhzux", X(31,311), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
-+
-+{"cbcdtd", X(31,314), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
-+
-+{"xor", XRC(31,316,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-+{"xor.", XRC(31,316,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-+
-+{"dcbtep", XRT(31,319,0), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
-+
-+{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE, PPCNONE, {RT, SPR}},
-+
-+{"div", XO(31,331,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-+{"div.", XO(31,331,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-+
-+{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
-+
-+{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, PPCNONE, {RT, PMR}},
-+
-+{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}},
-+{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, PPCNONE, {RT}},
-+{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, PPCNONE, {RT}},
-+{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, PPCNONE, {RT}},
-+{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, PPCNONE, {RT}},
-+{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, PPCNONE, {RT}},
-+{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, PPCNONE, {RT}},
-+{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}},
-+{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, PPCNONE, {RT}},
-+{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, PPCNONE, {RT}},
-+{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, PPCNONE, {RT}},
-+{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, PPCNONE, {RT}},
-+{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, PPCNONE, {RT}},
-+{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, PPCNONE, {RT}},
-+{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, PPCNONE, {RT}},
-+{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, PPCNONE, {RT}},
-+{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, PPCNONE, {RT}},
-+{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, PPCNONE, {RT, SPRG}},
-+{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
-+{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
-+{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
-+{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
-+{"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, PPCNONE, {RT}},
-+{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, PPCNONE, {RT}},
-+{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, PPCNONE, {RT}},
-+{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, PPCNONE, {RT}},
-+{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, PPCNONE, {RT}},
-+{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, PPCNONE, {RT}},
-+{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, PPCNONE, {RT}},
-+{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-+{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
-+{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, PPCNONE, {RT}},
-+{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, PPCNONE, {RT}},
-+{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
-+{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, PPCNONE, {RT, SPRBAT}},
-+{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
-+{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, PPCNONE, {RT, SPRBAT}},
-+{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
-+{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, PPCNONE, {RT}},
-+{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, PPCNONE, {RT, SPRBAT}},
-+{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, PPCNONE, {RT, SPRBAT}},
-+{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
-+{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
-+{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
-+{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
-+{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, PPCNONE, {RT}},
-+{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, PPCNONE, {RT}},
-+{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, PPCNONE, {RT}},
-+{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, PPCNONE, {RT}},
-+{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, PPCNONE, {RT}},
-+{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, PPCNONE, {RT}},
-+{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, PPCNONE, {RT}},
-+{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, PPCNONE, {RT}},
-+{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, PPCNONE, {RT}},
-+{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, PPCNONE, {RT}},
-+{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, PPCNONE, {RT}},
-+{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, PPCNONE, {RT}},
-+{"mfspr", X(31,339), X_MASK, COM, PPCNONE, {RT, SPR}},
-+
-+{"lwax", X(31,341), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}},
-+
-+{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
-+
-+{"lhax", X(31,343), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
-+
-+{"lvxl", X(31,359), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
-+
-+{"abs", XO(31,360,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
-+{"abs.", XO(31,360,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
-+
-+{"divs", XO(31,363,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-+{"divs.", XO(31,363,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-+
-+{"tlbia", X(31,370), 0xffffffff, PPC, PPCNONE, {0}},
-+
-+{"mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, PPCNONE, {RT}},
-+{"mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, PPCNONE, {RT}},
-+{"mftb", X(31,371), X_MASK, CLASSIC, POWER7, {RT, TBR}},
-+
-+{"lwaux", X(31,373), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}},
-+
-+{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
-+
-+{"lhaux", X(31,375), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
-+
-+{"popcntw", X(31,378), XRB_MASK, POWER7, PPCNONE, {RA, RS}},
-+
-+{"mtdcrx", X(31,387), X_MASK, BOOKE, PPCNONE, {RA, RS}},
-+
-+{"dcblc", X(31,390), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
-+{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"divdeu", XO(31,393,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
-+{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
-+{"divweu", XO(31,395,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
-+{"divweu.", XO(31,395,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
-+
-+{"dcblce", X(31,398), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
-+
-+{"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
-+
-+{"sthx", X(31,407), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
-+
-+{"orc", XRC(31,412,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-+{"orc.", XRC(31,412,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-+
-+{"sthepx", X(31,415), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
-+
-+{"mtdcrux", X(31,419), X_MASK, PPC464, PPCNONE, {RA, RS}},
-+
-+{"divde", XO(31,425,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
-+{"divde.", XO(31,425,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
-+{"divwe", XO(31,427,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
-+{"divwe.", XO(31,427,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
-+
-+{"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}},
-+
-+{"ecowx", X(31,438), X_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+
-+{"sthux", X(31,439), X_MASK, COM, PPCNONE, {RS, RAS, RB}},
-+
-+{"mdors", 0x7f9ce378, 0xffffffff, E500MC, PPCNONE, {0}},
-+
-+{"mr", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
-+{"or", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-+{"mr.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
-+{"or.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-+
-+{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE, PPCNONE, {SPR, RS}},
-+
-+{"dccci", X(31,454), XRT_MASK, PPC403|PPC440, PPCNONE, {RA, RB}},
-+
-+{"divdu", XO(31,457,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-+{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-+
-+{"divwu", XO(31,459,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+{"divwu.", XO(31,459,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+
-+{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, PPCNONE, {PMR, RS}},
-+
-+{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}},
-+{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, PPCNONE, {RS}},
-+{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, PPCNONE, {RS}},
-+{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, PPCNONE, {RS}},
-+{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, PPCNONE, {RS}},
-+{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, PPCNONE, {RS}},
-+{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, PPCNONE, {RS}},
-+{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, PPCNONE, {RS}},
-+{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, PPCNONE, {RS}},
-+{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, PPCNONE, {RS}},
-+{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, PPCNONE, {RS}},
-+{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, PPCNONE, {RS}},
-+{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, PPCNONE, {RS}},
-+{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, PPCNONE, {RS}},
-+{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, PPCNONE, {RS}},
-+{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, PPCNONE, {RS}},
-+{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, PPCNONE, {RS}},
-+{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, PPCNONE, {RS}},
-+{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, PPCNONE, {RS}},
-+{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, PPCNONE, {RS}},
-+{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, PPCNONE, {RS}},
-+{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, PPCNONE, {RS}},
-+{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, PPCNONE, {RS}},
-+{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, PPCNONE, {RS}},
-+{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, PPCNONE, {RS}},
-+{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, PPCNONE, {RS}},
-+{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, PPCNONE, {RS}},
-+{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, PPCNONE, {RS}},
-+{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, PPCNONE, {RS}},
-+{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, PPCNONE, {RS}},
-+{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, PPCNONE, {RS}},
-+{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, PPCNONE, {RS}},
-+{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, PPCNONE, {SPRG, RS}},
-+{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, PPCNONE, {RS}},
-+{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, PPCNONE, {RS}},
-+{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, PPCNONE, {RS}},
-+{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, PPCNONE, {RS}},
-+{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
-+{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
-+{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
-+{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
-+{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, PPCNONE, {RS}},
-+{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, PPCNONE, {RS}},
-+{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, PPCNONE, {RS}},
-+{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, PPCNONE, {RS}},
-+{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-+{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
-+{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, PPCNONE, {RS}},
-+{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, PPCNONE, {RS}},
-+{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
-+{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, PPCNONE, {SPRBAT, RS}},
-+{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
-+{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, PPCNONE, {SPRBAT, RS}},
-+{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
-+{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, PPCNONE, {RS}},
-+{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, PPCNONE, {SPRBAT, RS}},
-+{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, PPCNONE, {SPRBAT, RS}},
-+{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
-+{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
-+{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
-+{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, PPCNONE, {RS}},
-+{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, PPCNONE, {RS}},
-+{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, PPCNONE, {RS}},
-+{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, PPCNONE, {RS}},
-+{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, PPCNONE, {RS}},
-+{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, PPCNONE, {RS}},
-+{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, PPCNONE, {RS}},
-+{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, PPCNONE, {RS}},
-+{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, PPCNONE, {RS}},
-+{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, PPCNONE, {RS}},
-+{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, PPCNONE, {RS}},
-+{"mtspr", X(31,467), X_MASK, COM, PPCNONE, {SPR, RS}},
-+
-+{"dcbi", X(31,470), XRT_MASK, PPC, PPCNONE, {RA, RB}},
-+
-+{"nand", XRC(31,476,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-+{"nand.", XRC(31,476,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-+
-+{"dsn", X(31,483), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
-+
-+{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCNONE, {RT, RA, RB}},
-+
-+{"icbtls", X(31,486), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
-+
-+{"stvxl", X(31,487), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
-+
-+{"nabs", XO(31,488,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
-+{"nabs.", XO(31,488,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
-+
-+{"divd", XO(31,489,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-+{"divd.", XO(31,489,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-+
-+{"divw", XO(31,491,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+{"divw.", XO(31,491,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+
-+{"icbtlse", X(31,494), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
-+
-+{"slbia", X(31,498), 0xffffffff, PPC64, PPCNONE, {0}},
-+
-+{"cli", X(31,502), XRB_MASK, POWER, PPCNONE, {RT, RA}},
-+
-+{"popcntd", X(31,506), XRB_MASK, POWER7, PPCNONE, {RA, RS}},
-+
-+{"cmpb", X(31,508), X_MASK, POWER6, PPCNONE, {RA, RS, RB}},
-+
-+{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, POWER7, {BF}},
-+
-+{"lbdx", X(31,515), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
-+
-+{"bblels", X(31,518), X_MASK, PPCBRLK, PPCNONE, {0}},
-+
-+{"lvlx", X(31,519), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
-+{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+{"subco", XO(31,8,1,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
-+{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+{"subco.", XO(31,8,1,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
-+
-+{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+
-+{"clcs", X(31,531), XRB_MASK, M601, PPCNONE, {RT, RA}},
-+
-+{"ldbrx", X(31,532), X_MASK, CELL|POWER7, PPCNONE, {RT, RA0, RB}},
-+
-+{"lswx", X(31,533), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
-+{"lsx", X(31,533), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+
-+{"lwbrx", X(31,534), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
-+{"lbrx", X(31,534), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+
-+{"lfsx", X(31,535), X_MASK, COM, PPCNONE, {FRT, RA0, RB}},
-+
-+{"srw", XRC(31,536,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
-+{"sr", XRC(31,536,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
-+{"srw.", XRC(31,536,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
-+{"sr.", XRC(31,536,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
-+
-+{"rrib", XRC(31,537,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+{"rrib.", XRC(31,537,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+
-+{"srd", XRC(31,539,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
-+{"srd.", XRC(31,539,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
-+
-+{"maskir", XRC(31,541,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+{"maskir.", XRC(31,541,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+
-+{"lhdx", X(31,547), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
-+
-+{"bbelr", X(31,550), X_MASK, PPCBRLK, PPCNONE, {0}},
-+
-+{"lvrx", X(31,551), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
-+{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"subfo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+{"subo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
-+{"subfo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+{"subo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
-+
-+{"tlbsync", X(31,566), 0xffffffff, PPC, PPCNONE, {0}},
-+
-+{"lfsux", X(31,567), X_MASK, COM, PPCNONE, {FRT, RAS, RB}},
-+
-+{"lwdx", X(31,579), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
-+
-+{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
-+
-+{"mfsr", X(31,595), XRB_MASK|(1<<20), COM32, PPCNONE, {RT, SR}},
-+
-+{"lswi", X(31,597), X_MASK, PPCCOM, PPCNONE, {RT, RA0, NB}},
-+{"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}},
-+
-+{"msync", X(31,598), 0xffffffff, BOOKE, PPCNONE, {0}},
-+{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, PPCNONE, {0}},
-+{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}},
-+{"sync", X(31,598), XSYNC_MASK, PPCCOM, PPCNONE, {LS}},
-+{"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}},
-+
-+{"lfdx", X(31,599), X_MASK, COM, PPCNONE, {FRT, RA0, RB}},
-+
-+{"lfdepx", X(31,607), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}},
-+{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
-+
-+{"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
-+
-+{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"nego", XO(31,104,1,0), XORB_MASK, COM, PPCNONE, {RT, RA}},
-+{"nego.", XO(31,104,1,1), XORB_MASK, COM, PPCNONE, {RT, RA}},
-+
-+{"mulo", XO(31,107,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-+{"mulo.", XO(31,107,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-+
-+{"lxsdux", X(31,620), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
-+
-+{"mfsri", X(31,627), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+
-+{"dclst", X(31,630), XRB_MASK, PWRCOM, PPCNONE, {RS, RA}},
-+
-+{"lfdux", X(31,631), X_MASK, COM, PPCNONE, {FRT, RAS, RB}},
-+
-+{"stbdx", X(31,643), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
-+
-+{"stvlx", X(31,647), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
-+{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+
-+{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+
-+{"mfsrin", X(31,659), XRA_MASK, PPC32, PPCNONE, {RT, RB}},
-+
-+{"stdbrx", X(31,660), X_MASK, CELL|POWER7, PPCNONE, {RS, RA0, RB}},
-+
-+{"stswx", X(31,661), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}},
-+{"stsx", X(31,661), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
-+
-+{"stwbrx", X(31,662), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}},
-+{"stbrx", X(31,662), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
-+
-+{"stfsx", X(31,663), X_MASK, COM, PPCNONE, {FRS, RA0, RB}},
-+
-+{"srq", XRC(31,664,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+{"srq.", XRC(31,664,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+
-+{"sre", XRC(31,665,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+{"sre.", XRC(31,665,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+
-+{"sthdx", X(31,675), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
-+
-+{"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
-+{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"stbcx.", XRC(31,694,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
-+
-+{"stfsux", X(31,695), X_MASK, COM, PPCNONE, {FRS, RAS, RB}},
-+
-+{"sriq", XRC(31,696,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
-+{"sriq.", XRC(31,696,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
-+
-+{"stwdx", X(31,707), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
-+
-+{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
-+
-+{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
-+{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-+{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
-+{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-+
-+{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
-+{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-+{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
-+{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-+
-+{"stswi", X(31,725), X_MASK, PPCCOM, PPCNONE, {RS, RA0, NB}},
-+{"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}},
-+
-+{"sthcx.", XRC(31,726,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
-+
-+{"stfdx", X(31,727), X_MASK, COM, PPCNONE, {FRS, RA0, RB}},
-+
-+{"srlq", XRC(31,728,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+{"srlq.", XRC(31,728,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+
-+{"sreq", XRC(31,729,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+{"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+
-+{"stfdepx", X(31,735), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}},
-+{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
-+
-+{"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
-+
-+{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"stxsdux", X(31,748), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
-+
-+{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
-+{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-+{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
-+{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-+
-+{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-+{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-+
-+{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
-+{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-+{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
-+{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-+
-+{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+
-+{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE, PPCNONE, {RA, RB}},
-+{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
-+
-+{"stfdux", X(31,759), X_MASK, COM, PPCNONE, {FRS, RAS, RB}},
-+
-+{"srliq", XRC(31,760,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
-+{"srliq.", XRC(31,760,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
-+
-+{"lvlxl", X(31,775), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
-+{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"dozo", XO(31,264,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-+{"dozo.", XO(31,264,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-+
-+{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
-+{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+
-+{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
-+
-+{"tlbivax", X(31,786), XRT_MASK, BOOKE, PPCNONE, {RA, RB}},
-+{"tlbilx", X(31,787), X_MASK, E500MC, PPCNONE, {T, RA0, RB}},
-+{"tlbilxlpid", XTO(31,787,0), XTO_MASK, E500MC, PPCNONE, {0}},
-+{"tlbilxpid", XTO(31,787,1), XTO_MASK, E500MC, PPCNONE, {0}},
-+{"tlbilxva", XTO(31,787,3), XTO_MASK, E500MC, PPCNONE, {RA0, RB}},
-+
-+{"lwzcix", X(31,789), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
-+
-+{"lhbrx", X(31,790), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
-+
-+{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRT, RA, RB}},
-+{"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
-+
-+{"sraw", XRC(31,792,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
-+{"sra", XRC(31,792,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
-+{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
-+{"sra.", XRC(31,792,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
-+
-+{"srad", XRC(31,794,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
-+{"srad.", XRC(31,794,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
-+
-+{"lfddx", X(31,803), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}},
-+
-+{"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
-+
-+{"lxvw4ux", X(31,812), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
-+
-+{"rac", X(31,818), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-+
-+{"lhzcix", X(31,821), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
-+
-+{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, PPCNONE, {STRM}},
-+
-+{"lfqux", X(31,823), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
-+
-+{"srawi", XRC(31,824,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
-+{"srai", XRC(31,824,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}},
-+{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
-+{"srai.", XRC(31,824,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}},
-+
-+{"sradi", XS(31,413,0), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
-+{"sradi.", XS(31,413,1), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
-+
-+{"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-+{"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-+
-+{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
-+
-+{"slbmfev", X(31,851), XRA_MASK, PPC64, PPCNONE, {RT, RB}},
-+
-+{"lbzcix", X(31,853), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
-+
-+{"mbar", X(31,854), X_MASK, BOOKE, PPCNONE, {MO}},
-+{"eieio", X(31,854), 0xffffffff, PPC, PPCNONE, {0}},
-+
-+{"lfiwax", X(31,855), X_MASK, POWER6, PPCNONE, {FRT, RA0, RB}},
-+
-+{"abso", XO(31,360,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
-+{"abso.", XO(31,360,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
-+
-+{"divso", XO(31,363,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-+{"divso.", XO(31,363,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-+
-+{"lxvd2ux", X(31,876), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
-+
-+{"ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
-+
-+{"lfiwzx", X(31,887), X_MASK, POWER7, PPCNONE, {FRT, RA0, RB}},
-+
-+{"stvlxl", X(31,903), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
-+{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-+
-+{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
-+{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
-+{"divweuo", XO(31,395,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
-+{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
-+
-+{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
-+
-+{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, PPCNONE, {RTO, RA, RB}},
-+{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, PPCNONE, {RTO, RA, RB}},
-+
-+{"slbmfee", X(31,915), XRA_MASK, PPC64, PPCNONE, {RT, RB}},
-+
-+{"stwcix", X(31,917), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
-+
-+{"sthbrx", X(31,918), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
-+
-+{"stfdpx", X(31,919), X_MASK, POWER6, PPCNONE, {FRS, RA, RB}},
-+{"stfqx", X(31,919), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}},
-+
-+{"sraq", XRC(31,920,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+{"sraq.", XRC(31,920,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+
-+{"srea", XRC(31,921,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+{"srea.", XRC(31,921,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-+
-+{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
-+{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
-+{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
-+{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
-+
-+{"stfddx", X(31,931), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}},
-+
-+{"stvrxl", X(31,935), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
-+
-+{"divdeo", XO(31,425,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
-+{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
-+{"divweo", XO(31,427,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
-+{"divweo.", XO(31,427,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
-+
-+{"stxvw4ux", X(31,940), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
-+
-+{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
-+{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
-+{"tlbre", X(31,946), X_MASK, PPC403|BOOKE, PPCNONE, {RSO, RAOPT, SHO}},
-+
-+{"sthcix", X(31,949), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
-+
-+{"stfqux", X(31,951), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}},
-+
-+{"sraiq", XRC(31,952,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
-+{"sraiq.", XRC(31,952,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
-+
-+{"extsb", XRC(31,954,0), XRB_MASK, PPC, PPCNONE, {RA, RS}},
-+{"extsb.", XRC(31,954,1), XRB_MASK, PPC, PPCNONE, {RA, RS}},
-+
-+{"iccci", X(31,966), XRT_MASK, PPC403|PPC440, PPCNONE, {RA, RB}},
-+
-+{"divduo", XO(31,457,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-+{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-+
-+{"divwuo", XO(31,459,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+
-+{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
-+
-+{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
-+{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
-+{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE, PPCNONE, {RSO, RAOPT, SHO}},
-+{"tlbld", X(31,978), XRTRA_MASK, PPC, PPCNONE, {RB}},
-+
-+{"stbcix", X(31,981), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
-+
-+{"icbi", X(31,982), XRT_MASK, PPC, PPCNONE, {RA, RB}},
-+
-+{"stfiwx", X(31,983), X_MASK, PPC, PPCNONE, {FRS, RA0, RB}},
-+
-+{"extsw", XRC(31,986,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
-+{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
-+
-+{"icbiep", XRT(31,991,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
-+
-+{"icread", X(31,998), XRT_MASK, PPC403|PPC440, PPCNONE, {RA, RB}},
-+
-+{"nabso", XO(31,488,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
-+{"nabso.", XO(31,488,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
-+
-+{"divdo", XO(31,489,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-+{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-+
-+{"divwo", XO(31,491,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+{"divwo.", XO(31,491,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-+
-+{"stxvd2ux", X(31,1004), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
-+
-+{"tlbli", X(31,1010), XRTRA_MASK, PPC, PPCNONE, {RB}},
-+
-+{"stdcix", X(31,1013), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
-+
-+{"dcbz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}},
-+{"dclz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}},
-+
-+{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
-+
-+{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4, PPCNONE, {RA, RB}},
-+{"dcbzl", XOPL(31,1014,1), XRT_MASK, PPCCOM|E500MC,POWER4, {RA, RB}},
-+
-+{"cctpl", 0x7c210b78, 0xffffffff, CELL, PPCNONE, {0}},
-+{"cctpm", 0x7c421378, 0xffffffff, CELL, PPCNONE, {0}},
-+{"cctph", 0x7c631b78, 0xffffffff, CELL, PPCNONE, {0}},
-+
-+{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
-+{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
-+{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, PPCNONE, {0}},
-+
-+{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, PPCNONE, {0}},
-+{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, PPCNONE, {0}},
-+{"db12cyc", 0x7fdef378, 0xffffffff, CELL, PPCNONE, {0}},
-+{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, PPCNONE, {0}},
-+
-+{"lwz", OP(32), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}},
-+{"l", OP(32), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
-+
-+{"lwzu", OP(33), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAL}},
-+{"lu", OP(33), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
-+
-+{"lbz", OP(34), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
-+
-+{"lbzu", OP(35), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
-+
-+{"stw", OP(36), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}},
-+{"st", OP(36), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
-+
-+{"stwu", OP(37), OP_MASK, PPCCOM, PPCNONE, {RS, D, RAS}},
-+{"stu", OP(37), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
-+
-+{"stb", OP(38), OP_MASK, COM, PPCNONE, {RS, D, RA0}},
-+
-+{"stbu", OP(39), OP_MASK, COM, PPCNONE, {RS, D, RAS}},
-+
-+{"lhz", OP(40), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
-+
-+{"lhzu", OP(41), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
-+
-+{"lha", OP(42), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
-+
-+{"lhau", OP(43), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
-+
-+{"sth", OP(44), OP_MASK, COM, PPCNONE, {RS, D, RA0}},
-+
-+{"sthu", OP(45), OP_MASK, COM, PPCNONE, {RS, D, RAS}},
-+
-+{"lmw", OP(46), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAM}},
-+{"lm", OP(46), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
-+
-+{"stmw", OP(47), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}},
-+{"stm", OP(47), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
-+
-+{"lfs", OP(48), OP_MASK, COM, PPCNONE, {FRT, D, RA0}},
-+
-+{"lfsu", OP(49), OP_MASK, COM, PPCNONE, {FRT, D, RAS}},
-+
-+{"lfd", OP(50), OP_MASK, COM, PPCNONE, {FRT, D, RA0}},
-+
-+{"lfdu", OP(51), OP_MASK, COM, PPCNONE, {FRT, D, RAS}},
-+
-+{"stfs", OP(52), OP_MASK, COM, PPCNONE, {FRS, D, RA0}},
-+
-+{"stfsu", OP(53), OP_MASK, COM, PPCNONE, {FRS, D, RAS}},
-+
-+{"stfd", OP(54), OP_MASK, COM, PPCNONE, {FRS, D, RA0}},
-+
-+{"stfdu", OP(55), OP_MASK, COM, PPCNONE, {FRS, D, RAS}},
-+
-+{"lq", OP(56), OP_MASK, POWER4, PPCNONE, {RTQ, DQ, RAQ}},
-+
-+{"lfq", OP(56), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
-+
-+{"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
-+
-+{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRT, D, RA0}},
-+
-+{"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
-+
-+{"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
-+
-+{"ld", DSO(58,0), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}},
-+{"ldu", DSO(58,1), DS_MASK, PPC64, PPCNONE, {RT, DS, RAL}},
-+{"lwa", DSO(58,2), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}},
-+
-+{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+
-+{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}},
-+{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}},
-+
-+{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}},
-+{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}},
-+
-+{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}},
-+{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}},
-+
-+{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}},
-+{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}},
-+
-+{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, PPCNONE, {FRT, FRB}},
-+{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, PPCNONE, {FRT, FRB}},
-+
-+{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
-+{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
-+{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+
-+{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCNONE, {FRT, FRA, FRC}},
-+{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCNONE, {FRT, FRA, FRC}},
-+
-+{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
-+{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
-+{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+
-+{"fmsubs", A(59,28,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
-+
-+{"fmadds", A(59,29,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"fmadds.", A(59,29,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
-+
-+{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
-+
-+{"fnmadds", A(59,31,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
-+
-+{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+
-+{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
-+{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
-+
-+{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
-+{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
-+
-+{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}},
-+{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}},
-+
-+{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
-+{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
-+
-+{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
-+{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
-+
-+{"dcmpo", X(59,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
-+
-+{"dtstex", X(59,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
-+{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM}},
-+{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM}},
-+
-+{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
-+{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
-+
-+{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+
-+{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+
-+{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
-+{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
-+
-+{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+
-+{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+
-+{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+
-+{"dcmpu", X(59,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
-+
-+{"dtstsf", X(59,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
-+
-+{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+
-+{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+
-+{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
-+{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
-+
-+{"fcfids", XRC(59,846,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+
-+{"diex", XRC(59,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+
-+{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+
-+{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}},
-+{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}},
-+{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S, DMEX}},
-+{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
-+{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, DM}},
-+{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
-+{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
-+{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
-+{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
-+{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
-+{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
-+{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCNONE, {XT6, XB6, UIM}},
-+{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
-+{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
-+{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
-+{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
-+{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
-+{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-+
-+{"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
-+
-+{"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
-+
-+{"stfdp", OP(61), OP_MASK, POWER6, PPCNONE, {FRT, D, RA0}},
-+
-+{"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
-+
-+{"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
-+
-+{"std", DSO(62,0), DS_MASK, PPC64, PPCNONE, {RS, DS, RA0}},
-+{"stdu", DSO(62,1), DS_MASK, PPC64, PPCNONE, {RS, DS, RAS}},
-+{"stq", DSO(62,2), DS_MASK, POWER4, PPCNONE, {RSQ, DS, RA0}},
-+
-+{"fcmpu", X(63,0), X_MASK|(3<<21), COM, PPCNONE, {BF, FRA, FRB}},
-+
-+{"daddq", XRC(63,2,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+{"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+
-+{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
-+{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
-+
-+{"fcpsgn", XRC(63,8,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+
-+{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
-+{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
-+
-+{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}},
-+{"fcir", XRC(63,14,0), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}},
-+{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}},
-+{"fcir.", XRC(63,14,1), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}},
-+
-+{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}},
-+{"fcirz", XRC(63,15,0), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}},
-+{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}},
-+{"fcirz.", XRC(63,15,1), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}},
-+
-+{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}},
-+{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
-+{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}},
-+{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
-+
-+{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}},
-+{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
-+{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}},
-+{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
-+
-+{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}},
-+{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
-+{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}},
-+{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
-+
-+{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, PPCNONE, {FRT, FRB}},
-+{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, PPCNONE, {FRT, FRB}},
-+
-+{"fsel", A(63,23,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"fsel.", A(63,23,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}},
-+
-+{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
-+{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
-+{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+
-+{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC}},
-+{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}},
-+{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC}},
-+{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}},
-+
-+{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
-+{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
-+{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+
-+{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"fms", A(63,28,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
-+
-+{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"fma", A(63,29,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
-+
-+{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
-+
-+{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
-+{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
-+
-+{"fcmpo", X(63,32), X_MASK|(3<<21), COM, PPCNONE, {BF, FRA, FRB}},
-+
-+{"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+{"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+
-+{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
-+{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
-+
-+{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCNONE, {BT}},
-+{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCNONE, {BT}},
-+
-+{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
-+{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
-+
-+{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}},
-+
-+{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
-+{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
-+
-+{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT, FRB, RMC}},
-+{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRT, FRB, RMC}},
-+
-+{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCNONE, {BT}},
-+{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCNONE, {BT}},
-+
-+{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
-+{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
-+
-+{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
-+{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
-+
-+{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
-+{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
-+
-+{"ftdiv", X(63,128), X_MASK|(3<<21), POWER7, PPCNONE, {BF, FRA, FRB}},
-+
-+{"dcmpoq", X(63,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
-+
-+{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6, {BFF, U}},
-+{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6, PPCNONE, {BFF, U, W}},
-+{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6, {BFF, U}},
-+{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6, PPCNONE, {BFF, U, W}},
-+
-+{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
-+{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
-+
-+{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+
-+{"ftsqrt", X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE, {BF, FRB}},
-+
-+{"dtstexq", X(63,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
-+{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM}},
-+{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM}},
-+
-+{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
-+{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
-+
-+{"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+
-+{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
-+{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
-+
-+{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+
-+{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
-+{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
-+
-+{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+
-+{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
-+{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
-+{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
-+{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
-+{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
-+{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
-+{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
-+{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
-+
-+{"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+{"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+
-+{"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+{"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+
-+{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCNONE, {FRT}},
-+{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCNONE, {FRT}},
-+
-+{"dcmpuq", X(63,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
-+
-+{"dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
-+
-+{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6, {FLM, FRB}},
-+{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6, PPCNONE, {FLM, FRB, XFL_L, W}},
-+{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6, {FLM, FRB}},
-+{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6, PPCNONE, {FLM, FRB, XFL_L, W}},
-+
-+{"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+{"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+
-+{"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
-+
-+{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
-+{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
-+
-+{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
-+{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
-+
-+{"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
-+{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
-+
-+{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
-+{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
-+
-+{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-+{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-
--{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, {FRT, FRB}},
--{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, {FRT, FRB}},
-+{"fctidu", XRC(63,942,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-
--{"diexq", XRC(63,866,0), X_MASK, POWER6, {FRT, FRA, FRB}},
--{"diexq.", XRC(63,866,1), X_MASK, POWER6, {FRT, FRA, FRB}},
-+{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-
-+{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-+{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
- };
-
- const int powerpc_num_opcodes =
projects / crux-arm-cross-compiler.git / commitdiff