From c067e78f81f6de7fff6b6a3e1ab1986e2271ff06 Mon Sep 17 00:00:00 2001 From: Tilman Sauerbeck Date: Mon, 17 Jun 2019 08:05:55 +0200 Subject: [PATCH] common: Set SIM_SOPT2.PLLFLLSEL by default. At least the USB peripheral needs this, but probably others do, too. --- src/common/clock.rs | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/common/clock.rs b/src/common/clock.rs index c1bbb10..1bebbd1 100644 --- a/src/common/clock.rs +++ b/src/common/clock.rs @@ -28,8 +28,12 @@ type Reg32 = register::Register; const SIM_BASE: u32 = 0x40047000; +const SIM_SOPT2: u32 = SIM_BASE + 0x1004; + const SIM_CLKDIV1: u32 = SIM_BASE + 0x1044; +const SIM_SOPT2_PLLFLLSEL: u32 = 1 << 16; + const SIM_CLKDIV1_OUTDIV4_SHIFT: u32 = 16; const SIM_CLKDIV1_OUTDIV1_SHIFT: u32 = 28; @@ -145,4 +149,10 @@ pub unsafe fn configure() { switch_to_fbe(); switch_to_pbe(); switch_to_pee(); + + let mut sopt2 = Reg32::new(SIM_SOPT2); + + sopt2.modify(|v| { + v | SIM_SOPT2_PLLFLLSEL + }); } -- 2.30.2