X-Git-Url: http://git.code-monkey.de/?a=blobdiff_plain;f=src%2Fcommon%2Ffsl_common.h;h=5d61699a47695064b575ca52a83ab8e2fb50b0aa;hb=853beae392e40ee2843e7187500285da666f11e9;hp=a53dbc2713d14e0ecfe80a1e44f4cec82fd384b5;hpb=ce2821c45d209e454ae3249d0035f9921c11b6bc;p=gps-watch.git

diff --git a/src/common/fsl_common.h b/src/common/fsl_common.h
index a53dbc2..5d61699 100644
--- a/src/common/fsl_common.h
+++ b/src/common/fsl_common.h
@@ -168,12 +168,6 @@ enum _generic_status
 /*! @brief Type used for all status and error return values. */
 typedef int32_t status_t;
 
-/*
- * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
- * defined in previous of this file.
- */
-#include "fsl_clock.h"
-
 /*
  * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
  */
@@ -386,80 +380,9 @@ _Pragma("diag_suppress=Pm120")
 {
 #endif
 
-    /*!
-     * @brief Enable specific interrupt.
-     *
-     * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
-     * levels. For example, there are NVIC and intmux. Here the interrupts connected
-     * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
-     * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
-     * to NVIC first then routed to core.
-     *
-     * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
-     * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
-     *
-     * @param interrupt The IRQ number.
-     * @retval kStatus_Success Interrupt enabled successfully
-     * @retval kStatus_Fail Failed to enable the interrupt
-     */
-    static inline status_t EnableIRQ(IRQn_Type interrupt)
-    {
-        if (NotAvail_IRQn == interrupt)
-        {
-            return kStatus_Fail;
-        }
-
-#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
-        if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
-        {
-            return kStatus_Fail;
-        }
-#endif
-
-#if defined(__GIC_PRIO_BITS)
-        GIC_EnableIRQ(interrupt);
-#else
-        NVIC_EnableIRQ(interrupt);
-#endif
-        return kStatus_Success;
-    }
-
-    /*!
-     * @brief Disable specific interrupt.
-     *
-     * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
-     * levels. For example, there are NVIC and intmux. Here the interrupts connected
-     * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
-     * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
-     * to NVIC first then routed to core.
-     *
-     * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
-     * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
-     *
-     * @param interrupt The IRQ number.
-     * @retval kStatus_Success Interrupt disabled successfully
-     * @retval kStatus_Fail Failed to disable the interrupt
-     */
-    static inline status_t DisableIRQ(IRQn_Type interrupt)
+    static inline void __disable_irq(void)
     {
-        if (NotAvail_IRQn == interrupt)
-        {
-            return kStatus_Fail;
-        }
-
-#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
-        if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
-        {
-            return kStatus_Fail;
-        }
-#endif
-
-#if defined(__GIC_PRIO_BITS)
-        GIC_DisableIRQ(interrupt);
-#else
-    NVIC_DisableIRQ(interrupt);
-#endif
-        return kStatus_Success;
+        asm volatile("cpsid i" ::: "memory");
     }
 
     /*!