const SIM_BASE: u32 = 0x40047000;
+const SIM_SOPT1: u32 = SIM_BASE + 0x0000;
const SIM_SOPT2: u32 = SIM_BASE + 0x1004;
+const SIM_SCGC4: u32 = SIM_BASE + 0x1034;
const SIM_CLKDIV1: u32 = SIM_BASE + 0x1044;
+const SIM_SOPT1_USBREGEN: u32 = 1 << 31;
+
const SIM_SOPT2_PLLFLLSEL: u32 = 1 << 16;
+const SIM_SOPT2_USBSRC: u32 = 1 << 18;
+
+const SIM_SCGC4_USBOTG: u32 = 1 << 18;
const SIM_CLKDIV1_OUTDIV4_SHIFT: u32 = 16;
const SIM_CLKDIV1_OUTDIV1_SHIFT: u32 = 28;
const MCG_S_IREFST: u8 = 1 << 4;
const MCG_S_LOCK0: u8 = 1 << 6;
+const OSC0_CR: u32 = 0x40065000;
+
+const OSC_CR_ERCLKEN: u8 = 1 << 7;
+
fn configure_clkdiv() {
let mut clkdiv1 = Reg32::new(SIM_CLKDIV1);
- clkdiv1.write(1 << SIM_CLKDIV1_OUTDIV4_SHIFT);
- clkdiv1.modify(|v| v | (1 << SIM_CLKDIV1_OUTDIV1_SHIFT));
+ clkdiv1.write((1 << SIM_CLKDIV1_OUTDIV4_SHIFT)
+ | (1 << SIM_CLKDIV1_OUTDIV1_SHIFT));
}
fn switch_to_fbe() {
v | SIM_SOPT2_PLLFLLSEL
});
}
+
+pub unsafe fn reset() {
+ switch_to_pbe();
+ switch_to_fbe();
+}
+
+pub unsafe fn enable_osc0() {
+ Reg8::new(OSC0_CR).write(OSC_CR_ERCLKEN);
+}
+
+pub unsafe fn configure_usb() {
+ let mut scgc4 = Reg32::new(SIM_SCGC4);
+ scgc4.modify(|v| v & !SIM_SCGC4_USBOTG);
+
+ let mut sopt1 = Reg32::new(SIM_SOPT1);
+ sopt1.modify(|v| v | SIM_SOPT1_USBREGEN);
+
+ let mut sopt2 = Reg32::new(SIM_SOPT2);
+ sopt2.modify(|v| v | SIM_SOPT2_USBSRC);
+
+ scgc4.modify(|v| v | SIM_SCGC4_USBOTG);
+}