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Move trace view files
[pulseview.git]
/
pv
/
data
/
logicsegment.cpp
diff --git
a/pv/data/logicsegment.cpp
b/pv/data/logicsegment.cpp
index 5191a3f03e76a2654202f84039e18d574898b56e..b648f5d1c302af35c22c7c1dec35eaf08dee923e 100644
(file)
--- a/
pv/data/logicsegment.cpp
+++ b/
pv/data/logicsegment.cpp
@@
-20,9
+20,9
@@
#include <extdef.h>
#include <cassert>
#include <extdef.h>
#include <cassert>
-#include <cstring>
-#include <cstdlib>
#include <cmath>
#include <cmath>
+#include <cstdlib>
+#include <cstring>
#include "logic.hpp"
#include "logicsegment.hpp"
#include "logic.hpp"
#include "logicsegment.hpp"
@@
-33,8
+33,8
@@
using std::lock_guard;
using std::recursive_mutex;
using std::max;
using std::min;
using std::recursive_mutex;
using std::max;
using std::min;
-using std::pair;
using std::shared_ptr;
using std::shared_ptr;
+using std::vector;
using sigrok::Logic;
using sigrok::Logic;
@@
-44,17
+44,15
@@
namespace data {
const int LogicSegment::MipMapScalePower = 4;
const int LogicSegment::MipMapScaleFactor = 1 << MipMapScalePower;
const float LogicSegment::LogMipMapScaleFactor = logf(MipMapScaleFactor);
const int LogicSegment::MipMapScalePower = 4;
const int LogicSegment::MipMapScaleFactor = 1 << MipMapScalePower;
const float LogicSegment::LogMipMapScaleFactor = logf(MipMapScaleFactor);
-const uint64_t LogicSegment::MipMapDataUnit = 64
*
1024; // bytes
+const uint64_t LogicSegment::MipMapDataUnit = 64
*
1024; // bytes
-LogicSegment::LogicSegment(pv::data::Logic& owner,
shared_ptr<sigrok::Logic> data
,
+LogicSegment::LogicSegment(pv::data::Logic& owner,
unsigned int unit_size
,
uint64_t samplerate) :
uint64_t samplerate) :
- Segment(samplerate,
data->unit_size()
),
+ Segment(samplerate,
unit_size
),
owner_(owner),
last_append_sample_(0)
{
owner_(owner),
last_append_sample_(0)
{
- lock_guard<recursive_mutex> lock(mutex_);
memset(mip_map_, 0, sizeof(mip_map_));
memset(mip_map_, 0, sizeof(mip_map_));
- append_payload(data);
}
LogicSegment::~LogicSegment()
}
LogicSegment::~LogicSegment()
@@
-143,12
+141,19
@@
void LogicSegment::append_payload(shared_ptr<sigrok::Logic> logic)
assert(unit_size_ == logic->unit_size());
assert((logic->data_length() % unit_size_) == 0);
assert(unit_size_ == logic->unit_size());
assert((logic->data_length() % unit_size_) == 0);
+ append_payload(logic->data_pointer(), logic->data_length());
+}
+
+void LogicSegment::append_payload(void *data, uint64_t data_size)
+{
+ assert((data_size % unit_size_) == 0);
+
lock_guard<recursive_mutex> lock(mutex_);
uint64_t prev_sample_count = sample_count_;
lock_guard<recursive_mutex> lock(mutex_);
uint64_t prev_sample_count = sample_count_;
- uint64_t sample_count =
logic->data_length()
/ unit_size_;
+ uint64_t sample_count =
data_size
/ unit_size_;
- append_samples(
logic->data_pointer()
, sample_count);
+ append_samples(
data
, sample_count);
// Generate the first mip-map from the data
append_payload_to_mipmap();
// Generate the first mip-map from the data
append_payload_to_mipmap();
@@
-172,7
+177,7
@@
const uint8_t* LogicSegment::get_samples(int64_t start_sample,
lock_guard<recursive_mutex> lock(mutex_);
lock_guard<recursive_mutex> lock(mutex_);
- return get_raw_samples(start_sample, (end_sample
-
start_sample));
+ return get_raw_samples(start_sample, (end_sample
-
start_sample));
}
SegmentLogicDataIterator* LogicSegment::begin_sample_iteration(uint64_t start)
}
SegmentLogicDataIterator* LogicSegment::begin_sample_iteration(uint64_t start)
@@
-252,7
+257,7
@@
void LogicSegment::append_payload_to_mipmap()
// Compute higher level mipmaps
for (unsigned int level = 1; level < ScaleStepCount; level++) {
MipMapLevel &m = mip_map_[level];
// Compute higher level mipmaps
for (unsigned int level = 1; level < ScaleStepCount; level++) {
MipMapLevel &m = mip_map_[level];
- const MipMapLevel &ml = mip_map_[level
-
1];
+ const MipMapLevel &ml = mip_map_[level
-
1];
// Expand the data buffer to fit the new samples
prev_length = m.length;
// Expand the data buffer to fit the new samples
prev_length = m.length;
@@
-298,7
+303,7
@@
uint64_t LogicSegment::get_unpacked_sample(uint64_t index) const
}
void LogicSegment::get_subsampled_edges(
}
void LogicSegment::get_subsampled_edges(
-
std::
vector<EdgePair> &edges,
+ vector<EdgePair> &edges,
uint64_t start, uint64_t end,
float min_length, int sig_index)
{
uint64_t start, uint64_t end,
float min_length, int sig_index)
{